external crystal running at a nominal 25 MHz or from the CLK_OUT signal on the switch. When the Ethernet Switch is configured
for MAC-MAC communication, the switch provides the clocks and acts like a PHY.
Figure 20. MII interface connections
RMII signaling: RMII data is exchanged via 2-bit data signals TXD[1:0] and RXD[1:0] as shown in
Figure 21.
on page 23.
Transmit and receive signals are synchronous with the shared reference clock, REF_CLK.
Figure 21. RMII interface connections
8 Quad Serial Peripheral Interface
S32K1xx has one instance of QuadSPI. The Quad Serial Peripheral Interface (QuadSPI) block acts as an interface to external
serial flash device. It supports SDR and HyperRAM modes upto 4 and 8 bidirectional data lines respectively. The QuadSPI
supports an A-side and a B-side. The A-side of the QuadSPI is connected to the fast pads (80 mA) while the B-side connects to
the 20 mA pads. See datasheet for operating values.
Only one external memory will be supported in any given application and it will not be permitted to run the A-side and the B-side
of the QuadSPI simultaneously. As such the following external memory options can be supported:
• Single Quad Flash on the A-side
NXP Semiconductors
Quad Serial Peripheral Interface
Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018
Application Note
23 / 33
