5.2 RESET system
Resetting the MCU provides a way to start processing from a known set of initial conditions. System reset begins with the on-chip
regulator in full regulation and system clocking generation from an internal reference.
5.2.1 External pin RESET
For all reset sources, the RESET_B pin is driven low by the MCU for at least 128 bus clock cycles and until flash memory
initialization has completed.
After flash memory initialization has completed, the RESET_B pin is released and the internal chip reset desserts. Keeping the
RESET_B pin asserted externally delays the negation of the internal chip reset.
On this device, RESET is a dedicated pin. This pin is open drain and has an internal pull/up device. Asserting RESET wakes the
device from any mode. During a pin reset, the RCM's SRS[PIN] bit is set. Hence, application software can detect an external pin
RESET by reading this register.
In case RESET_PIN_CFG within Flash Option Register (FTFC_FOPT) is cleared, RESET_B pin is disabled following a POR and
cannot be enabled as reset function. When this option is selected, there could be a short period of contention during a POR ramp
where the device drives the pin low prior to establishing the setting of this option and releasing the reset function on the pin. The
RESET pin is the same as the standard GPIO. It can operate as a pseudo open-drain output because there is also a PMOS
device in the output stage.
This bit is preserved through system resets and low-power modes. When RESET_B pin function is disabled, it cannot be used
as a source for low-power mode wake-up.
When the reset pin has been disabled and security has been enabled by means of the FSEC register, a mass
erase can be performed only by setting both the Mass Erase and System Reset Request fields in the MDM-AP
register.
NOTE
The reset line has an internal pull-up resistor. If the environment and the customer application is noisy, an external pull up resistor
(between 10KOhmshms-100KOhms) can be added and to avoid a sporadic or unintended reset occurs. Refer to the device
datasheet for the value of the internal pull-up resistor value.
Despite a capacitor in the reset line is not directly required for the MCU. In some cases, in order to add a further ESD protection,
an external capacitor is added between the RESET pin to ground. The values of the pull up resistor and the capacitor must be
selected according to the design requirements of the application. Refer to the device datasheet for the minimum RESET pulse
value that can be detected for the MCU.
6 Analog comparator interface
The comparator (CMP) module provides a circuit for comparing two analog input voltages in the S32K1xx Microcontrollers. The
comparator circuit is designed to operate across the full range of the supply voltage, known as rail-to-rail operation.
CMPO is high
when the non-inverting input is greater than the inverting input, and is low when the non-inverting input is less than the inverting
input.
NXP Semiconductors
Analog comparator interface
Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018
Application Note
11 / 33
