NXP Semiconductors
UM11802
RDGD3162I3PH5EVB three-phase inverter reference design
Problem
Evaluation
Explanation
Corrective action(s)
Check VGE fault (VGE_FLT)
A short on IGBT or SiC module gate,
or too low of VGEMON delay setting
causes VGE fault, locking out PWM
control of the gate.
Clear VGE_FLT bit (STATUS2) to
continue. Increase VGEMON delay
setting (CONFIG6).
If safe operating condition can be
guaranteed, set VGE_FLTM (MSK2)
bit to logic 0, to mask fault.
No PWM output (fault reported)
Check for short-circuit fault (SC) in
STATUS1 register
SC is a severe fault that disables
PWM. SC fault cannot be masked
Clear SC fault to continue. Consider
adjusting SC fault settings on
GD3162:
•
Adjust short-circuit threshold
setting (CONFIG2)
•
Adjust short-circuit filter setting
(CONFIG2)
Check for dead time fault (DTFLT) in
STATUS2 register
Dead time is enforced, but fault
indicates that PWM controls signals
are in violation
Clear DTFLT fault bit (STATUS2).
Check phase U PWMALT weak
pull-downs R862 and R857 are
removed to bypass dead time faults
for SC testing.
Consider adjusting dead time settings
on GD3162:
•
Change mandatory PWM dead
time setting (CONFIG5)
•
Mask dead time fault (MSK2)
PWM output is good, but with
persistent fault reported
Check for overcurrent (OC) fault in
STATUS1 register
OC fault latches, but does not disable
PWM. OC fault cannot be masked.
Clear OC fault bit (STATUS1).
Adjust OC fault detection settings on
GD3162:
•
Adjust overcurrent threshold
setting (CONFIG1)
•
Adjust overcurrent filter setting
(CONFIG1)
PWM or FSSTATE rising edge has
longer delay than falling edge
Check translator output voltage
versus GD3162 VDD voltage
Low translator output voltage
(compared with correct VDD at
GD3162) causes the high threshold
at the GD3162 pin to be crossed later
than commanded
Check translator output voltage
selection (J3) is configured to the
same level as the GD3162 VDD
Check VCCSEL supply or translator
outputs on the translator board
for excessive loading or supply
droop/pulldown
WDOG_FLT reported on startup
Check VSUP and VCC are powered
On initialization, watchdog fault is
reported when one die is powered up
before the other
Check VSUP and VCC both have
power applied.
Clear WDOG_FLT bit (STATUS2) to
continue.
SPIERR reported on startup
Check KL25Z/translator connection
On initialization, SPIERR can occur
when the SPI bus is open, or when
GD3162 IC is powered up before the
translator (which provides CSB).
Clear SPIERR fault to continue.
Reinitialize power to GD3162 after
translator is powered (over USB).
Check bit length of message sent
There is SPIERR if SCLK does not
see a n*24 multiple of cycles
Use 24-bit message length for SPI
messages
Check CRC
SPIERR faults if CRC provided in
sent message is not good
Use FlexGUI to generate commands
with valid CRC. The command can be
copied in binary or hexadecimal and
sent from another program.
SPIERR reported after SPI message
Check for sufficient dead time
between SPI messages
SPIERR fault bit is set when the time
between SPI messages (txfer_delay)
received is too short. Minimum
required delay time is 19 µs.
Check time between CSB rising edge
(old message end) and CSB falling
edge (new message start) during
normal SPI read, and ensure transfer
delay dead time check.
SPIERR can also be cleared in BIST.
VCCUV reported on startup
Check VCC potential
Caused by low VCC
Clear VCCUV fault bit (STATUS1).
Tune VCC-GNDISO potential with
power supply set resistor (5 kΩ
potentiometer).
UM11802
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© NXP B.V. 2022. All rights reserved.
User manual
Rev. 1 — 10 June 2022
31 / 38
