NXP Semiconductors
UM11802
RDGD3162I3PH5EVB three-phase inverter reference design
Problem
Evaluation
Explanation
Corrective action(s)
Check that HV domain is powered
correctly
Related to slow rise time of VCC
supply on HV domain, or failed VREF
regulator
Clear VREFUV bit (STATUS2).
Reset HV domain supply if fault bit
does not clear.
VREFUV reported on startup
Check VCC for undervoltage
condition
Low VCC is visible indirectly through
other HV domain faults
Tune VCC-GNDISO using 5 kΩ
potentiometer feedback
Check VEE level on suspect domain. If VEE level is not at desired negative
voltage, it could cause excessive VCC
level.
Check Zener diode in power supply
circuit for proper value in setting VEE
level.
Clear VCCOV bit (STATUS1) to
continue.
VCCOV fault reported on startup
Check VCC-GNDISO potential
PWM is disabled during a VCC
overvoltage (23 V nom.)
Tune VCC-GNDISO potential to
suitable level with power supply set
resistor (5 kΩ potentiometer).
Clear VCCOV bit (STATUS1) to
continue.
No PWM during short circuit test
(phase U only)
Check PWM Alt resistor weak
pull-downs
Incorrect configuration of PWMALT
pins prevents short-circuit test by
enforcing dead time
For short-circuit test, remove resistors
R862 and R857 to bypass dead time.
(phase U only)
Check VSUP/VDD for undervoltage
condition
VDD_UV latches SPI buffer contents,
preventing updated fault reporting.
Check voltage provided at VDD pin
(pin 3).
On each read, compare the address
from the sent command and response
(a difference indicates that the SPI
response is latched due to inactive).
Read multiple addresses to ensure a
good comparison.
Check EN_PS is set to HIGH in
VCC/VEE can be enabled/disabled in
software.
Enable flyback VCC/VEE from
FlexGUI
Bad SPI data, appears to repeat
previous response
Check VCC for undervoltage
Unpowered VCC prevents HV domain
from updating data
Tune VCC-GNDISO using 5 kΩ
potentiometer feedback
8 Configuring the hardware
RDGD3162I3PH5EVB with KITGD316xTREVB attached as shown in
Windows based PC and FlexGUI software.
Note:
Double pulse and short-circuit testing can be conducted on phase U only. See
FlexGUI Pulse Tab,
Suggested equipment needed for test:
•
Rogowski coil high-current probe
•
High-voltage differential voltage probe
•
High sample rate digital oscilloscope with probes
•
DC link capacitor compatible with HybridPACK drive module
•
IGBT or SiC MOSFET HybridPACK drive module
•
Windows based PC
•
High-voltage DC power supply for DC link voltage
•
Low-voltage DC power supply for VPWR
–
+12 V DC gate drive board low-voltage domain
•
Voltmeter for monitoring high-voltage DC link supply
•
Load coil for double pulse testing (phase U only)
Note:
To enable short-circuit testing on phase U only, two resistors (R857, R862) must
be pulled from PWMALT phase U signals to disable deadtime control on phase U gate
drivers.
UM11802
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© NXP B.V. 2022. All rights reserved.
User manual
Rev. 1 — 10 June 2022
32 / 38
