NXP Semiconductors
UM11802
RDGD3162I3PH5EVB three-phase inverter reference design
6.2.5 Connectors and jumpers
Figure 6. RDGD3162I3PH5EVB connector and jumper locations
Name
Description
J9
solder jumper 1-2 default - DC supply for VSUP to gate drivers supplied through J99
terminal connection
jumper open VSUP supply to gate drivers isolated
J101
jumper 1-2 default master output slave input (MOSI) - normal mode three device daisy
chain three device high side, three device low side (× 3 - 2 channel)
jumper 2-3 MOSI - six device daisy chain all six gate drivers daisy chained together
(× 6 - 1 channel)
J102
jumper 1-2 default master input slave output (MISO) - normal mode three device daisy
chain three device high side, three device low side (× 3 - 2 channel)
jumper 2-3 MISO - six device daisy chain all six gate drivers daisy chained together
(× 6 - 1 channel)
J103
DC bus current measurement connection header
Phase current feedback
connector
current feedback connections from U, V, and W phases
Resolver signals connector
resolver excitation signals (see schematic for more information)
MCU signals
two-row header of all MCU signals for debug and development (see schematic for details)
PCIe/MCU connector
2 × 32 PCIe connector for easy connection to MPC5777CDEVB or MPC5744P via PCIe
cable (S32SDEV-CON18)
J99 VPWR terminal connector used for external low-voltage power supply connection, typically 12 V V
BAT
Table 4. RDGD3162I3PH5EVB connector and jumper descriptions
UM11802
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User manual
Rev. 1 — 10 June 2022
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