NXP Semiconductors
UM11802
RDGD3162I3PH5EVB three-phase inverter reference design
Pulse tab
•
Used for double pulse, short-circuit, and PWM testing
•
Select desired T1, T2, and T3 timings for each test type; select enable then generate
pulses
Note:
Phase U can be configured for performing double pulse and short-circuit testing.
To enable short-circuit testing, two resistors (R857, R862) must be pulled from PWMALT
phase U signals to disable deadtime control on phase U gate drivers.
Figure 24. Pulse tab
7.4 Troubleshooting
Some common issues and troubleshooting procedures are detailed in the following table.
This is not an exhaustive list by any means, and additional debug may be needed:
Problem
Evaluation
Explanation
Corrective action(s)
Check PWM jumper position on
translator board
Incorrect PWM jumpers obstruct
signal path but not report fault
Set PWMH_SEL (J4) and
PWML_SEL (J5) jumpers properly, for
desired control method:
•
3.3 V to 5.0 V translator board
Check PWM control signal
Ensure that proper PWM signal is
reaching GD3162
Monitor EXT_PWML (TP14) and
EXT_PWMH (TP15) for commanded
PWM state
Check FSENB status (see GD3162
pin 15, STATUS3)
PWM is disabled when
FSENB = LOW
Set pin FSENB = HIGH (pin 15) to
continue
No PWM output (no fault reported)
Check CONFIG_EN bit (MODE2)
PWM is disabled when CONFIG_EN
is logic 1
Write CONFIG_EN = logic 0 to
continue
UM11802
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User manual
Rev. 1 — 10 June 2022
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