NXP Semiconductors P5010, User Manual, Page: 56 / 77

P5040/P5020 Reference Design Board User Guide, Rev. 0
56 Freescale Semiconductor
Programming Model
7.1.9 Board Configuration Register (PX_BRDCFG0)
This register controls board configurations; they can be changed at any time.
Figure 30. Board Configuration Register 0 (PX_BRDCFG0)
0 1 2 3 4 5 6 7
R
I
2
C2_EN I
2
C4_nI
2
C2 NGI
2
C ACC I
2
C4_ISOLb PJWP_B
FLASHCS_SE
L0
FLASHCS_SE
L1
SD8X
W
Reset 1 0 0 1 0 0 0 1
Offset 0x08
Table 36. PX_BRDCFG0 Field Descriptions
Bits Name Description
0 I
2
C2_EN
Controls processor access to I
2
C2 connected devices: DDR1 SPD and DDR2
SPD.
• 0 - Inaccessible
• 1 - Accessible
1 I
2
C4_nI
2
C2
Controls I
2
C4 integration—if it is separated from or integrated into an I
2
C2 bus.
• 0 - Separated I
2
C4
1
• 1 - Integrated I
2
C4 = I
2
C2
1
Bit [1]: used for P5040/P5020.
2 NGI
2
C_ACC
Controls CPU access to I
2
C1 connected devices owned by ngPIXIS: FPGA,
EEPROM FPGA Configuration Data, and EEPROM FPGA ExConfiguration
Data.
• 0 - Inaccessible
• 1 - Accessible
3 I
2
C4_ISOLb
Controls processor access to I
2
C4 connected devices: Thermal Monitor, RTC,
1588 riser card, and FPGA.
• 0 - Inaccessible
• 1 - Accessible
4 PJWP_B
Controls write access to PROMJet.
• 0 - No access
• 1 - Access
5 FLASHCS_SEL0
Controls SPICS connections to Spansion HS SPI FLASH
S25FL129P0XNFI001 as per FLASHCS_SEL1. See
Table 37 .
6 FLASHCS_SEL1
Controls SPICS connection to Spansion HS SPI FLASH S25FL129P0XNFI001
as per FLASHCS_SEL0. See
Table 37 .
7 SD8X
• 0 - Uses SPI_CS(0:3)_B pins as SDHC data bits 4:7 for SDHC-8bit mode.
SPI CS_B pins are pulled high.
• 1 - Uses SPI_CS(0:3)_B pins with the SPI controller. SDHC data bits 4:7 are
pulled high. Only uses SDHC-4bit mode.