P5040/P5020 Reference Design Board User Guide, Rev. 0
14
Freescale Semiconductor
Architecture
GETH
Connectors
Copper Interface
• Integrated GETH RJ45 Connector for EC1 and USB TypeA connector for USB1
(J2)
• 90
0
RJ45 connector for EC2 (P1)
PHY
Configuration
CMODE[7...0]
Inputs used to configure VSC8244 hardware operating modes by connecting
Pull-up/down resistors.
PHY Default
Configuration
• MAC interface select: RGMII to CAT5.
• Speed/Duplex auto negotiation: 10/100/1000 Base-T HDX, FDX.
• PHY address[4:2] = ’000’
PHY Control
MII Management
Port
• Controls the following via the two-wire interface port:
–
EMI1_MDC clock
–
EMI1_MDIO bi-directional data line
MAX4906
Analog switch that chooses EMI1 routing.
EMI1
• Routing determined by one of the following:
–
P5040/P5020 GPIO[0...3]
–
ngPIXIS registers PX_BRDCFG1 and PX_BRDCFG2
PHY Reset
VSC8244
PHY RESET
• Input is driven by the P5040/P5020 HRESET signal via FPGA, and reset after
each P5040/P5020 HRESET sequence.
• Input can be driven by register PX_RST P5040/P5020RDB FPGA Bit 7.
VSC8244
SOFT_RESET
• Input is driven by the P5040/P5020 HRESET signal via FPGA, and reset after
each P5040/P5020 HRESET sequence.
• Input can be driven by register PX_RST P5040/P5020RDB FPGA Bit 5.
• Can implement by asserting bit 15 (MSB) on VSC8244 PHY MII Mode Control
Register 0.
Table 6. 10/100/1000 Base-T GETH Ports (continued)
GETH Feature
Specifics
Description