P5040/P5020 Reference Design Board User Guide, Rev. 0
50
Freescale Semiconductor
Programming Model
7.1.1
ID Register (PX_ID)
The ID register has a unique classification number; the software uses it to uniquely identify development
boards. The number remains the same for all revisions.
Figure 22. ID Register (PX_ID)
7.1.2
Architectural Version Register (PX_ARCH)
The architectural version register holds the board’s architectural revision. Registers change only after a
significant board revision—a software-visible and impacting change; for example, replacing a component
with a slot or eliminating a “backup” device.
NOTE
Changing a FLASH manufacturer is not considered an architectural change
as CFI-compliant FLASH programmers are meant to be adaptable.
0x32
PX_VID_DIR
FPGA
VID(0-3)/GPIO(28-31)
Direction - N/A for
P5040RDB
R/W
0x00
0x33
PX_VID_OUT
FPGA
VID(0-3)/GPIO(28-31)
Out
R
xx
0x34
PX_VID_IN
FPGA GPIO(28-31) In
R/W
0x00
0
1
2
3
4
5
6
7
R
ID
W
Reset
0x20
Offset
0x00
Table 27. PX_ID Field Descriptions
Bits
Name
Description
0–7
ID
Board identification
Table 26. ngPIXIS Register Map (continued)
Base Address Offset
Name
ngPIXIS (PX) Register
Access
Reset