P5040/P5020 Reference Design Board User Guide, Rev. 0
Freescale Semiconductor
41
Architecture
This table summarizes switch-selectable clock generation possibilities. The calculations are based upon
25 MHz reference clock input. “Control Word” field values are characterized as follows:
•
Data was sent to ICS307 upon startup or if commanded by the FPGA VELA controller.
•
Values were calculated from ICS307 data sheet examples or using the IDT on-line calculator.
•
Values were calculated for frequency accuracy versus lowest-jitter; the latter parameter was
chosen.
5.5
System Reset
shows P5040/P5020RDB reset connections from which the following can be inferred:
•
ngPIXIS registers are reset by every reset input as well as GO.
— GO is a VELA-controller output that is, in turn, controlled by ngPIXIS registers.
•
Most ngPIXIS registers are reset by either RRST or XRST.
— PX_AUX is the exception; it is ONLY reset by RRST and is unaffected by COP_HRST and
wdog_rst.
•
If the watchdog timer expires then all internal settings are reset. This includes VELA-controlled
configurations.
•
If the COP_HRST signal is asserted then all internal settings are reset.This includes
VELA-controlled configurations.
•
Reset sequencer is triggered at GO, COP_HRESET, or RST.
— Sequencer asserts CPU_TRST when triggered by GO and RST.
— Sequencer does NOT assert CPU_TRST when triggered by COP_HRST.
•
Reset sequencer controls CPU_HRST. The sequencer must be active in order for the COP_HRST
signal to pass through.
•
Conversely, CPU_TRST is wire-OR’ed with the sequencer.
Table 20. SYSCLK Frequency Options
SYSCLK_SEL[0...2]
Desired SYSCLK
(MHz)
Actual SYSCLK
(MHz)
Error
(ppm)
ICS307
Control Word
0 0 0
67
66.666
4.985
0x370801
0 0 1
83
83.333
4.012
0x330601
0 1 0
100
100.000
0
0x330801
0 1 1
125
125.000
0
0x310381
1 0 0
133
133.333
2.503
0x310401
1 0 1
150
150.000
0
0x310501
1 1 0
160
160.000
0
0x310C03
1 1 1
167
166.666
2
0x310601