NXP Semiconductors MPC5746R, Datasheet

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Table of Contents
1 Introduction........................................................................................ 3
1.1 Block diagram......................................................................... 3
2 Package pinouts and signal descriptions............................................ 5
3 Absolute maximum ratings................................................................ 6
4 Electromagnetic Compatibility (EMC).............................................. 7
5 Electrostatic discharge (ESD)............................................................ 7
6 Operating conditions.......................................................................... 8
7 DC electrical specifications................................................................11
8 I/O pad specification.......................................................................... 12
8.1 Input pad specifications...........................................................12
8.2 Output pad specifications........................................................ 15
8.3 I/O pad current specifications................................................. 17
9 Reset pad (PORST, RESET) electrical characteristics...................... 18
10 Oscillator and FMPLL....................................................................... 22
11 ADC modules.....................................................................................26
11.1 ADC input description............................................................ 26
11.2 SAR ADC................................................................................26
11.3 S/D ADC................................................................................. 29
12 Temperature sensor............................................................................ 39
13 LVDS fast asynchronous serial transmission (LFAST) pad
electrical characteristics..................................................................... 40
13.1 LFAST interface timing diagrams...........................................40
13.2 LFAST and MSC /DSPI LVDS interface electrical
characteristics.......................................................................... 42
14 LFAST PLL electrical characteristics................................................45
15 Aurora LVDS electrical characteristics............................................. 46
16 Power management PMC POR LVD sequencing..............................47
16.1 Power management electrical characteristics..........................47
16.1.1 Recommended power transistors............................ 47
16.1.2 Power management integration.............................. 48
16.1.3 Regulator example for the NJD2873 transistor...... 50
16.1.4 Regulator example for the 2SCR574d transistor.... 51
16.1.5 Device voltage monitoring......................................51
16.1.6 Power up/down sequencing.................................... 53
17 Flash memory specifications..............................................................54
17.1 Flash memory program and erase specifications.................... 54
17.2 Flash memory Array Integrity and Margin Read
specifications...........................................................................55
17.3 Flash memory module life specifications................................55
17.4 Data retention vs program/erase cycles...................................56
17.5 Flash memory AC timing specifications.................................57
17.6 Flash read wait state and address pipeline control settings.....58
18 AC specifications............................................................................... 58
18.1 Debug and calibration interface timing...................................58
18.1.1 JTAG interface timing............................................ 58
18.1.2 Nexus interface timing............................................61
18.1.3 Aurora LVDS interface timing............................... 63
18.2 DSPI timing with CMOS and LVDS...................................... 65
18.2.1 DSPI master mode full duplex timing with CMOS
and LVDS pads.......................................................66
18.2.2 DSPI CMOS slave mode........................................ 78
18.3 FEC timing.............................................................................. 80
18.3.1 MII-lite receive signal timing (RXD[3:0],
RX_DV, RX_ER, and RX_CLK)...........................80
18.3.2 MII-lite transmit signal timing (TXD[3:0],
TX_EN, TX_ER, TX_CLK)...................................81
18.3.3 MII-lite async inputs signal timing (CRS and
COL)....................................................................... 82
18.3.4 MII-lite serial management channel timing
(MDIO and MDC).................................................. 82
18.3.5 RMII serial management channel timing (MDIO
and MDC)............................................................... 83
18.3.6 RMII receive signal timing (RXD[1:0], CRS_DV)84
18.3.7 RMII transmit signal timing (TXD[1:0], TX_EN). 85
18.4 UART timings......................................................................... 86
18.5 eMIOS timing..........................................................................86
19 Obtaining package dimensions.......................................................... 86
20 Thermal characteristics...................................................................... 87
20.1 General notes for specifications at maximum junction
temperature..............................................................................89
21 Ordering information......................................................................... 90
22 Revision history................................................................................. 91
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
2 NXP Semiconductors