NXP Semiconductors MPC5746R, Datasheet

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17.5 Flash memory AC timing specifications
Table 33. Flash memory AC timing specifications
Symbol Characteristic Min Typical Max Units
t
psus
Time from setting the MCR-PSUS bit until MCR-DONE bit is set
to a 1. — 9.4
plus four
system
clock
periods
11.5
plus four
system
clock
periods
μs
t
esus
Time from setting the MCR-ESUS bit until MCR-DONE bit is set
to a 1. — 16
plus four
system
clock
periods
20.8
plus four
system
clock
periods
μs
t
res
Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low. — — 100 ns
t
done
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared. — — 5 ns
t
dones
Time from 1 to 0 transition on the MCR-EHV bit aborting a
program/erase until the MCR-DONE bit is set to a 1. — 16
plus four
system
clock
periods
20.8
plus four
system
clock
periods
μs
t
drcv
Time to recover once exiting low power mode. 16
plus seven
system
clock
periods.
— 45
plus seven
system
clock
periods
μs
t
aistart
Time from 0 to 1 transition of UT0-AIE initiating a Margin Read
or Array Integrity until the UT0-AID bit is cleared. This time also
applies to the resuming from a suspend or breakpoint by
clearing AISUS or clearing NAIBP — — 5 ns
t
aistop
Time from 1 to 0 transition of UT0-AIE initiating an Array
Integrity abort until the UT0-AID bit is set. This time also applies
to the UT0-AISUS to UT0-AID setting in the event of a Array
Integrity suspend request. — — 80
plus fifteen
system
clock
periods
ns
t
mrstop
Time from 1 to 0 transition of UT0-AIE initiating a Margin Read
abort until the UT0-AID bit is set. This time also applies to the
UT0-AISUS to UT0-AID setting in the event of a Margin Read
suspend request. 10.36
plus four
system
clock
periods
— 20.42
plus four
system
clock
periods
μs
Flash memory specifications
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
NXP Semiconductors 57