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2. V
DD_LV
noise due to application in the range V
DD_LV
= 1.25V (+/-5%) with frequency below PLL bandwidth (40 KHz) will be
filtered.
Table 14. FMPLL1 electrical characteristics
Symbol
Parameter
Conditions
Value
Unit
Min
Typ
Max
f
PLL1IN
PLL1 input clock
—
38
—
78
MHz
Δ
PLL1IN
—
35
—
65
%
f
PLL1VCO
PLL1 VCO frequency
—
600
—
1250
MHz
f
PLL1PHI0
PLL1 output clock PHI0
—
4.762
—
200
MHz
t
PLL1LOCK
PLL1 lock time
—
—
—
100
µs
f
PLL1MOD
PLL1 modulation frequency
—
—
—
250
kHz
|
δ
PLL1MOD
| PLL1 modulation depth (when enabled) Center spread
0.25
—
2
%
Down spread
0.5
—
4
%
|
Δ
PLL1PHI0SPJ
|
PLL1_PHI0 single period peak to peak
jitter
f
PLL1PHI0
= 200 MHz, 6-
sigma pk-pk
—
—
500
ps
I
PLL1
PLL1 consumption
FINE LOCK state
—
—
6
mA
1. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when
using internal PLL0 or external oscillator is used in functional mode.
2. 1.25V +/-5%, application noise below 40kHz at V
DD_LV
pin - no frequency modulation
All oscillator specifications are valid for V
DD_HV_IO_JTAG
= 3.0 V to 5.5 V.
Table 15. XOSC External Oscillator electrical specifications
Symbol
Parameter
Conditions
Value
Unit
Min
Max
f
XTAL
—
4
8
MHz
—
>8
20
16MHz < freq < 40MHz (at present, freq =
20M and 40M have been validated, but still
needs to be carried out for freq = 16MHz)
>20
40
t
cst
T
J
= 150 °C, 20 MHz ≤ f ≤ 40 MHz
—
5
ms
t
rec
—
—
0.5
ms
V
IHEXT
EXTAL input high voltage
(External Reference)
V
REF
= 0.28 * V
DD_HV_IO_JTAG
V
REF
+ 0.6
—
V
V
ILEXT
EXTAL input low voltage
(External Reference)
V
REF
= 0.28 * V
DD_HV_IO_JTAG
—
V
REF
-
0.6
V
C
S_EXTAL
Total on-chip stray capacitance
on EXTAL pin
BGA
4.75
5.25
pF
QFP
5.25
5.75
C
S_XTAL
Total on-chip stray capacitance
on XTAL pin
BGA
4.75
5.25
pF
QFP
5.25
5.75
g
m
Oscillator Transconductance
T
J
= -40 °C to 150
°C
f
XTAL
≤ 8 MHz
3
13
mA/V
f
XTAL
≤ 20 MHz
9
35
Table continues on the next page...
Oscillator and FMPLL
SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017
NXP Semiconductors
23