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NXP Semiconductors MPC5746R, Datasheet

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Table 50. RMII serial management channel timing (continued)

Spec

Characteristic

Value

Unit

Min

Max

M11

MDC falling edge to

MDIO output valid (max

prop delay)

—

25

ns

M12

MDIO (input) to MDC

rising edge setup

10

—

ns

M13

MDIO (input) to MDC

rising edge hold

0

—

ns

M14

MDC pulse width high

40%

60%

MDC period

M15

MDC pulse width low

40%

60%

MDC period

MDC (output)

MDIO (output)

MDIO (input)

M12

M13

M10

M15

M14

M11

Figure 45. RMII-lite serial management channel timing diagram

18.3.6 RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.
There is no minimum frequency requirement. The system clock frequency must be at
least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK
frequency.

All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels.

AC specifications

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

84

NXP Semiconductors

Summary of Contents for MPC5746R

Page 1: ...C5746R series of microcontroller units MCUs For functional characteristics see the MPC5746R Microcontroller Reference Manual NXP Semiconductors Document Number MPC5746R Data Sheet Technical Data Rev 6...

Page 2: ...h memory specifications 54 17 1 Flash memory program and erase specifications 54 17 2 Flash memory Array Integrity and Margin Read specifications 55 17 3 Flash memory module life specifications 55 17...

Page 3: ...high as 200 MHz and offers high performance processing optimized for low power consumption It capitalizes on the available development infrastructure of current Power Architecture devices and is supp...

Page 4: ...200 MHz System Memory Protection Unit SMPU_0 SWT_0 STM_0 E200 z425 200 MHz Main Core_0 DSP VLE Scalar SP FPU Nexus3p I Mem ctrl I Cache ctrl 16kB IMEM 8kB 2way D Mem ctrl 32kB DMEM Core Memory Protect...

Page 5: ...ER_0 PIT_RTI A TX MEMU JT AGM STCU2 JDC TDM ADC_SD_2 ADC_SD_0 ADC_SAR_2 ADC_SAR_0 SENT_0 DTS CRC_0 REACM eTPU_0 Reg eTPU_0 Code RAM RAM eTPU_0 Par eMIOS_0 FEC eDMA 3x SWT 2x STM INTC SEMA4 PFLASH PCM...

Page 6: ...ence to VSS 0 3 0 3 V VSS_HV_ADV_SAR SAR ADC ground voltage Reference to VSS 0 3 0 3 V VDD_HV_ADV_SAR SAR ADC supply voltage Reference to VSS_HV_ADV_SAR 0 3 6 0 V VDD_HV_ADV_SD S D ADC supply voltage...

Page 7: ...s given are for reference only 7 The maximum input voltage on an I O pin tracks with the associated I P supply maximum For the injection current condition on a pin the voltage will be equal to the sup...

Page 8: ...ce Model Component Level 6 Operating conditions The following table describes the operating conditions for the device and for which all specifications in the data sheet are valid except where explicit...

Page 9: ...HV_ADV_SD VSS VSS_HV_ADV_SD differential voltage 25 25 mV VSS_HV_ADV_SAR VSS VSS_HV_ADV_SAR differential voltage 25 25 mV VRAMP_VDD_LV Slew rate on power supply pins VDD_LV Ramp up 0 069 100 V ms Ramp...

Page 10: ...VDD_HV_ADV_SD to VDD_HV_ADV_SAR at board level 17 Temperature Sensor and its associated Band Gap reference are supplied by this pin The temperature sensor performance is guaranteed only between 4 5 V...

Page 11: ...t operational 3 4 5 VDDSTBY 1 3 V to 5 9 V TJ 150 C 575 A VDDSTBY 1 3 V to 5 9 V TA 40 C 55 VDDSTBY 1 3 V to 5 9 V TA 85 C 65 IDDSTBY_REG 32 KB RAM Standby Regulator Current 6 VDDSTBY 1 2 V to 5 9 V T...

Page 12: ...nt on the pin when VDDSTBY pin is set to 0V disabling the standby regulator 7 Worst case usage data trace data overlay full Aurora utilization 8 I O pad specification The following table describes the...

Page 13: ...55 VDD_HV_IO VDD_HV_IO 0 3 V VILCMOS_H CMOS input low level with hysteresis 3 0 V VDD_HV_IO 5 5 V VSS 0 3 0 35 VDD_HV_IO V VILCMOS CMOS input low level without hysteresis 3 0 V VDD_HV_IO 5 5 V VSS 0 3...

Page 14: ...tics Symbol Parameter Conditions Value Unit Min Typ Max IWPU Weak pull up current absolute value1 Vin VIH 0 65 VDD_HV_IO A 4 5V VDD_HV_IO 5 5V 30 3 0V VDD_HV_IO 3 6V 18 Vin VIL 0 35 VDD_HV_IO 4 5V VDD...

Page 15: ...itances and VDD_HV_IO supply Figure 4 Weak pull up electrical characteristics definition Analog input leakage and pull up down information is located in the ADC input description section 8 2 Output pa...

Page 16: ...ter Conditions Value 1 2 Unit Min Typ Max VOH GPIO pad output high voltage 4 5V VDD_HV_IO 5 0V MSCR OERC 11 IOH 38mA MSCR OERC 10 IOH 19mA MSCR OERC 01 IOH 10mA MSCR OERC 00 IOH 5mA 0 8 VDD_H V_IO V 3...

Page 17: ...W Difference between rise and fall time 10 1 All GPIO pad output specifications are valid for 3 0V VDD_HV_IO 5 5V except where explicitly stated 2 All values need to be confirmed during device validat...

Page 18: ...t of the I O on a single segment should remain below the IMAXSEG value given in the table Absolute maximum ratings In order to ensure device functionality the sum of the dynamic and static current of...

Page 19: ...ure describes device behavior depending on supply signal on PORST 1 PORST low pulse amplitude is too low it is filtered by input buffer hysteresis Device remains in current state 2 PORST low pulse dur...

Page 20: ...V VIL Reset Input low level TTL 3 5 V VDD_HV_IO 3 6 V VSS 0 3 0 6 V 4 5 V VDD_HV_IO 5 5 V VSS 0 3 0 8 VHYS Reset Input hysteresis TTL 3 5 V VDD_HV_IO 5 5 V 300 mV VIH PORST Input high level CMOS 3 5...

Page 21: ...V VDD_HV_IO 3 6 V 80 IWPD PORST Weak pull down current absolute value PORST pin VIN VIH 0 65 VDD_HV_IO 4 5 V VDD_HV_IO 5 5 V 120 A PORST pin VIN VIH 0 65 VDD_HV_IO 3 5 V VDD_HV_IO 3 6 V 80 PORST pin...

Page 22: ...frequency 600 1250 MHz fPLL0PHI0 PLL0 output clock PHI0 4 762 400 MHz tPLL0LOCK PLL0 lock time 110 s PLL0PHI1SPJ PLL0_PHI1 single period jitter fPLL0IN 20 MHz resonator fPLL0PHI1 40 MHz 6 sigma 3002 p...

Page 23: ...25V 5 application noise below 40kHz at VDD_LV pin no frequency modulation All oscillator specifications are valid for VDD_HV_IO_JTAG 3 0 V to 5 5 V Table 15 XOSC External Oscillator electrical specif...

Page 24: ...ng for on chip and PCB capacitance The capacitance on EXTAL and XTAL by internal capacitance array is controlled by the XOSC LOAD CAP SEL field of the UTEST Miscellaneous DCF client See the DCF Record...

Page 25: ...L XTAL 0 V 0 V V ALC DDOSC Figure 9 Test circuit Table 17 Internal RC Oscillator electrical specifications Symbol Parameter Conditions Value Unit Min Typ Max fTarget IRCOSC target frequency 16 MHz fva...

Page 26: ...for the analog input pad weak pull up and pull down and the resistance for the analog input bias diagnostic pull up down Table 18 Analog Input Leakage and Pull Up Down DC electrical characteristics Sy...

Page 27: ...ve 3 Differential non linearity error DNL 4 Integral non linearity error INL 5 Center of a step of the actual transfer curve code out 4095 4094 4093 4092 4091 4090 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 4089 4...

Page 28: ...fCK 2 ADC Clock frequency depends on ADC configuration The duty cycle depends on AD_CK3 frequency 20 80 MHz fs Sampling frequency 1 00 MHz tsample Sample time4 250 ns tconv Conversion time5 80 MHz 700...

Page 29: ...ADC 4 During the sample time the input capacitance CS can be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach its final voltag...

Page 30: ...DR_SD GAIN fADCD_M S D clock frequency TJ 150 C 4 14 4 16 MHz fADCD_S Conversion rate TJ 150 C 333 ksps Oversampling ratio Internal modulator 24 256 RESOLUTION S D register resolution 2 s complement n...

Page 31: ...ADV_SD GAIN 8 TJ 150 C 69 4 5 VDD_HV_ADV_SD 5 57 VDD_HV_ADR_SD VDD_HV_ADV_SD GAIN 16 TJ 150 C 65 SNRDIFF333 7 Signal to noise ratio in differential mode 333 ksps output rate 4 5 VDD_HV_ADV_SD 5 57 VDD...

Page 32: ...de 150 ksps output rate 4 5 VDD_HV_ADV_SD 5 57 VDD_HV_ADR_SD VDD_HV_ADV_SD GAIN 1 TJ 150 C 72 dB 4 5 VDD_HV_ADV_SD 5 57 VDD_HV_ADR_SD VDD_HV_ADV_SD GAIN 2 TJ 150 C 69 4 5 VDD_HV_ADV_SD 5 57 VDD_HV_ADR...

Page 33: ..._HV_ADV_SD GAIN 4 TJ 150 C 74 4 5 VDD_HV_ADV_SD 5 57 VDD_HV_ADR_SD VDD_HV_ADV_SD GAIN 8 TJ 150 C 80 4 5 VDD_HV_ADV_SD 5 57 VDD_HV_ADR_SD VDD_HV_ADV_SD GAIN 16 TJ 150 C 80 THDDIFF333 Total Harmonic Dis...

Page 34: ...ended mode 150 ksps output rate 4 5 VDD_HV_ADV_SD 5 57 VDD_HV_ADR_SD VDD_HV_ADV_SD GAIN 1 TJ 150 C 68 dB 4 5 VDD_HV_ADV_SD 5 57 VDD_HV_ADR_SD VDD_HV_ADV_SD GAIN 2 TJ 150 C 68 4 5 VDD_HV_ADV_SD 5 57 V...

Page 35: ...V_ADV_SD GAIN 4 TJ 150 C 69 4 5 VDD_HV_ADV_SD 5 57 VDD_HV_ADR_SD VDD_HV_ADV_SD GAIN 8 TJ 150 C 68 8 4 5 VDD_HV_ADV_SD 5 57 VDD_HV_ADR_SD VDD_HV_ADV_SD GAIN 16 TJ 150 C 64 8 SINADDIFF333 Signal to Nois...

Page 36: ...ingle ended mode 150 ksps output rate 4 5 VDD_HV_ADV_SD 5 57 VDD_HV_ADR_SD VDD_HV_ADV_SD GAIN 1 TJ 150 C 66 dB 4 5 VDD_HV_ADV_SD 5 57 VDD_HV_ADR_SD VDD_HV_ADV_SD GAIN 2 TJ 150 C 66 4 5 VDD_HV_ADV_SD 5...

Page 37: ...VINTCM Common Mode input reference voltage11 12 12 VBIAS Bias voltage VDD_ HV_ ADR_S D 2 V VBIAS Bias voltage accuracy 2 5 2 5 CMRR Common mode rejection ratio 55 dB Anti aliasing filter External ser...

Page 38: ...CD_S fHIGH High pass filter 3dB frequency Enabled 10e 5 fADCD_S tSTARTUP Start up time from power down state 100 s tLATENCY Latency between input data and converted data when input mux does note chang...

Page 39: ...ce given at fADCD_M 16 MHz Impedance is inversely proportional to SDADC clock frequency ZDIFF fADCD_M 16 MHz fADCD_M ZDIFF ZCM fADCD_M 16 MHz fADCD_M ZCM 10 Input impedance in single ended mode ZIN 2...

Page 40: ...characteristics The LFAST pad electrical characteristics apply to both the LFAST and high speed debug serial interfaces on the device The same LVDS pad is used for the Microsecond Channel MSC and DSP...

Page 41: ...Minimum Differential Minimum Data Bit Time Data Bit Period Min common mode input at RX Signal excursions below this level NOT allowed Opening No Go Area 0 55 T LFAST 0 50 T MSC SIPI DATA VOD VOD 1743...

Page 42: ...ollowing table contains the electrical characteristics for the LFAST interface The LVDS pad electrical characteristics in this table apply to both the LFAST and High speed Debug HSD LVDS pad and the M...

Page 43: ...l bridge clock periods The LFAST and High Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance values 2 Total transmitter startup time from sleep mode to norma...

Page 44: ...C Table 24 MSC DSPI LVDS transmitter electrical characteristics Symbol Parameter Conditions Value Unit Min Typ Max Data Rate fDATA Data rate 80 Mbps VOS Common mode voltage 1 08 1 32 V VOD Differentia...

Page 45: ...cal characteristics Symbol Parameter Conditions Value Unit Min Nominal Max fRF_REF PLL reference clock frequency 10 26 MHz ERRREF PLL reference clock frequency error 1 1 DCREF PLL reference clock duty...

Page 46: ...e peripheral bridge clock that is connected to the PLL on the device 3 Measured at the transmitter output across a 100 Ohm termination resistor on a device evaluation board Refer to the figure below D...

Page 47: ...ata rate FTX 2 The minimum value of 400 mV is only valid for differential resistance RV_L 99 ohm to 101 ohm The differential output voltage swing tracks with the value of RV_L 3 Transimission line los...

Page 48: ...ximum DC collector current 2 0 A VCESAT Collector to emitter saturation voltage 300 mV VBE Base to emitter voltage 0 95 V VC Minimum voltage at transistor collector 2 5 V 16 1 2 Power management integ...

Page 49: ...ed on the device for proper operation Table 28 Device power supply integration Symbol Parameter Conditions Value1 Unit Min Typ Max CLV Minimum VDD_LV external bulk capacitance 2 3 4 7 F CHV_PMC Minimu...

Page 50: ...uirements 5 The recommended flash regulator composition capacitor is 1 5 F typical X7R or X5R with 50 and 35 as min and max This puts the min cap at 0 75 F 6 For noise filtering it is recommended to a...

Page 51: ...n 100n Cc 4u 14u ESR 15m 150m Beta 120 360 ILoad Figure 19 Regulator example 16 1 5 Device voltage monitoring The LVD HVDs for the device and their levels are given in the following table Voltage moni...

Page 52: ...is asserted tVDASSERT after detection when lower threshold is crossed HVD is released after tVDRELEASE temporization when lower threshold is crossed HVD is asserted tVDASSERT after detection when upp...

Page 53: ...Falling voltage trimmed 3270 3370 3470 LVD_SAR SAR ADC supply low voltage monitoring Rising voltage 6bit Yes Disa b 2820 2910 3000 mV Falling voltage 2790 2880 2970 tVDASSERT Voltage detector threshol...

Page 54: ...e 256 bits program time 73 200 300 108 500 s tqppgm Quad page 1024 bits program time 268 800 1 200 396 2 000 s t16kers 16 KB Block erase time 168 290 320 250 1 000 ms t16kpgm 16 KB Block program time...

Page 55: ...on 256 KB block 893 01 1 339 5 s 1 Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read The equation presented require Tperiod which is the u...

Page 56: ...Program and erase supported across standard temperature specs 17 4 Data retention vs program erase cycles Graphically Data Retention versus Program Erase Cycles can be represented by the following fi...

Page 57: ...riods s tdrcv Time to recover once exiting low power mode 16 plus seven system clock periods 45 plus seven system clock periods s taistart Time from 0 to 1 transition of UT0 AIE initiating a Margin Re...

Page 58: ...133 MHz 3 1 6 1 167 MHz 4 1 7 1 200 MHz 5 2 8 1 18 AC specifications 18 1 Debug and calibration interface timing 18 1 1 JTAG interface timing These specifications apply to JTAG boundary scan only See...

Page 59: ...t of high impedance 600 ns 13 tBSDHZ TCK falling edge to output high impedance 600 ns 14 tBSDST Boundary scan input valid to TCK rising edge 15 ns 15 tBSDHT TCK rising edge to boundary scan input inva...

Page 60: ...TCK 6 8 7 5 TMS TDI TDO 4 Figure 23 JTAG test access port timing TCK JCOMP 9 10 Figure 24 JTAG JCOMP timing AC specifications SPC5746R Microcontroller Data Sheet Rev 6 06 2017 60 NXP Semiconductors...

Page 61: ...type as specified in the I O section of the data sheet Table 36 Nexus debug port timing Symbol Characteristic Value Unit Min Max 1 tEVTIPW EVTI Pulse Width 4 tCYC 1 2 tEVTOPW EVTO Pulse Width 40 ns 3...

Page 62: ...proper operation TCK frequency should be set to the peripheral frequency divided by a number greater than or equal to that specified here 3 This is a functionally allowable feature However it may be l...

Page 63: ...defined as the time taken by LVDS current reference block for settling bias current after its pwr_down power down has been deasserted LVDS functionality is guaranteed only after the startup time 2 St...

Page 64: ...LK Reference clock frequency 625 1200 MHz 1a tMCYC Reference clock rise fall time 400 ps 2 tRCDC Reference clock duty cycle 45 55 3 JRC Reference clock jitter 40 ps 4 tSTABILITY Reference clock stabil...

Page 65: ...ency support is shown in Table 39 Timing specifications are shown in Table 40 Table 41 Table 42 Table 43 Table 44 Table 39 DSPI channel frequency support DSPI use mode Max usable frequency MHz 1 2 CMO...

Page 66: ...mismatching of rise and fall times of the output pads Table 40 DSPI CMOS master classic timing full duplex and output only MTFE 0 CPHA 0 or 1 Symbol Characteristic Condition Value1 Unit Pad drive2 Lo...

Page 67: ...drive strength Very strong 25 pF 7 0 ns Strong 50 pF 8 0 Medium 50 pF 16 0 SOUT data hold time after SCK edge 10 tHO SOUT data hold time after SCK9 SOUT and SCK drive strength Very strong 25 pF 7 7 n...

Page 68: ...ivide ratios cases the absolute spec number is applied as jitter uncertainty to the nominal high time and low time 7 PCSx and PCSS using same pad configuration 8 Input timing assumes an input slew rat...

Page 69: ...mismatching of rise and fall times of the output pads NOTE In Table 41 all output timing is worst case and includes the mismatching of rise and fall times of the output pads Table 41 DSPI CMOS master...

Page 70: ...35 4 tSDC SCK duty cycle6 SCK drive strength Very strong 0 to 50 pF 1 2tSCK 2 1 2tSCK 2 ns Strong 0 to 50 pF 1 2tSCK 2 1 2tSCK 2 Medium 0 to 50 pF 1 2tSCK 5 1 2tSCK 5 PCS strobe timing 5 tPCSC PCSx to...

Page 71: ...es may reduce operating speeds and may cause incorrect operation 3 N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx P...

Page 72: ...UT load capacitances are the same value Data Data Last Data First Data First Data LastData SIN SOUT SCK Output SCK Output CPOL 0 PCSx CPOL 1 tSCK tSDC tSDC CSC t t ASC t t SUI HI tSUO tHO Figure 33 DS...

Page 73: ...x tSYS 3 10 ns Medium 50 pF N2 x tSYS 3 32 ns 3 tASC After SCK delay LVDS SCK Very strong PCS 0 pF SCK 25 pF M4 x tSYS 3 8 ns Strong PCS 0 pF SCK 25 pF M4 x tSYS 3 8 ns Medium PCS 0 pF SCK 25 pF M4 x...

Page 74: ...clock mode is selected in which case N is automatically set to 0 clock cycles PCS and SCK are driven by the same edge of DSPI_CLKn 3 tSYS is the period of DSPI_CLKn clock the input clock to the DSPI...

Page 75: ...6 DSPI LVDS master mode modified timing CPHA 0 Data First Data First Data Last Data Data LastData SIN PCSx SCK Output SCK Output CPOL 0 CPOL 1 SOUT tSUI t t HI HI tSUO tHO Figure 37 DSPI LVDS master m...

Page 76: ...with 50 pF differential load cap LVDS 15 pF to 50 pF differential 1 2tSCK 2 1 2tSCK 2 ns SOUT data valid time after SCK edge 5 tSUO SOUT data valid time from SCK2 SOUT and SCK drive strength LVDS 15 p...

Page 77: ...CK 2 ns Strong 0 to 50 pF 1 2tSCK 2 1 2tSCK 2 ns Medium 0 to 50 pF 1 2tSCK 5 1 2tSCK 5 ns SOUT data valid time after SCK edge 9 tSUO SOUT data valid time from SCK CPHA 1 5 SOUT and SCK drive strength...

Page 78: ...slave operation is only supported for a single master and single slave on the device Timing is valid for that case only Table 45 DSPI CMOS slave timing Modified Transfer Format MTFE 0 1 Symbol Charac...

Page 79: ...g assumes an input slew rate of 1 ns 10 90 and uses TTL Automotive voltage thresholds 2 All timing values for output signals in this table are measured to 50 of the output voltage All output timing is...

Page 80: ...ly up to a RX_CLK maximum frequency of 25 MHz 1 There is no minimum frequency requirement The system clock frequency must be at least equal to or greater than the RX_CLK frequency All timing specifica...

Page 81: ...is the same in either case This options allows the use of non compliant MII PHYs All timing specifications are referenced from TX_CLK 1 4 V to the valid output levels Table 47 MII lite transmit signa...

Page 82: ...L M9 Figure 43 MII lite async inputs timing diagram 18 3 4 MII lite serial management channel timing MDIO and MDC The FEC functions correctly with a maximum MDC frequency of 2 5 MHz NOTE All timing sp...

Page 83: ...DC pulse width low 40 60 MDC period M1 1 M10 MDC output MDIO output M12 M13 MDIO input M14 M15 Figure 44 MII lite serial management channel timing diagram 18 3 5 RMII serial management channel timing...

Page 84: ...M12 M13 M10 M15 M14 M11 Figure 45 RMII lite serial management channel timing diagram 18 3 6 RMII receive signal timing RXD 1 0 CRS_DV The receiver functions correctly up to a REF_CLK maximum frequenc...

Page 85: ...be at least equal to or greater than the TX_CLK frequency which is half that of the REF_CLK frequency The transmit outputs TXD 1 0 TX_EN can be programmed to transition from either the rising or fall...

Page 86: ...10 6 Limited voting on one sample with configurable sampling point 13 33 5 16 4 20 18 5 eMIOS timing Table 54 eMIOS timing Symbol Characteristic Condition Min Value Max Value Unit tMIPW eMIOS Input Pu...

Page 87: ...a function of die size on chip power dissipation package thermal resistance mounting site board temperature ambient temperature air flow power dissipation of other components on the board and board t...

Page 88: ...e junction temperature per JEDEC JESD51 12 Table 58 Thermal characteristics for the 252 pin MAPBGA package with full solder balls Rating Conditions Symbol Value Unit Junction to Ambient Natural Convec...

Page 89: ...erature per JEDEC JESD51 12 20 1 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature TJ can be obtained from this equation TJ TA R JA PD whe...

Page 90: ...W PD power dissipation in the package W The thermal characterization parameter is measured per JESD51 2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case...

Page 91: ...GE_0 In section Introduction removed section Parameter classification In section Absolute maximum ratings Table 1 VDD_HV_IO_FEC spec removed row for Using Ethernet Reference to VSS condition Corrected...

Page 92: ...DC modules revised the subsection structure and titles Added section ADC input description with content moved from the Input pad specifications section Section Input impedance and ADC accuracy renamed...

Page 93: ...on LFAST and MSC DSPI LVDS interface electrical characteristics Table 24 the max value for Rise Fall time specs changed from 4 0 to 5 7 ns In section LFAST PLL electrical characteristics Table 25 PERE...

Page 94: ...changed PCS strobe timing values In section DSPI CMOS master mode modified timing Added NOTE In Table 41 changed PCS strobe timing values In section DSPI LVDS master mode modified timing Table 42 cha...

Page 95: ...Max value changed to 610 mA IDDSTBY_ON TA 40 C and TA 85 C values updated IVDDA values updated In section I O pad specification Table 6 Description for Input only pads removed reference to Automotive...

Page 96: ...changed 5V or Vcollector to 3 3V or Vcollector In section DSPI CMOS master mode classic timing Table 40 Changed tSDC spec s Condition SCK drive strength from 0 pF to 0 to 50 pF In tSUI and tHI specs f...

Page 97: ...C collector current In section SAR ADC table ADC conversion characteristics Removed the condition for tsample Removed the Min and added the formula 6 02 ENOB 1 76 for SINAD Changed the Min value from...

Page 98: ...pts no liability for any vulnerability that is discovered Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products N...

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