Distributor of NXP Semiconductors: Excellent Integrated System Limited
Datasheet of MPC8569E-MDS-PB - BOARD MOD DEV SYSTEM MPC8569
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MPC8569E-MDS-PB Hardware Getting Started, Rev. 3.1
Freescale Semiconductor
19
Board Control Status Registers (BCSR)
10 Board Control Status Registers (BCSR)
10.1
BCSR0
Table 8. BCSR0 Register
10.2
BCSR1
Table 9. BCSR1 Register
Bit
Config Signals
Function
Default
Att
[0:3]
CFG_SYS_PLL[0:3]
Establishes clock ratio between SYSCLK and CCB.
SW7[1:4] sampled at
HRESET. [
1000
]
R,W
[4:6]
CFG_CORE_PLL[0:2]
Sets ratio between e500 Core PLL clock and CCB.
SW7[5:7] sampled at
HRESET [
100
]
R,W
[7]
CFG_SRDS_REFCLK
• 0: SerDes expects 125 MHz reference clock frequency.
• 1 (Default): SerDes expects 100 MHz reference clock
frequency.
SW7[8] sampled at
HRESET [
1
]
R,W
Bit
Config Signals
Function
Default
Att
[0:2]
CFG_DDR_CLK_PLL[0:2]
Configure DDR PLL ratio.
SW5[1:3] sampled at
HRESET.
• DDR2 [
100
]
• DDR3 [
110
]
R,W
[3]
CFG_DDR_FB_SEL
DDR QE and Platform PLL Feedback Select
• 0: gclk-matched/long DDR, QE, and Platform PLLs
feedback path.
• 1 (Default): local/short DDR PLL feedback path.
SW5[4] sampled at
HRESET [
1
]
R,W
[4]
CFG_DDR_TYPE
DDR Dram Type (DDR2 or DDR3)
• 0: DDR3 of 1.5V and low CKE at reset.
• 1 (Default): DDR2 of 1.8V and low CKE at reset.
SW5[5] sampled at
HRESET.
• DDR3 [
0
]
• DDR2 [
1
]
R,W
[5]
CFG_DDR_MODE
DDR Dram Mode (1x64 or 2x32)
• 0: Primary and Secondary DDR is enabled (32-bit width
data bus).
• 1 (Default): Primary DDR is enabled (64-bit width data
bus) but secondary DDR is disabled.
SW5[6] sampled at
HRESET [
1
]
R,W
[6]
CFG_DDR_SPEED
DDR speed configuration input configures internal logic for
proper operation of the DDR.
• 0: DDR clock frequency < 500MHz.
• 1: DDR clock frequency is > or = 500MHz.
SW5[7] sampled at
HRESET [
0
]
R,W
[7]
DDR_FIX
• 1: At reset, DDR disables both MCK and MCKE.
• 0: DDR disables MCKE at reset; a few cycles later MCK
is disabled.
SW5[8] sampled at
HRESET [
1
]
R,W
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