Distributor of NXP Semiconductors: Excellent Integrated System Limited
Datasheet of MPC8569E-MDS-PB - BOARD MOD DEV SYSTEM MPC8569
Contact us: [email protected] Website: www.integrated-circuit.com
MPC8569E-MDS-PB Hardware Getting Started, Rev. 3.1
10
Freescale Semiconductor
Switch Default Settings
SW6 Configuration: QE
SW6.1-SW6.5: QUICC Engine PLL Configuration
• QUICC Engine Clock: defined by a multiplier & divisor applied to the SYSCLK input signal:
QUICC Engine clock = SYSCLK *cfg_qe_pll[0:4]
SW6.6: SDHC Card Detect Polarity Select
• ‘0’: SDHC card-detect polarity is inverted.
• ’1’: (Default) SDHC card-detect polarity isn’t inverted.
SW6.7: QE UCC1 and UCC3 Voltage Select
• ‘0’: QUICC Engine UCC1&3 GB Ethernet interface operates at 3.3V.
• ’1’: (Default) QUICC Engine UCC1&3 GB Ethernet interface operates at 2.5V.
SW6.8: QE UCC2 and UCC4 Voltage Select
• ‘0’: QUICC Engine UCC2&4 GB Ethernet interface operates at 3.3V.
• ’1’: (Default) QUICC Engine UCC2&4 GB Ethernet interface operates at 2.5V.
8
7
6
5
4
3
2
1
LVDD_SEL1
LVDD_SEL0
SDHC
QE_PLL4
QE_PLL3
QE_PLL2
QE_PLL1
ON ’0’
QE_PLL0
Value (Binary)*
Multiplier
0_0000
16
0_0010
2
0_0011
3
0_0100
4
0_0101
5
0_0110
6
0_0111
7
0_1000
(Default) 8
0_1001
9
0_1010
10
*All other combinations are reserved.
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