Distributor of NXP Semiconductors: Excellent Integrated System Limited
Datasheet of MPC8569E-MDS-PB - BOARD MOD DEV SYSTEM MPC8569
Contact us: [email protected] Website: www.integrated-circuit.com
MPC8569E-MDS-PB Hardware Getting Started, Rev. 3.1
12
Freescale Semiconductor
Switch Default Settings
SW8 Configuration: I/O
NOTE!
100 MHz clock reference (set
cfg_srds_refclk to 1).
125 MHz clock reference (set
cfg_srds_refclk to 0).
SW8.1-SW8.4: I/O Port Selection
SW8.5-SW8.7: RapidIO Device ID of the MPC8569E
• Specifies lower-order bits (3) for use by hosts on the RapidIO interface.
• (Default) If configured as a RapidIO host then the upper-order device ID bits default to ‘0’.
• If configured as a RapidIO agent then the upper-order device ID bits default to ‘1’.
• Regardless of host/agent mode configuration, unconnected cfg_device_ID_1[
n
] inputs
default to ‘1’.
SW8.8:
RapidIO System Size
• ‘0’: Large system size with a maximum of 65,536 devices.
• ‘1’: (Default) Small system size with a maximum of 256 devices.
8
7
6
5
4
3
2
1
RIO_SYS_SIZE
RIO_ID7
RIO_ID6
RIO_ID5
PORT_SEL3
PORT_SEL2
PORT_SEL1
ON ’0’
PORT_SEL0
Value
(Binary)
Description
SerDes Reference
Clock Speed
0000
- PC I Express x1 (2.5 Gbps), Lane A
100 MHz
0001
- SR IO1 1x (2.5 Gbps), Lane A
- SR IO2 1x (2.5 Gbps), Lane B
- SGMII x2 (1.25 Gbps; half-speed), Lanes E–F
100 MHz
0010
- SR IO1 1x (2.5 Gbps; half-speed), Lane A
- SR IO2 1x (2.5 Gbps; half-speed), Lane B
- SGMII x2 (1.25 Gbps; half-speed), Lanes E–F
100 MHz
0011
- SR IO1 1x (3.125 Gbps), Lane A
- SR IO2 1x (3.125 Gbps), Lane B
125 MHz
0100
- PC I Express x1 (2.5 Gbps), Lane A
- SGMII x2 (1.25 Gbps; half-speed), Lanes E–F
100 MHz
0101
- PC I Express x2 (2.5 Gbps), Lanes A–B
- SGMII x2 (1.25 Gbps; half-speed), Lanes E–F
100 MHz
0110
- PC I Express x1 (2.5 Gbps), Lane A
- SR IO1 1x (2.5 Gbps), Lane E
- SR IO2 1x (2.5 Gbps), Lane F
100 MHz
0111
(D efault)
- PC I Express x2 (2.5 Gbps), Lanes A–B
- SR IO1 1x (2.5 Gbps), Lane E
- SR IO2 1x (2.5 Gbps), Lane F
100 MHz
1000
- PC I Express x2 (2.5 Gbps), Lanes A–B
- SR IO1 1x (2.5 Gbps—half speed), Lane E
- SR IO2 1x (2.5 Gbps—half speed), Lane F
100 MHz
1001
- SR IO1 4x (1.25 Gbps; half-speed), Lanes A–B, E–F
100 MHz
1010
- SR IO1 4x (2.5 Gbps), Lanes A–B, E–F
100 MHz
1011
- SR IO1 4x (3.125 Gbps), Lanes A–B, E–F
125 MHz
1100
- PC I Express x1 (2.5 Gbps), Lane A
- SR IO2 x1 (2.5 Gbps; half-speed), Lane B
- SGMII x2 (1.25 Gbps; half-speed), Lanes E–F
100 MHz
1101
- Serdes disabled; Lanes A-B, E-F are powered-off
-
1110
- Reserved
-
1111
- PC I Express x4 (2.5 Gbps), Lanes A–B, E–F
100 MHz
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