NXP Semiconductors Boundary Scan, Manual

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1 Overview
This document focuses on the procedure of entering boundary scan mode for
board-level test. It provides the setup sequence and script examples to ensure
first-pass success.
Engineers should understand the standard for test access port and boundary
scan architecture from IEEE 1149.1.
1.1 Boundary Scan
Boundary scan is a method for testing interconnects on PCBs and internal IC
sub-blocks. It is defined in the IEEE 1149.1 standard.
In boundary scan test, each primary input and output signal on a device is supplemented with a multi-purpose memory element
called a boundary scan cell. These cells are connected to a shift register, which is referred to as the boundary scan register. This
register can be used to read and write port states.
In normal mode, these cells are transparent and the core is connected to the ports. In boundary scan mode, the core is isolated
from the ports and the port signals are controlled by the JTAG interface.
Figure 1 shows the principle of boundary scan chain.
Contents
1 Overview......................................... 1
1.1 Boundary Scan............................ 1
1.2 Test Access Port (TAP) JTAG..... 2
2 Installing software............................3
3 Hardware connection diagram........ 3
4 BSDL file validation using Lauterbach
JTAG debugger...............................8
5 Introduction to other EVK board of
i.MX RT series...............................13
6 Revision history.............................14
AN12919
Introduction to Boundary Scan of i.MX RT Series
Rev. 1 — March 2, 2021
Application Note