NXP Semiconductors Boundary Scan Manual Download

Page: 7 / 15

Figure 6. Test mode and POR connection

4. The value of GPIO_AD_B0_08 is 1 in the

BSDL

file, but we pull down it to GND on the EVK board. So we should disconnect

the resistor R303 ground terminal, and pull up this pin with

DCDC_3V3

Figure 7. GPIO_AD_B0_08 connection

5. We used OPENSDA circuit on the RT1064 EVK board, which will affect the JTAG signal level during the Boundary

Scan test. So we should disconnect the SWD jump connectors, J47, J48, J49, and J50.

shows SWD jump

connector disconnection.

NXP Semiconductors

Hardware connection diagram

Introduction to Boundary Scan of i.MX RT Series, Rev. 1, March 2, 2021

Application Note

7 / 15

Summary of Contents for Boundary Scan

Page 1: ...ndary scan cell These cells are connected to a shift register which is referred to as the boundary scan register This register can be used to read and write port states In normal mode these cells are...

Page 2: ...a general purpose port and it can provide access to many test support functions built into the component It has four or five signals as described in Table 1 NXP Semiconductors Overview Introduction to...

Page 3: ...ling software The TRACE32 installation package can be found on the Lauterbach page Download the TRACE32_201909 7z to the computer and install it 1 Because the installation package is relatively large...

Page 4: ...n to prevent damages to the debugger or target It is recommended to press F1 to enter the on line help system to get familiar with debugger 1 Taking RT1064 EVK board as an example the hardware connect...

Page 5: ...2 3 0 to burn one bit 0x460 Boot Cfg1 in eFuse to enable JTAG It can t go back to SWD after eFuse burn Figure 4 shows the setup information NXP Semiconductors Hardware connection diagram Introduction...

Page 6: ...ANCE_PATTERN part of the BSDL file They should have the same status 011 on the EVK board Figure 5 is compliance_patterns part of the BSDL file Figure 6 shows test mode and the por_b connection Figure...

Page 7: ...DCDC_3V3 Figure 7 GPIO_AD_B0_08 connection 5 We used OPENSDA circuit on the RT1064 EVK board which will affect the JTAG signal level during the Boundary Scan test So we should disconnect the SWD jump...

Page 8: ...r Lauterbach JTAG debugger recommended is LA 4533 Debug USB3 with LA 7960 4513 Related information can be found on the lauterbach page NOTE 2 Open the TRACE32 software and choose ARM32 USB NXP Semicon...

Page 9: ...he BSDL state window Figure 9 BSDL state window 5 After loading the file type in command as below BSDL SOFTRESET 6 Switch to the Check tab of the BSDL state window Click BYPASSall and IDCODEall button...

Page 10: ...eck Intern to filter out the internal registers The remaining contents are the sampled value on each signal pins Use a multimeter to measure voltage of at least three signal pins and see if the logic...

Page 11: ...shown in Figure 13 Then switch to the BSDL state window and check SetAndRun and TwoStepDR as shown in Figure 14 Figure 13 BSDL SET window EXTEST set up NXP Semiconductors BSDL file validation using La...

Page 12: ...check pass other pins as shown in Figure 15 Figure 15 BSDL SET window enable and toggle signal level The following uses GPIO_AD_B0_14 as an example It connects U1 H14 RT1064 chip as shown in Figure 1...

Page 13: ...own resistor R303 of the JTAG_MOD pin and connect it to the DCDC_3V3 power supply 3 Ensure independent JTAG topology avoid level interference of other multiplexed signals and disconnect the headers J6...

Page 14: ...n test delete the R21 resistor and mount R16 with 100 K resistor 4 Ensure independent JTAG topology avoid level interference of other multiplexed signals disconnect the headers J35 J36 J37 and J38 5 U...

Page 15: ...updates from NXP and follow up appropriately Customer shall select products with security features that best meet rules regulations and standards of the intended application and make the ultimate desi...