Figure 14. BSDL.STATE window set up
10. Switch back to BSDL.SET window, click the buttons in the Enable column to enable output of corresponding signal pins
and click the buttons in “Reg.” column to toggle their output logic state 0 or 1. Use a multimeter to measure if the logic state
really toggles on those signal pins. At least three signal pins need to be verified. Then RELOAD/EXTEST check pass other
pins, as shown in
.
Figure 15. BSDL.SET window enable and toggle signal level
The following uses GPIO_AD_B0_14 as an example. It connects U1.H14 (RT1064 chip, as shown in
) and U12.1 (CAN
BUS chip, as shown in
) with the net name of
CAN2_TX
. When Reg. is set to 0, the corresponding level of above two pins
are 0 V. When Reg. is set to 1, the corresponding level of above two pins are 3.3 V.
NXP Semiconductors
BSDL file validation using Lauterbach JTAG debugger
Introduction to Boundary Scan of i.MX RT Series, Rev. 1, March 2, 2021
Application Note
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