Figure 5. Continuous Mode and Pulsed Modes
The two images on the left side show the continuous mode, the bottom images are the zoom of the upper ones. The images on
the right are screen captures of pulsed mode. Note that the VDD_1P8 presents a higher ripple due to DC-DC being turned off for
some time until minimum voltage threshold is reached. The ripple can be configured from -75 mV to +75 mV (in 25 mV increments)
via register bit fields DCDC_LP_STATE_HYS_L and DCDC_LP_STATE_HYS_H.
Note that these register bits should not be set to 0 mV offset at the same time as this will create a situation where the DC-DC
controller is active more than necessary and consumes more current than desired.
4.1 Application Initialization Requirements
To ensure optimum DC-DC operation, it is highly recommended to configure the Loop Control bits as below during the DC-DC
startup routine. These bits properly configure the internal hardware hysteresis parameters and improve transient supply ripple
and efficiency.
DCDC_REG1[DCDC_LOOPCTRL_DF_HST_THRESH] = 0 (This is already the reset value)
DCDC_REG1[DCDC_LOOPCTRL_CM_HST_THRESH] = 0 (This is already the reset value)
DCDC_REG1[DCDC_LOOPCTRL_EN_DF_HYST] = 1
DCDC_REG1[DCDC_LOOPCTRL_EN_CM_HYST] = 1
DCDC_REG2[DCDC_LOOPCTRL_HYST_SIGN] = 1
If Pulsed mode is used, the below bit must also be configured as follows:
NXP Semiconductors
DC-DC converter software setup
MKW4xZ/3xZ/3xA/2xZ DC-DC Power Management, Rev. 3, 04 June 2021
Application Note
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