NXP Semiconductors AN5025, Application Note

Page: 17 / 28

C402
M1
Input
1.8 V
8 13
11
M4
M3
9
10,12
M2
C410 C418
1.5 V
C402
M1
Input
1.8 V
8 13
11
M4
M3
9
10,12
M2
C410 C418
1.5 V
C402
M1
Input
1.8 V
8 13
11
M4
M3
9
10,12
M2
C410 C418
1.5 V
C402
M1
Input
1.8 V
8 13
11
M4
M3
9
10,12
M2
C410 C418
1.5 V
Figure 11. Current loops of the two outputs of the DC-DC converter in buck mode
In boost mode, there will be similar loops but they take different paths. The below images show the different paths in boost mode.
Note that the images on top display the charging phase of boost mode while the bottom images display the recirculation phase.
C402
M1
Input
1.8 V
8 13
11
M4
M3
9
10,12
M2
C410 C418
1.5 V
C402
M1
Input
1.8 V
8 13
11
M4
M3
9
10,12
M2
C410 C418
1.5 V
C402
M1
Input
1.8 V
8 13
11
M4
M3
9
10,12
M2
C410 C418
1.5 V
C402
M1
Input
1.8 V
8 13
11
M4
M3
9
10,12
M2
C410 C418
1.5 V
Figure 12. Current loops of the two outputs of the DC-DC converter in boost mode
Physical location of the components in this route determines the area/shape of these current loops. Reduction of area/distance of
these loops minimize the emissions from the switching of the DC-DC. Not only should the loop geometry be minimized, the loops
should overlap as closely as possible. Therefore, it is recommended to keep the traces thick and as short as possible. It is not
recommended to have vias or have the inductor on a different layer than the microcontroller. As the switching frequency is high,
keeping traces in parallel reduces the electromagnetic field volume, increasing EMC performance.
An example of a minimized loop area for the KW36 40-pin wettable QFN package and the path the current will take is shown below.
NXP Semiconductors
Hardware design Guidelines
MKW4xZ/3xZ/3xA/2xZ DC-DC Power Management, Rev. 3, 04 June 2021
Application Note 17 / 28