NXP Semiconductors AN5025, Application Note

Page: 26 / 28

The image on the left shows the VDD_1P8 (pink) going from 3.3 V to 1.8 V, and the image on the right shows the opposite. Note
that immediately after setting the output voltage to a new level, the bit DCDC_STS_DC_OK (yellow) goes to low, and just after
output voltage stabilizes it is set back to 1.
6.4 DC-DC Efficiency
The power consumption is a function of the many configurations possible for the MCU platform. Below there are four examples
showing the real efficiency numbers to support the designer optimizing the system energy management.
The tests were performed on five samples using a testing board measured at -40ºC, 25ºC, and 125ºC.
FEI: Core: 48 MHz, Bus/Flash: 24 MHz (Fastest wake up condition)
PowerIn
0 0.100 0.075 0.025 0.050
85
80
90
95
75
PowerIn
0.025 0.125 0.100 0.050 0.075
90
88
92
94
86
PowerIn
0.025 0.125 0.100 0.050 0.075
90
89
91
92
93
94
88
PowerIn
0.050 0.150 0.125 0.075 0.100
90
89
91
92
88
VDCDC_IN = 3.7 V,
VDD_1P8 = 1.80 V
VDD_1P5 = 1.45 V
held constant at 0 mA and
VDD_1P8 load swept VDCDC_IN = 3.7 V,
VDD_1P8 = 1.80 V
VDD_1P5 = 1.45 V
held constant at 10 mA and
VDD_1P8 load swept
VDCDC_IN = 3.7 V,
VDD_1P8 = 1.80 V
VDD_1P5 = 1.45 V
held constant at 29 mA and
VDD_1P8 load swept VDCDC_IN = 3.7 V,
VDD_1P8 = 1.80 V
VDD_1P5 = 1.45 V
held constant at 15 mA and
VDD_1P8 load swept
ef
ficiency
ef
ficiency
ef
ficiency
ef
ficiency
Figure 21. DC-DC Efficiency on different scenarios for buck mode
NXP Semiconductors
Current estimation and efficiency report
MKW4xZ/3xZ/3xA/2xZ DC-DC Power Management, Rev. 3, 04 June 2021
Application Note 26 / 28