Is
DCDC Shutdown in Buck Manual Start
Mode
DCDC shutdown
not allowed
Write
to
N
Y
Figure 9. Flowchart of shutting down the DC-DC
Below is an example code to shut down DC-DC using the SDK 2.2:
if((DCDC->REG0 & DCDC_REG0_PSWITCH_STATUS_MASK) == 0)
{
DCDC_DoSoftShutdown(DCDC);
}
4.4.1 Software strategies when battery is running out
If the application needs to stop executing the code, for example, if battery is running out during the periodic VDCDC_IN
measurement, then the application can shut down the DC-DC, as explained previously. This makes the VDD_1P8 and VDD_1P5
to be in off state. In case the operation mode is not the Buck Manual Start Mode, it is not possible to shut down the DC-DC and
software may use an interrupt to decide how to handle a low battery situation.
In other applications, it may be advantageous to force a reset hold condition. To force a reset hold condition, a solution is to use
the Low Voltage Detect module that monitors VDD. The code needs to configure VDD_1P8, which supplies to VDD, to have a
value below V
LVDx
, for example if VDD_1P8 is configured to generate 1.8 V, when selecting the threshold V
LVDH
(2.56 V), the
microcontroller will immediately be hold on reset until a power-off and power-on cycle is performed. Note that if VDCDC_IN returns
to its normal value, as the VDD_1P8 is still programmed to be below V
LVDx
, just a complete power cycle releases the device from
reset condition.
4.5 System impact in function of registers configuration
This section details some specific bits that have no clear relation to how the system is impacted by selecting or disabling them.
These bits may be left on default state with no major impact. For more details, refer to below descriptions. You can also refer to
the latest device-specific Reference Manual for the most up-to-date descriptions.
4.5.1 DCDC_REG0
• DCDC_REG0[DCDC_DISABLE_AUTO_CLK_SWITCH]
In case the external clock is selected as the DC-DC clock source, and if the oscillator is lost, this feature automatically switches
to internal DC-DC oscillator to avoid DC-DC abnormal behavior.
• DCDC_REG0[DCDC_SEL_CLK]
This bit selects the external 32 MHz clock or the internal oscillator to drive DC-DC. Selecting the crystal oscillator leads to a better
and consistent DC-DC performance. This bit does not apply when DCDC_REG0[DCDC_DISABLE_AUTO_CLK_SWITCH] is 0.
NXP Semiconductors
DC-DC converter software setup
MKW4xZ/3xZ/3xA/2xZ DC-DC Power Management, Rev. 3, 04 June 2021
Application Note
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