background image

Is

DCDC Shutdown in Buck Manual Start

Mode

DCDC shutdown

not allowed

Write

to

N

Y

Figure 9. Flowchart of shutting down the DC-DC

Below is an example code to shut down DC-DC using the SDK 2.2:

if((DCDC->REG0 & DCDC_REG0_PSWITCH_STATUS_MASK) == 0)
{
DCDC_DoSoftShutdown(DCDC);
}

4.4.1 Software strategies when battery is running out

If the application needs to stop executing the code, for example, if battery is running out during the periodic VDCDC_IN
measurement, then the application can shut down the DC-DC, as explained previously. This makes the VDD_1P8 and VDD_1P5
to be in off state. In case the operation mode is not the Buck Manual Start Mode, it is not possible to shut down the DC-DC and
software may use an interrupt to decide how to handle a low battery situation.
In other applications, it may be advantageous to force a reset hold condition. To force a reset hold condition, a solution is to use
the Low Voltage Detect module that monitors VDD. The code needs to configure VDD_1P8, which supplies to VDD, to have a
value below V

LVDx

, for example if VDD_1P8 is configured to generate 1.8 V, when selecting the threshold V

LVDH 

(2.56 V), the

microcontroller will immediately be hold on reset until a power-off and power-on cycle is performed. Note that if VDCDC_IN returns
to its normal value, as the VDD_1P8 is still programmed to be below V

LVDx

, just a complete power cycle releases the device from

reset condition.

4.5 System impact in function of registers configuration

This section details some specific bits that have no clear relation to how the system is impacted by selecting or disabling them.
These bits may be left on default state with no major impact. For more details, refer to below descriptions. You can also refer to
the latest device-specific Reference Manual for the most up-to-date descriptions.

4.5.1 DCDC_REG0

• DCDC_REG0[DCDC_DISABLE_AUTO_CLK_SWITCH]

In case the external clock is selected as the DC-DC clock source, and if the oscillator is lost, this feature automatically switches
to internal DC-DC oscillator to avoid DC-DC abnormal behavior.

• DCDC_REG0[DCDC_SEL_CLK]

This bit selects the external 32 MHz clock or the internal oscillator to drive DC-DC. Selecting the crystal oscillator leads to a better
and consistent DC-DC performance. This bit does not apply when DCDC_REG0[DCDC_DISABLE_AUTO_CLK_SWITCH] is 0.

NXP Semiconductors

DC-DC converter software setup

MKW4xZ/3xZ/3xA/2xZ DC-DC Power Management, Rev. 3, 04 June 2021

Application Note

13 / 28

Summary of Contents for AN5025

Page 1: ...e the output voltages within the ranges shown in the table below provided that in Buck mode for all input ranges the outputs are lower than input voltage by 50 mV or higher than input voltage by 50 mV...

Page 2: ...orrect return signal without series resistance from VDD_1P8 to VDD_0 1 It is not possible to configure the DC DC for buck or boost modes while sourcing VDD_0 1 from an external source 3 DC DC Power mo...

Page 3: ...he better for efficiency 3 2 1 Buck Mode Manual Startup In this mode the DC DC is not automatically started upon the presence of voltage on VDCDC_IN Instead the DC DC is started after a pulse or level...

Page 4: ...mode manual start 3 2 2 Buck Mode Auto start This mode allows the DC DC to automatically turn on immediately after power is applied to the device Typical startup time is 2 3 ms and varies with the loa...

Page 5: ...t voltage in the range of 0 9 V to 1 795 V To guarantee startup the DC DC requires a minimum of 1 1 V The typical conversion efficiency is 90 In this mode the DC DC converter increases the input volta...

Page 6: ...C mode must change after the power is turned off and the pin configuration correctly set 4 DC DC converter software setup The DC DC operates in two different modes Continuous Mode and Pulsed Mode In C...

Page 7: ...e more than necessary and consumes more current than desired 4 1 Application Initialization Requirements To ensure optimum DC DC operation it is highly recommended to configure the Loop Control bits a...

Page 8: ...DC initialization The period for the Timer to trigger the measurement of the VDCDC_IN is user controlled and depends on the applications VDCDC_IN voltage dynamics Every time the application expects a...

Page 9: ...th VDD1P8 1 8V DCDC_Init mDCDCBuckDefaultConfig call to DCDC SDK Framework 4 2 Configuring Continuous mode The DC DC converter operates only in Continuous Mode when the MCU is in RUN WAIT and STOP mod...

Page 10: ...efficiency when loading is less than 0 5 mA As mentioned before larger tank capacitors on VDD_1P8 and VDD_1P5 lead to better efficiency in pulsed mode as the refresh time increases Pulsed mode is auto...

Page 11: ...reticLowerThresholdValue kDCDC_HystereticThresholdOffset0mV enableDiffComparators true Code DCDC Low Power Configuration DCDC_SetLowPowerConfig DCDC dcdc_Low_Power_Config Disable Stepping prior to cal...

Page 12: ...e performed on a test board containing just the microcontroller with device running in VLPR pulsed mode and a minimal number of internal modules enabled For this example which uses the default DC DC r...

Page 13: ...e microcontroller will immediately be hold on reset until a power off and power on cycle is performed Note that if VDCDC_IN returns to its normal value as the VDD_1P8 is still programmed to be below V...

Page 14: ...left disabled When powered on it reduces overshoot undershoot for high dynamic loading The response time increment gets configure on DCDC_REG2 DCDC_LOOPCTRL_EN_RCSCALE The tradeoff is that it increase...

Page 15: ...put replacing the normal size FET on low power modes pulsed This double FET has a smaller RDS resistance from drain to source but pre driver consumes a slightly higher current As the current consumpti...

Page 16: ...C DC switching works and the paths that the current take In a buck converter the higher frequency contents of the inductor current will circulate in one of two loops the first when charging charging p...

Page 17: ...8 13 11 M4 M3 9 10 12 M2 C410 C418 1 5 V Figure 12 Current loops of the two outputs of the DC DC converter in boost mode Physical location of the components in this route determines the area shape of...

Page 18: ...Figure 13 Current route during charging phase NXP Semiconductors Hardware design Guidelines MKW4xZ 3xZ 3xA 2xZ DC DC Power Management Rev 3 04 June 2021 Application Note 18 28...

Page 19: ...t should also be noted here that while surface mount capacitors are advantageous due to their size they have the negative side effect of often times having an actual capacitance less than their rated...

Page 20: ...value 10 uH 20 tolerance Inductor current rating 120 mA Buck mode Inductor current rating 320 mA Boost mode vdd1p8 supplying 1 8 V Inductor current rating 400 mA Boost mode vdd1p8 supplying 3 3 V Ind...

Page 21: ...to the device specific data sheet as this limit may not be the same for all devices Note the output current specification in either buck and boost modes represent the maximum current the DC DC convert...

Page 22: ...on is 12 96 mW Power IN x 90 Leaving a total of 112 mW assuming a 125 mW maximum power output 125 mW 12 96 mW available to power the RF portion and other circuits There is a maximum capacity for VDD_1...

Page 23: ...ce specific data sheet as to the actual limits at 1 8 V and 3 0 V Also note that other conditions such as VDD_1P8 voltage may affect these limits NOTE 6 3 DC DC timings 6 3 1 Turn on time The below os...

Page 24: ...until DC DC is stable yellow curve Just after the voltage stabilization occurs the application may add extra loads such as turning on internal modules or draining high current on GPIOs 6 3 2 Settle T...

Page 25: ...Figure 20 Settle time NXP Semiconductors Current estimation and efficiency report MKW4xZ 3xZ 3xA 2xZ DC DC Power Management Rev 3 04 June 2021 Application Note 25 28...

Page 26: ...MHz Fastest wake up condition PowerIn 0 0 100 0 075 0 025 0 050 85 80 90 95 75 PowerIn 0 025 0 125 0 100 0 050 0 075 90 88 92 94 86 PowerIn 0 025 0 125 0 100 0 050 0 075 90 89 91 92 93 94 88 PowerIn 0...

Page 27: ...tial release 1 03 2018 General updates 2 03 2020 Updates to Hardware Design Guidelines Clarifications of switching frequency Updates to voltage requirements 3 06 2021 Editorial updates NXP Semiconduct...

Page 28: ...rly check security updates from NXP and follow up appropriately Customer shall select products with security features that best meet rules regulations and standards of the intended application and mak...

Reviews: