PRELIMINARY ISD1700 SERIES
Publication Release Date: Nov 6, 2008
- 56 -
Revision 1.31
commands are sent while in this mode. The RDY bit of SR1 is Low until the device has
latched addresses and begun recording. If no further command is sent, the device will record
until end address <E10:E0> and write an EOM marker there. Once the RDY bit of SR1
returns to High, another SET_REC command can be sent. By doing so, a second pair of
START_ address and END_address is loaded into a FIFO buffer. So when the device
reaches the first end address, no EOM is written there and it automatically jumps to the
second start address, then continue the recording operation. During the record process,
power supply cannot be interrupted. Otherwise, it will cause the device malfunctioned.
11.4.3 SET_ERASE (0x82)
SCLK
MOSI
MISO
SS
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15 16 17
18 19
20
Data Byte 1
Command (82h)
Start Address (16 bits)
LSB
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20
MSB LSB
MSB LSB
21 22 23 24 25 26 27 28
29 30
31
S0 S1 S2 S3 S4
MSB
B22 B23
S6 S7
B24 B25 B26 B27 B28 B29 B30 B31
S8 S9 S10
S5
B21
X
X
X
X
X
Status Register 0 : Bytes #1 & #2
Status Register 0 : Bytes #1 & #2
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
End Address (24 bits)
MSB
LSB
B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52
B54 B55
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
X
X
X
X
X
X
X
X
X
X
X
X
X
B53
Status Register 0 : Bytes #1 & #2
Status Register 0 : Byte #1
SET_ERASE
Opcode 0x82 0x00
Interrupt
Yes
Byte Sequence:
MOSI
0x82
0x00
<S7:S0>
<00000
S10:S8>
<E7:E0> <00000
E10:E8>
0x00
MISO SR0
SR0
SR0
SR0
Description:
Start an erase operation from start address <S10:S0> to end address
<E10:E0> inclusive.
State before Execution
Idle
State after Execution
Idle
Registers Affected
SR0, SR1:ERASE, RDY
The SET_ERASE command erases rows from start address <S10:S0> to end address <E10:E0>
inclusively. In this mode, the device will only respond to RESET, CLR_INT, RD_STATUS and PD
commands. The CMD_ERR bit of SR0 is set when other commands are sent. The RDY bit of SR1 is
Low until erasure is completed and an interrupt is generated. During the erase process, power
supply cannot be interrupted. Otherwise, it will cause the device malfunctioned.
11.5 A
DDITIONAL
C
OMMAND
