PRELIMINARY ISD1700 SERIES
Publication Release Date: Nov 6, 2008
- 43 -
Revision 1.31
State before Execution
Any, except PD
State after Execution
PD
Registers Affected
SR0, SR1, APC
This command stops the current operation, if any, puts the device back to power down state,
and clears the status of interrupt & EOM bits. As a result, all interrupt & EOM bits are cleared
and
is released.
INT
11.1.4 CLR_INT(0x04)
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15
SCLK
MOSI
MISO
SS
Data Byte 1
Command (04h)
LSB
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LSB
MSB
Status Register 0 : Bytes #1 & #2
CLR_INT
Opcode: 0x04 0x00 Interrupt: No
Byte Sequence:
MOSI
0x04
0x00
MISO SR0
Description:
Read Status and Clear INT and EOM
State before Execution
Any
State after Execution
Does not affect state, clears the INT bit and INT pin.
Registers Affected
SR0: INT bit, EOM bit
The Clear Interrupt command reads the status of the device and clears the status of interrupt
& EOM bits. As a result, all interrupt & EOM bits are cleared and
INT
is released.
11.1.5 RD_STATUS (0x05)
RD_STATUS
Opcode: 0x05 0x00
0x00
Interrupt: No
Data Byte 1
Command (05h)
MSB
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
16 17
18 19
20
21
22
23
Data Byte 2
LSB
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23
SCLK
MOSI
MISO
SS
LSB
MSB
LSB
MSB
Status Register 0 : Bytes #1 & #2
Status Register 1
