Nuvoton ISD1700 series, Design Manual

Page: 36 / 82

PRELIMINARY ISD1700 SERIES
Publication Release Date: Nov 6, 2008
- 36 - Revision 1.31
SR0
Size: 16 bits Type: Read
Byte #1 Bit # : D7 D6 D5 D4 D3 D2 D1 D0
Name : A2 A1 A0 INT EOM PU FULL CMD_ERR
Byte #2 Bit # : D15 D14 D13 D12 D11 D10 D9 D8
Name : A10 A9 A8 A7 A6 A5 A4 A3
Description: Device status register
Access Every SPI command returns SR0 as first two bytes in MISO
Table 10.3 Bit description of Status Register 0
Bit Name Description
Byte #1
7 A2 Current row address bit 2
6 A1 Current row address bit 1
5 A0 Current row address bit 0
4 INT This bit is set to 1 when current operation is done. It can be cleared by
CLR_INT command.
3 EOM This bit is set to 1 when an EOM is detected. It can be cleared by CLR_INT
command.
2 PU This bit is set to 1 when the device is powered up and operating in SPI mode.
1 FULL This bit, when set to 1, indicates memory array is full. That means the device
cannot record any new messages unless old messages are deleted. This bit is
only valid when user follows push button format to program and erase the
array.
0 CMD_ERR This bit indicates the previous SPI command is invalid when is set to 1, if:
μ
C sends less than 5 bytes of row address,
SPI command is decoded but ignored.
Byte #2
15 A10 Current row address bit 10
14 A9 Current row address bit 9
13 A8 Current row address bit 8
12 A7 Current row address bit 7
11 A6 Current row address bit 6
10 A5 Current row address bit 5
9 A4 Current row address bit 4
8 A3 Current row address bit 3
SR0
where <A10:A0> is the active row of memory