PRELIMINARY ISD1700 SERIES
Publication Release Date: Nov 6, 2008
- 54 -
Revision 1.31
11.4 D
IRECT
M
EMORY
A
CCESS
C
OMMANDS
These types of commands allow the SPI host to perform random access to any memory location
by specifying the start and the end addresses. For the record and playback operations, the next
pair of addresses can be preloaded. As a result, the subsequent operation jumps to the next start
address seamlessly, when the operation on the first pair of addresses is finished.
All these commands require a START_ADDRESS and an END_ADDRESS. They operate from
START_ADDRESS to END_ADDRESS inclusively. Because the memory is configured as a
circular fashion, an END_ADDRESS smaller than START_ADDRESS is allowed. In this case, the
ISD1700 will wrap around from the last row of the memory to the address 0x010 (excluding the
SEs) and continue until END_ADDRESS is reached. If an END_ADDRESS is smaller than
START_ADDRESS and an END_ADDRESS is also smaller than 0x10, then it will cause the
device to loop endlessly, as the END_ADDRESS never matches the current address. Thus,
precautions must be paid to address to the beginning of the memory. Also, care must be taken in
accessing the SE rows (0x000-0x00F) and SEs should be handled independently.
11.4.1 SET PLAY (0x80)
SCLK
MOSI
MISO
SS
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15 16 17
18 19
20
Data Byte 1
Command (80h)
Start Address (16 bits)
LSB
B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20
MSB LSB
MSB LSB
21 22 23 24 25 26 27 28
29 30
31
S0 S1 S2 S3 S4
MSB
B22 B23
S8 S9 S10
S5
B21
S6 S7
X
X
X
X
X
B24 B25 B26 B27 B28 B29 B30 B31
Status Register 0 : Bytes #1 & #2
Status Register 0 : Bytes #1 & #2
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
End Address (24 bits)
MSB
LSB
B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52
B54 B55
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
X
X
X
X
X
X
X
X
X
X
X
X
X
B53
Status Register 0 : Bytes #1 & #2
Status Register 0 : Byte #1
SET_PLAY
Opcode 0x80 0x00 Interrupt
Yes
Byte Sequence:
MOSI
0x80
0x00
<S7:S0>
<00000
S10:S8>
<E7:E0> <00000
E10:E8>
0x00
MISO SR0
SR0
SR0
SR0
Description:
Start a playback operation from start address <S10:S0> to end address
<E10:E0> inclusive or stop at EOM, depending on the D11 of APC.
State before Execution
Idle
State after Execution
Idle
Registers Affected
SR0, SR1:PLAY, RDY
