Novatech Bitronics M87X Series, Manual

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ML0021 August 15, 2018
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Copyright 2018 Bitronics, LLC
duplex links cannot have collisions). Collisions are an expected part of normal half-duplex
Ethernet operations and the hardware transparently retries up to 16 times to send the
message. If collisions occur more often than about once per second, it indicates a very
heavily loaded network which is probably delivering messages late. If a large number of
collisions occur, it is suggested that either the network speed be increased to 100 Mb or
the hubs replaced with Ethernet switches.
8.12 Software Configuration
The M87x is able to determine the capabilities of the network equipment if the equipment
supports auto-negotiation. If auto-negotiation is not supported, the M87x will be able to
determine the network speed through a process known as parallel detection, but it cannot
determine the duplex capability. In order to allow the M87x to operate in half or full-duplex,
the user must supply the choice for the cases where the mode cannot be determined.
Each communication protocol will supply a method to individually set the 10 Mb and 100
Mb duplex values for these cases. Half-duplex is always the safest choice since it is
compatible with all legacy equipment. Full-duplex allows a potential doubling of the
network speed and an extension of the 100 Mb fiber length. Consult your network
administrator before setting the duplex configuration to full since this can cause serious
network problems if misapplied.
8.13 Technical Details
Bitronics has secured a block of Ethernet addresses from the IEEE. They are of the form:
00-D0-4F-xx-xx-xx
The actual unique 48-bit address is marked on the circuit board above the jumper block.
The remainder of this section may be skipped by casual users and is pertinent only to P1x
modules. The Ethernet board uses an AMD 79C972 ("Pcnet Fast+") media access
controller (MAC) which interfaces directly to shared PCI memory on the cPCI bus. It
interfaces to a National DP83843 ("PHYTER") Physical Layer Controller (PHY) via an on-
board MII interface. The PHY interfaces directly to the magnetics module of the copper
interface and the 100BASE-FX optical transceiver. It indirectly interfaces to the 10 Mb
optics via a Micro Linear ML4669 10BASE-FL to 10BASE-T adapter. The user jumper
block connects to the PHYTER AN0/AN1 pins and allows all 9 combinations of these pins
to be used. The Ethernet software driver allows access to a modified copy of the 16-bit
PHYSTS (PHY status) within the PHY for link type determination.
The Ethernet driver automatically manages link state changes. If the link is ever
determined to be lost, it continuously searches for a new link. This search begins by
resetting the PHY to allow the jumper block setting to be used. If this fails to provide a link,
the PHY is configured to auto-negotiate while advertising all combinations or 100BASE-
TX, 10BASE-T, half-duplex, and full-duplex. This will attempt linkage using both auto-
negotiation and parallel detection. If this fails and 10BASE-FL is supported, the PHY is
reconfigured for forced 10 Mb mode to allow the 4669 to transmit an optical link idle signal
(some network vendor’s equipment refuse to generate the optical link idle unless they
receive a link idle). If 100BASE-FX is supported, the PHY is reconfigured for forced 100
Mb mode using the PECL signals and an unscrambled data stream.