NM500 Manual
20
5
INTERCONNECTING CHIPS
One of the benefits of the NM500 architecture is that you can cascade multiple chips in parallel to expand the size
of the neural network by increment of 576 neurons. The behavior of the neurons in a single-chip or multiple-chips
configuration remains the same.
A chain of multiple chips is defined by connecting their NeuroMem bus together with external pull-up resistors
when applicable (refer to the pinout table for details).
The external controller sending Read/Write commands to a chain of chips must be careful to release the
bidirectional lines as soon as the Ready signal falls. Failure to do so will prevent the proper execution of commands
interconnecting all the neurons together through the bi-directional lines of DATA, ID_, and UNC_.
5.1
COUNTING THE NEURONS IN A CHAIN OF UNKNOWN LENGTH
-
Write NSR 0x10
Set the SR mode
-
Write TESTCAT Value
Commit all the neurons with a same category value
-
Write RESETCHAIN
Point to the 1
st
neuron in chain
-
Ncount=0
-
Do Loop
o
Read CAT, cat
o
+
-
Until cat=0xFFFF
(Ncount-1) is the number of neurons in the chain
-
Write NSR 0x00
Cancel the SR mode
5.2
VERIFYING THE PROPER INTERCONNECTIVITY OF THE ENTIRE CHAIN
When multiple chips are assembled in a chain, their inter-connectivity needs to be verified to ensure proper
learning and recognition. This inter-connectivity depends on mechanical and electrical constraints and this chapter
describes the recommended functional verifications:
