NM500 Manual
11
o
Write TESTCOMP=0
o
Write INDEXCOMP i
-
Write NSR 0x10
Set the SR mode
-
Write TESTCAT 0
Uncommit all the neurons
-
Write NSR 0x00
Cancel the SR mode, back to normal mode
2.2
REGISTERS ACCESS LATENCY
Accessing most registers takes a single clock cycle. In Learn and Recognition mode, reading and writing the LCOMP,
DIST and CAT registers can take between 3 and 19 clock cycles depending on the content of the neuron at the time
of the execution. This means that two neurons can execute a same instruction in different number of clock cycles
depending on its status and internal registers’ values. For example, a neuron which does not recognize an input
pattern will execute the RDIST instruction in 1 cycle, when a neuron which recognizes the pattern (i.e. fires) will
participate to the Search and Sort race for up to 16 clock cycles. The Ready line of the chip indicates when all the
neurons have finished the execution of an instruction and can receive a new one.
Write LCOMP (0x02), Read DIST (0x03), Read and Write CAT (0x04) are "snooping" commands meaning they are
making open collector bus mixing. The release of the DATA lines as well as the ID_ and UNC_ lines after the fall of
the DS signal is critical so they can snoop properly.
The following table reports the number of clock cycles (cc) necessary to read and write the registers of the chip.
The cycles are counted from the first rising edge of the system clock upon the receipt of the DS signal, to the rising
edge of the READY signal upon execution of the command.
Addr Register
Description
Learn and Recognition
mode
Save and Restore
mode
Write cycles
Read
cycles
Write
cycles
Read
cycles
0x00 NCR
Neuron Context Register
1
1
0x01 COMP
Component
1
1
1
0x02 LCOMP
Last Component
1 if no neurons
3 otherwise
0x03
0x03
INDEXCOMP
DIST
Component Index
Distance
1
18
1
1
0x04 CAT
Category
1 if ID, 19
otherwise
3 if ID, 19
otherwise
1
1
0x05 AIF
Active Influence Field
1
1
0x06 MINIF
Minimum Influence Field
1
1
1
0x07 MAXIF
Maximum Influence Field
1
1
0x08 TESTCOMP
Test Component
1
0x09 TESTCAT
Test Category
1
0x0A NID
Neuron Identifier
1
1
0x0B GCR
Global Context Register
1
1
0x0C RESETCHAIN
1
0x0D NSR
Network Status Register
1
1
0x0F FORGET
Clear the neurons
1
0x0F NCOUNT
Committed neurons
1
1