NM500 Manual
17
4
TYPICAL TIMINGS CONSTRAINTS
The DS, RW_, REG and DATA signals are updated at the negative edge of the system clock (G_CLK) so that they are
stable when the neurons read them at the next positive edge of G_CLK. The RDY signal is then immediately pulled
down by the neurons and released at the first positive edge of G_CLK following the completion of the command.
The duration during which the RDY signal is low represents the execution time of the command.
In the case of a Read command, the output DATA is ready to be read when RDY rises.
4.1
TIMINGS
All the neurons execute the commands simultaneously. Depending on their status (Idle, Ready-to-Learn or
Committed) and on the register to access, the Read and Write commands can take between 1 and 19 clock cycles.
The neurons sample signals on the positive edge of the system clock G_CLK. Their setup time must be at least 5
nanoseconds before the positive edge of G-Clock. The hold time must be at least 5 nanoseconds after the positive
edge of the clock.
The neurons pull down their RDY line when the DS rises and hold it down for the duration of the command. Upon
completion, the RDY line is pulled back up on the positive edge of the system clock.
The CS_ signal must be pulled down at the latest when the DS signal rises and it can be pulled back up at the
earliest when the RDY line rises back up.
A Write command (DS, RW_=0, REG, DATA) must be stable on the positive edge of the system clock and released
before the next positive edge of the system clock. The DATA lines must be released before the next positive edge
of the clock to ensure that the data bus becomes bi-directional for proper execution of the commands requiring
snooping of the bus.
A Read command (DS, RW_=1, REG) must be stable on the positive edge of the system clock and released before
the next positive edge of the system clock. DATA is stable when the RDY control line is pulled high.
Write in one cycle:
REG MINIF (0x06)
Read in one clock cycle:
REG CAT (0x04) in SR mode
