NM500 Manual
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1
OVERVIEW
The NM500 chip is a fully parallel silicon neural network: it is a chain of identical elements (i.e. neurons) addressed
in parallel and which have their own “genetic” material to learn and recall patterns without running a single line of
code and without reporting to any supervising unit. In addition, the neurons fully collaborate with each other
through a bi-directional and parallel neuron bus which is the key to accuracy, adaptivity and speed performance.
Indeed, each neuron incorporates information from all the other neurons into its own learning logic and into its
response logic.
The neurons can learn and recognize input vectors autonomously and in parallel. If several neurons recognize a
pattern (i.e. “fire”), their responses can be retrieved automatically in increasing order of distance (equivalent to a
decreasing order of confidence). The information which can be read from a firing neuron includes its distance,
category, and neuron identifier. If the response of several or all firing neurons is polled, this data can be
consolidated to make a more sophisticated decision weighing the cost of uncertainty or else.
1.1
ARCHITECTURE
The NM500 chip has a unique homogeneous architecture:
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Chain of identical neurons, daisy-chained Intra-Chip and Inter-Chip
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Neuron Interconnect module (switches, no controller or supervisor) which synchronize communication
between the neurons Intra-Chip and Inter-Chip.
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All neurons have the same behavior and execute the instructions in parallel independent from the cluster
or even chip they belong to.
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Selection of one out of two classifiers: K-Nearest Neighbor (KNN) or Radial Basis Function (RBF) and more
precisely a Restricted Coulomb Energy (RCE) neural network
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Recognition time is independent of the number of neurons in use
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Automatic model generator built into the neurons
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Save and Restore of the contents of the neurons
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Simple Register Transfer Level instruction set through of 15 registers
