NM500 Manual
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9
POWER CONSUMPTION
The NM500 is a neuromorphic memory chip and consequently it is in idle mode at all time except when executing
a command.
Power consumption Idle mode .....................< 1 micro amp at 3.3V with external pull-up resistors of 2.7 K Ohms
.......................................................................3.3 mWatts
9.1
PEAK POWER
Peak power occurs during the execution of Read or Write commands. Their latencies range between 30 ns to 1 µs
depending on the register to read or write.
Peak power depends on the clock frequency but most importantly on the values of the pull-up resistors attached
to the bidirectional lines of the NeuroMem bus.
9.2
INTRINSIC POWER
The intrinsic power consumption for a targeted number of recognitions per second can be calculated by
multiplying the number of cycles for a single recognition by the number of recognitions per second.
The number of cycles for a recognition depends on the length L of the vector and the level of details expected in
the recognition ranging from a simple status taking 1 Read command, or the list of the K nearest neighbors with K
ranging from 1 to a user defined value.
Operation
Clock cycles @35 Mhz (single chip)
L=256, N=576, K=3
@18 Mhz (multi-chips)
L=256, N=576, K=3
Learn a vector of length L
L+3 + 18
7.9 µs
15.4 µs
Status of a vector of length L
L+3+1
7.4 µs
14.4 µs
Best match of a vector of length L
L+3+37
8.3 µs
16.2 µs
Get the K top match of a vector of length L L+3+ (K*37) 9.1 µs
17.8 µs
Save/Restore N neurons
4+ (N*260) 4.27 ms
8.3 ms
9.3
U
POWER SAVING TIPS
Since the DATA bus is composed of 16 internal pull-up lines, the broadcast of a value other than 0xFFFF on this bus
will draw current until the execution of another command releasing its lines in whole or in part. The register
POWERSAVE allows the release of the DATA bus (back to 0xFFFF) when no other Write command is expected.
