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NEC uPD98502, User Manual

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Preliminary User’s Manual

µµµµ

PD98502

Network Controller

Document No. S15543EJ1V0UM00 (1st edition)
Date Published December 2001 NS  CP(K)

                              2001
Printed in Japan

Summary of Contents for uPD98502

Page 1: ...Preliminary User s Manual µ µ µ µPD98502 Network Controller Document No S15543EJ1V0UM00 1st edition Date Published December 2001 NS CP K 2001 Printed in Japan ...

Page 2: ...Preliminary User s Manual S15543EJ1V0UM 2 MEMO ...

Page 3: ...APTER 3 SYSTEM CONTROLLER 185 CHAPTER 4 ATM CELL PROCESSOR 229 CHAPTER 5 ETHERNET CONTROLLER 277 CHAPTER 6 USB CONTROLLER 309 CHAPTER 7 PCI CONTROLLER 370 CHAPTER 8 UART 414 CHAPTER 9 TIMER 424 CHAPTER 10 MICRO WIRE 427 APPENDIX A MIPS III INSTRUCTION SET DETAILS 431 APPENDIX B VR4120A COPROCESSOR 0 HAZARDS 590 ...

Page 4: ...ote No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should...

Page 5: ...are and information in the design of the customer s equipment shall be done under the full responsibility of the customer NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits software and information While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the...

Page 6: ... To gain an overall understanding of the function of the µPD98502 Read through all the chapters in sequence To check the electrical characteristics of the µPD98502 Refer to the separate data sheet Notation This manual uses the following conventions Data bit significance High order bits on the left side low order bits on the right side Active low XXXX_B Pin and signal names are suffixed with _B Not...

Page 7: ...ply 37 1 7 4 System control interface 38 1 7 5 Memory interface 39 1 7 6 PCI interface 41 1 7 7 ATM interface 43 1 7 8 Ethernet interface 45 1 7 9 USB interface 46 1 7 10 UART interface 47 1 7 11 Micro Wire interface 47 1 7 12 Parallel port interface 47 1 7 13 Boundary scan interface 47 1 7 14 I C open 48 1 7 15 I C pull down 48 1 7 16 I C pull down with resistor 48 1 7 17 I C pull up 48 1 8 I O R...

Page 8: ...116 2 1 4 System control coprocessor 117 2 1 5 CP0 registers 119 2 5 Exception Processing 129 2 5 1 Exception processing operation 129 2 5 2 Precision of exceptions 130 2 5 3 Exception processing registers 130 2 1 4 Details of exceptions 142 2 1 5 Exception processing and servicing flowcharts 158 2 2 Initialization Interface 165 2 2 1 Cold reset 165 2 2 2 Soft reset 165 2 2 3 VR4120A processor mod...

Page 9: ... 196 3 2 10 S_WRCR Warm Reset Control Register 197 3 2 11 S_WRSR Warm Reset Status Register 198 3 2 12 S_PWCR Power Control Register 199 3 2 13 S_PWSR Power Status Register 200 3 3 CPU Interface 201 3 3 1 Overview 201 3 3 2 Data rate control 201 3 3 3 Burst size control 201 3 3 4 Address decoding 201 3 3 5 Endian conversion 201 3 3 6 I O performance 203 3 4 Memory Interface 204 3 4 1 Overview 204 ...

Page 10: ...iagram of ATM cell processor 230 4 1 3 ATM cell processing operation overview 232 4 2 Memory Space 236 4 2 1 Work RAM and register space 237 4 2 2 Shared memory 237 4 3 Interruption 237 4 4 Registers for ATM Cell Processing 238 4 4 1 Register map 238 4 4 2 A_GMR General Mode Register 240 4 4 3 A_GSR General Status Register 240 4 4 4 A_IMR Interrupt Mask Register 241 4 4 5 A_RQU Receiving Queue Und...

Page 11: ...4 8 4 Mailbox 276 CHAPTER 5 ETHERNET CONTROLLER 277 5 1 Overview 277 5 1 1 Features 277 5 1 2 Block diagram of Ethernet controller block 277 5 2 Registers 279 5 2 1 Register map 279 5 2 2 En_MACC1 MAC Configuration Register 1 285 5 2 3 En_MACC2 MAC Configuration Register 2 286 5 2 4 En_IPGT Back to Back IPG Register 286 5 2 5 En_IPGR Non Back to Back IPG Register 286 5 2 6 En_CLRT Collision Regist...

Page 12: ... Buffer descriptor format 301 5 3 4 Frame transmission 302 5 3 5 Frame reception 305 5 3 6 Address Filtering 307 CHAPTER 6 USB CONTROLLER 309 6 1 Overview 309 6 1 1 Features 309 6 1 2 Internal block diagram 310 6 2 Registers 311 6 2 1 Register map 311 6 2 2 U_GMR USB General Mode Register 313 6 2 3 U_VER USB Frame Number Version Register 313 6 2 4 U_GSR1 USB General Status Register 1 314 6 2 5 U_I...

Page 13: ... settings 332 6 5 Data Transmit Function 334 6 5 1 Overview of transmit processing 334 6 5 2 Tx buffer configuration 334 6 5 3 Data transmit modes 337 6 5 4 VR4120A processing at data transmitting 338 6 5 5 USB controller processing at data transmitting 341 6 5 6 Tx indication 343 6 6 Data Receive Function 344 6 6 1 Overview of receive processing 344 6 6 2 Rx Buffer configuration 345 6 6 3 Receive...

Page 14: ...ss Register 392 7 5 6 P_PCDR PCI Configuration Data Register 392 7 5 7 P_IGSR Internal Bus side General Status Register 393 7 5 8 P_IIMR Internal Bus Interrupt Mask Register 394 7 5 9 P_PGSR PCI side General Status Register 395 7 5 10 P_IIMR Internal Bus Interrupt Mask Register 396 7 5 11 P_PIMR PCI Interrupt Mask Register 397 7 5 12 P_HMCR Host Mode Control Register 398 7 5 13 P_PCDR Power Consum...

Page 15: ...egister 426 9 3 4 TM1CSR Timer CH1 Count Set Register 426 9 3 5 TM0CCR Timer CH0 Current Count Register 426 9 3 6 TM1CCR Timer CH1 Current Count Register 426 CHAPTER 10 MICRO WIRE 427 10 1 Overview 427 10 2 Operations 428 10 2 1 Data read at the power up load 428 10 2 2 Accessing to EEPROM 428 10 3 Registers 429 10 3 1 Register map 429 10 3 2 ECCR EEPROM Command Control Register 429 10 3 3 ERDR EE...

Page 16: ...le Endian 62 2 7 CP0 Registers 63 2 8 MIPS III ISA CPU Instruction Formats 66 2 9 Pipeline Stages MIPS III Instruction Mode 84 2 10 Instruction Execution in the Pipeline 85 2 11 Pipeline Activities MIPS III 85 2 12 Branch Delay In MIPS III Instruction Mode 87 2 13 ADD Instruction Pipeline Activities In MIPS III Instruction Mode 88 2 14 JALR Instruction Pipeline Activities In MIPS III Instruction M...

Page 17: ...ontext Register Format 131 2 48 BadVAddr Register Format 132 2 49 Count Register Format 132 2 50 Compare Register Format 133 2 51 Status Register Format 134 2 52 Status Register Diagnostic Status Field 135 2 53 Cause Register Format 136 2 54 EPC Register Format 138 2 55 WatchLo Register Format 139 2 56 WatchHi Register Format 139 2 57 XContext Register Format 140 2 58 Parity Error Register Format ...

Page 18: ... 2 84 Writeback Flow 180 2 85 Refill Flow 180 2 86 Writeback Refill Flow 181 2 87 Non maskable Interrupt Signal 182 2 88 Hardware Interrupt Signals 183 2 89 Masking of Interrupt Request Signals 184 3 1 Bit and Byte Order of Endian Modes 227 3 2 Half word Data Array Example 227 3 3 Word Data Array Example 228 4 1 Block Diagram of ATM Cell Processor 230 4 2 AAL 5 Sublayer and ATM Layer 232 4 3 AAL 5...

Page 19: ...gram of Ethernet Controller 278 5 2 Tx FIFO Control Mechanism 295 5 3 Rx FIFO Control Mechanism 297 5 4 Buffer Structure for Ethernet Block 300 5 5 Transmit Descriptor Format 301 5 6 Receive Descriptor Format 301 5 7 Transmit Procedure 304 5 8 Receive Procedure 306 6 1 USB Controller Internal Configuration 310 6 2 USB Attachment Sequence 330 6 3 Mailbox Configuration 333 6 4 Division of Data into ...

Page 20: ... 7 1 The PCI Controller Block Diagram 370 7 2 Posted Write Transaction from Internal Bus to PCI 372 7 3 Non Posted Write Transaction from Internal Bus to PCI 373 7 4 Delayed Read Transaction from Internal Bus to PCI 374 7 5 Non Delayed Read Transaction from Internal Bus to PCI 375 7 6 Posted Write Transaction from PCI to Internal bus 377 7 7 Non Posted Write Transaction from PCI to Internal bus 37...

Page 21: ... Branch Instructions 79 2 18 Branch Instructions Extended ISA 80 2 19 Special Instructions 81 2 20 Special Instructions Extended ISA 1 2 81 2 20 Special Instructions Extended ISA 2 2 82 2 21 System Control Coprocessor CP0 Instructions 1 2 82 2 21 System Control Coprocessor CP0 Instructions 2 2 83 2 22 Operation in Each Stage of Pipeline MIPS III 86 2 23 Correspondence of Pipeline Stage to Interloc...

Page 22: ... 1 List of Tx Packet Attribute 249 4 2 List of Rx Pool Attributes 253 4 3 Commands 257 4 4 Reception Errors That Can Occur During Packet Reception 275 4 5 Error Reporting Priorities 275 5 1 Ethernet Controller s Register Categories 279 5 2 MAC Control Register Map 279 5 3 Statistics Counter Register Map 281 5 4 DMA and FIFO Management Registers Map 283 5 5 Interrupt and Configuration Registers Map...

Page 23: ...ity for specification update Supports CBR VBR UBR service classes Includes 2 channel 10 100 Mbps Ethernet controller compliant to IEEE802 3 IEEE 802 3u and IEEE802 3x Can directly connect external Ethernet PHY device through 3 3 V MII interface Includes USB full speed function controller compliant to USB specification 1 1 Supports operation conforming to the USB Communication Device Class Specific...

Page 24: ...on in a single chip By selecting user interface examples of system configuration will be realized as shown below USB and Ethernet functions will exclusively operate each other Figure 1 1 Examples of the µ µ µ µPD98502 System Configuration a ADSL MODEM USB PCI PC µPD98502 POTS SPLITTER ADSL SDRAM ADSL PHY FLASH ADSL AFE b ADSL ROUTER 100B T PC PC µPD98502 MII POTS SPLITTER ADSL SDRAM ADSL PHY Ether...

Page 25: ...ram of the µ µ µ µPD98502 SDRAM ATM Cell Processor Full Speed USB Controller Ethernet Controller 1 2 System Controller VR4120A RISC Processor Core JTAG PHY Management 16 5 25 33 MHz UTOPIA 2 3 3V MII RS 232C Micro Wire USB PCI Controller 32 bit PCI Interface IBUS Parallel Port PROM Flash JTAG Control Clock Control ...

Page 26: ... together with large size instruction cache Features of VR4120A RISC Processor Core are as follows MIPS I II III instruction set will be supported FPU LL LLD SC SCD instruction will be excluded Realize high speed processing of application by supporting high speed multiply and accumulate function Includes large size cache memory Instruction 16 Kbytes Data 8 Kbytes Supports up to 1T byte virtual add...

Page 27: ...supports the following bus protocols Single read write transfer Burst read write transfer Slave lock Retry and disconnect Bus parking Figure 1 4 Block Diagram of IBUS System Controller ATM Cell Processor Ethernet Controller 1 2 USB Controller PCI Controller IBUS IBUS arbiter IBUS Master I F IBUS Slave I F decoder IBUS MUX BUS MASTER BUS SLAVE Using MUX Bus Arrangement IBUS Interface Block ...

Page 28: ...and Memory Supports Endian Converting function on SysAD bus Can directly connect SDRAM MAX 32 MBytes and PROM Flash MAX 8 MBytes memory Supports all VR4120A bus cycles at 66 MHz or 100 MHz PROM Flash data signals multiplexed on SDRAM data signals Supports 266 MB sec 32 bits 66 MHz bursts on IBUS Generates NMI and INT Supports NS16550 compatible Universal Asynchronous Receiver Transmitter UART Supp...

Page 29: ...PIA level 2 including management interface as PHY layer interface Supports processing AAL2 AAL5 Raw cell AAL0 and F5 OAM cells Supports 3 service classes CBR VBR UBR Supports up to 50 Mbps Cell speed together with upstream and downstream Supports fine grain ATM cell shaping in 1cell sec granularity on per VC basis Figure 1 6 Block Diagram of ATM Cell Processor ATM Cell Processor IBUS Controller IB...

Page 30: ...02 3u Supports full duplex operation for both 100 Mbps and 10 Mbps Supports flow control function compliant to IEEE802 3x D3 2 Implements 256 Byte FIFO buffer for each Tx and Rx Implements address filtering functions for unicast multicast broadcast Implements MIB counters for network management MIB II Ether like MIB IEEE802 3LME are supported Implements local DMA controller with individual DMA cha...

Page 31: ...nts 7 kinds of endpoints Control Interrupt IN OUT Isochronous IN OUT Bulk IN OUT Implements 64 Bytes FIFO buffer used for Control transfer for Tx Implements 128 Bytes FIFO buffer used for Isochronous transfer for Tx Implements 128 Bytes FIFO buffer used for Bulk transfer for Tx Implements 64 Bytes FIFO buffer used for Interrupt transfer for Tx Implements 128 Bytes shared FIFO buffer used for Contr...

Page 32: ...Supports PCI Dual Address Cycle as master 33 MHz PCI frequency capable Compliant to PCI Local Bus Specification Rev 2 2 Compliant to PCI Bus Power Management Interface Rev 1 1 Supports up to 16 words burst for each directions Implements PCI bus arbiter that supports up to 4 external PCI master devices at Host mode Figure 1 9 Block Diagram of PCI Bus controller PCI Slave IBUS Master PCI Master IBUS...

Page 33: ...1V0UM 33 1 6 Pin Configuration Bottom View 500 pin Tape BGA Heat spread type 40 40 µPD98502N7 H6 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A 30 29 28 27 AK AJ AH AG Index Mark ...

Page 34: ...IVDD E13 POM0 H2 SMA7 A17 IC OPEN B26 IC OPEN D5 SMD3 E14 GND H3 SMA9 A18 IC PDnR B27 PUMD D6 SMD6 E15 POM7 H4 IVDD A19 IC OPEN B28 PHINT_B D7 EVDD E16 GND H5 GND A20 IC OPEN B29 PRSTO_B D8 IVDD E17 GND H26 GND A21 IC PDn B30 PGTO0_B D9 URCLK E18 IC OPEN H27 IVDD A22 JCK C1 SMA2 D10 IVDD E19 GND H28 PCBE0_B A23 JMS C2 GND D11 GND E20 IC PDn H29 PAD9 A24 EVDD C3 SMA16 D12 IVDD E21 GND H30 GND A25 E...

Page 35: ... T1 SMD8 W30 PAD27 AC29 IC OPEN AF18 EVDD M3 SMD29 T2 GND Y1 IC OPEN AC30 PINT_B AF19 GND M4 IVDD T3 CLKUSL1 Y2 PSDGND AD1 MIRD2 AF20 UMWR_B M5 GND T4 CLKUSL0 Y3 PSAGND AD2 MIRD1 AF21 GND M26 GND T5 EVDD Y4 PSAVD AD3 MIRCLK AF22 EVDD M27 IVDD T26 PAD22 Y5 PSDVD AD4 MIRER AF23 GND M28 PSTP_B T27 IVDD Y26 PAD31 AD5 MIRDV AF24 GND M29 PDSEL_B T28 GND Y27 PME_B AD26 GND AF25 EVDD M30 EVDD T29 PAD23 Y2...

Page 36: ...OPEN AJ4 GND AJ26 UMD1 AK18 UDTD3 AG21 IVDD AH13 EVDD AJ5 MI2RER AJ27 GND AK19 UDTD0 AG22 UMD10 AH14 UDTSC AJ6 GND AJ28 GND AK20 UMRST_B AG23 IVDD AH15 EVDD AJ7 MI2TD1 AJ29 UMAD6 AK21 UMRD_B AG24 UMD2 AH16 UDTAD1 AJ8 UDRE_B AJ30 UMAD4 AK22 UMD14 AG25 UMAD11 AH17 UDTD4 AJ9 UDRD6 AK1 MI2RD3 AK23 UMD12 AG26 UMAD9 AH18 UDTD2 AJ10 UDRD3 AK2 MI2RD2 AK24 UMD8 AG27 IVDD AH19 UMINT_B AJ11 UDRAD4 AK3 MI2RCL...

Page 37: ...AH23 AH8 AJ13 AJ14 AJ16 AJ18 AJ20 AJ27 AJ28 AJ4 AJ6 GND 0 V IVDD A16 C26 D10 D12 D14 D17 D19 D21 D23 D27 D4 D8 H27 H4 K27 K4 M27 M4 P27 P4 T27 U27 U4 V4 W2 W27 W4 AA27 AA4 AC27 AC4 AE4 AG10 AG12 AG14 AG17 AG19 AG21 AG23 AG27 AG30 AG4 AG6 AG8 AH26 AJ15 Internal logic core power supply 2 5 V EVDD A24 A25 B15 C11 D7 E22 E25 E6 E9 F26 F5 G28 G4 J26 J5 K30 L5 M1 M30 R1 R26 T5 U30 W29 AA30 AB26 AB5 AD27...

Page 38: ...rough PSTBY AA2 I System PLL standby mode control 0 active 1 standby PUMD B27 I USB PLL mode control 0 normal 1 through PUSTBY D25 I USB PLL standby mode control 0 active 1 standby BIG D16 I H VR4120 big endian mode ENDCEN C15 I Endian conversion enable EXINT_B A15 I L External interrupt EXNM_BI A13 I L External non maskable interrupt RSTB_B AB30 I L System reset RMSL0 E11 I ROM access bus width s...

Page 39: ... SMA3 J2 O Memory address SMA4 H1 O Memory address SMA5 J3 O Memory address SMA6 J4 O Memory address SMA7 H2 O Memory address SMA8 G1 O Memory address SMA9 H3 O Memory address SMA10 E4 O Memory address SMA11 D3 O Memory address SMA12 B1 O Memory address SMA13 A1 O Memory address SMA14 B2 O Memory address SMA15 G2 O Memory address SMA16 C3 O Memory address SMA17 F1 O Memory address SMA18 J1 O Memor...

Page 40: ... P3 I O Memory data SMD16 E7 I O Memory data SMD17 B5 I O Memory data SMD18 C6 I O Memory data SMD19 A5 I O Memory data SMD20 B6 I O Memory data SMD21 C7 I O Memory data SMD22 A6 I O Memory data SMD23 B7 I O Memory data SMD24 N1 I O Memory data SMD25 N2 I O Memory data SMD26 N4 I O Memory data SMD27 N5 I O Memory data SMD28 M2 I O Memory data SMD29 M3 I O Memory data SMD30 L4 I O Memory data SMD31...

Page 41: ...and and byte enable PCBE1_B L26 I OZ L Bus command and byte enable PCBE2_B N30 I OZ L Bus command and byte enable PCBE3_B T30 I OZ L Bus command and byte enable PRQO_B Y28 O L Bus request out PRQI0_B C30 I L Bus request in 0 PRQI1_B D29 I L Bus request in 1 PRQI2_B E28 I L Bus request in 2 PRQI3_B E27 I L Bus request in 3 PGTI_B AA28 I L Bus grant in PGTO0_B B30 O L Bus grant out 0 PGTO1_B C29 O L...

Page 42: ... P29 I OZ PCI address and data PAD18 P30 I OZ PCI address and data PAD19 R27 I OZ PCI address and data PAD20 R28 I OZ PCI address and data PAD21 R30 I OZ PCI address and data PAD22 T26 I OZ PCI address and data PAD23 T29 I OZ PCI address and data PAD24 V28 I OZ PCI address and data PAD25 V27 I OZ PCI address and data PAD26 V26 I OZ PCI address and data PAD27 W30 I OZ PCI address and data PAD28 W28...

Page 43: ...HY address UMAD4 AJ30 O PHY address UMAD5 AK30 O PHY address UMAD6 AJ29 O PHY address UMAD7 AH28 O PHY address UMAD8 AH27 O PHY address UMAD9 AG26 O PHY address UMAD10 AK28 O PHY address UMAD11 AG25 O PHY address UMD0 AK27 I O Management data UMD1 AJ26 I O Management data UMD2 AG24 I O Management data UMD3 AK26 I O Management data UMD4 AJ25 I O Management data UMD5 AH24 I O Management data UMD6 AK...

Page 44: ... AG11 I Receive data UDRD1 AF11 I Receive data UDRD2 AK10 I Receive data UDRD3 AJ10 I Receive data UDRD4 AH10 I Receive data UDRD5 AK9 I Receive data UDRD6 AJ9 I Receive data UDRD7 AK8 I Receive data UDTCLK AK16 O Transmit clock UDTCLV AH11 I H Transmit cell available UDTE_B AK14 O L Transmit enable UDTSC AH14 O H Transmit cell start position UDTAD0 AG16 O Transmit PHY address UDTAD1 AH16 O Transm...

Page 45: ...OL AH3 I Collision MICRS AF2 I Carrier sense MIRCLK AD3 I Receive clock 2 5 25 MHz MIRDV AD5 I Receive data valid MIRER AD4 I Receive error MIRD0 AE1 I Receive data MIRD1 AD2 I Receive data MIRD2 AD1 I Receive data MIRD3 AC2 I Receive data MITCLK AH1 I Transmit clock 2 5 25 MHz MITE AF1 O Transmit enable MITER AE3 O Transmit error MITD0 AJ1 O Transmit data MITD1 AH2 O Transmit data MITD2 AG3 O Tra...

Page 46: ...RDV AK4 I Receive data valid MI2RER AJ5 I Receive error MI2RD0 AH4 I Receive data MI2RD1 AJ3 I Receive data MI2RD2 AK2 I Receive data MI2RD3 AK1 I Receive data MI2TCLK AK5 I Transmit clock 2 5 25 MHz MI2TE AF7 O Transmit enable MI2TER AH6 O Transmit error MI2TD0 AK7 O Transmit data MI2TD1 AJ7 O Transmit data MI2TD2 AK6 O Transmit data MI2TD3 AH7 O Transmit data 1 7 9 USB interface Pin Name Pin No ...

Page 47: ...icro Wire chip select MWDI A12 I Micro Wire data in MWDO B12 O Micro Wire data out MWSK A11 O Micro Wire SK 1 7 12 Parallel port interface Pin Name Pin No I O Active Level Function POM0 E13 O Parallel port signal output POM1 D13 O Parallel port signal output POM2 C13 O Parallel port signal output POM3 B13 O Parallel port signal output POM4 C14 O Parallel port signal output POM5 B14 O Parallel port...

Page 48: ...18 D20 E18 Y1 AA1 AB1 AB27 AB28 AC28 AC29 AD29 AH12 AJ12 O 1 7 15 I C pull down Pin Name Pin No I O Active Level Function IC PDn A21 B21 E20 AB4 I 1 7 16 I C pull down with resistor Pin Name Pin No I O Active Level Function IC PDnR A18 D15 AE30 AD28 AE27 AE28 AE29 AF28 AF29 AF30 I O 1 7 17 I C pull up Pin Name Pin No I O Active Level Function IC PUp U3 V3 W1 W3 AB3 AC1 AK29 I ...

Page 49: ...d Transmitting Cell Counter ATM F098H 4 A_RUEC R Receive Unprovisioned VPI VCI Error Cell Counter ATM F09CH 4 A_RIDC R Receiving Internal Discarded Cell Counter ATM F0A0H F0AFH N A Reserved for future use ATM F0B0H F0B3H N A Reserved for future use ATM F0B4H F0BCH N A Reserved for future use ATM F0C0H 4 A_T1R R W T1 Timer Register ATM F0C4H N A Reserved for future use ATM F0C8H 4 A_TSR R W Time St...

Page 50: ...H N A Reserved for future use Ether DCH 4 En_CAR1 R W Carry register 1 Ether E0H 4 En_CAR2 R W Carry register 2 Ether E4H 12CH N A Reserved for future use Ether 130H 4 En_CAM1 R W Carry mask register 1 Ether 134H 4 En_CAM2 R W Carry mask register 2 Ether 138H 13CH N A Reserved for future use Ether 140H 4 En_RBYT R W Receive Byte Counter Ether 144H 4 En_RPKT R W Receive Packet Counter Ether 148H 4 ...

Page 51: ... W Interrupt Mask Register SYSCNT 10H 4 S_NSR R NMI Status Register SYSCNT 14H 4 S_NER R W NMI Enable Register SYSCNT 18H 4 S_VER R Version Register SYSCNT 1CH 4 S_IOR R W IO Port Register SYSCNT 20H 2FH N A Reserved for future use SYSCNT 30H 4 S_WRCR W Warm Reset Control Register SYSCNT 34H 4 S_WRSR R Warm Reset Status Register SYSCNT 38H 4 S_PWCR W Power Control Register SYSCNT 3CH 4 S_PWSR R Po...

Page 52: ..._EP2CR R W USB EP2 Control Register USB 2CH 4 U_EP3CR R W USB EP3 Control Register USB 30H 4 U_EP4CR R W USB EP4 Control Register USB 34H 4 U_EP5CR R W USB EP5 Control Register USB 38H 4 U_EP6CR R W USB EP6 Control Register USB 3CH N A Reserved for future use USB 40H 4 U_CMR R W USB Command Register USB 44H 4 U_CA R W USB Command Address Register USB 48H 4 U_TEPSR R USB Tx EndPoint Status Register...

Page 53: ...00_3000H 1000_2FFFH 2000_0000H 1FFF_FFFFH FFFF_FFFFH 1F00_0000H 1EFF_FFFFH 1002_0000H 1000_FFFFH ATM Cell Processor 1001_0000H 1001_FFFFH 0000_0000H 4 KB 4 KB 4 KB 64 KB 16 MB 256 MB 1000_4000H 1000_3FFFH 4 KB Actual size of PROM Flash is max 8 MB Configuration 1 MB 1FCF_FFFFH 1FC0_0000H 2 MB 1FDF_FFFFH 1FC0_0000H Actual size of SDRAM is max 32 MB Configuration 04 MB 003F_FFFFH 0000_0000H 08 MB 00...

Page 54: ...g edge of RST_B signal After 2 VR4120A clock internal VCLOCK cycles at rising edge of the RST_B the System Controller deasserts the CLKSET signal synchronously with clkm Then 16 clkm cycles see section 1 12 at the rising edge of the RST_B signal the System Controller deasserts the COLDRST synchronously with clkm And also the System Controller deasserts the HOTRST synchronously with clkm after 16 c...

Page 55: ...ble interrupts and Non Maskable to the CPU Figure 1 12 Interrupt Signal Connection USB Controller Ethernet Controller 1 ATM Cell Processor System Controller VR4120A S_ISR intb 0 intb 1 intb 2 intb 4 intb 3 EXTNM I EXTINT nm ib S_IM R BUS IF UART TIM ER Ethernet Controller 2 S_NSR S_NER DSU BUS IF PCI Controller ...

Page 56: ...ATM Cell Processor 33 25 16 5 MHz 66 MHz USB Controller 48 MHz USBCLK 12 MHz Peripheral 100 66 MHz System Controller macstop usbstop atmstop 1 3 SCLK 33 MHz 100 66MHz 66 MHz Ethernet Controller 1 25 MHz 25 MHz MIRCLK 25 MHz MITCLK 25 MHz 66 MHz 66 MHz Ethernet Controller 2 25 MHz 25 MHz MIRCLK 25 MHz MITCLK 25 MHz 66 MHz PCI Controller PCICLK 33 MHz 66 MHz IBUS pcistop mac2stop CLO CK ENABLER CLO ...

Page 57: ...rnal block diagram of the VR4120A core In addition to the conventional high performance integer operation units this CPU core has the full associative format translation look aside buffer TLB which has 32 entries that provide mapping to 2 page pairs odd and even for one entry Moreover it also has instruction caches data caches and bus interface Figure 2 1 VR4120A Core Internal Block Diagram CPU CP...

Page 58: ...ting address conversion The translation lookaside buffer TLB converts virtual addresses to physical addresses 2 1 1 3 Instruction cache The instruction cache employs direct mapping virtual index and physical tag Its capacity is 16 Kbytes 2 1 1 4 Data cache The data cache employs direct mapping virtual index physical tag and write back Its capacity is 8 Kbytes 2 1 1 5 CPU bus interface The CPU bus ...

Page 59: ... and Link instructions This register can be used for other instructions However be careful that use of the register by a link instruction will not coincide with use of the register for other operations The register group is provided within the CP0 system control coprocessor to process exceptions and to manage addresses CPU registers can operate as either 32 bit or 64 bit registers depending on the...

Page 60: ...set b Computational instructions perform arithmetic logical shift and multiply and divide operations on values in registers They include R type in which both the operands and the result are stored in registers and I type in which one operand is a 16 bit signed immediate value formats c Jump and branch instructions change the control flow of a program Jumps are always made to an absolute address fo...

Page 61: ... Endian Byte Ordering in Word Data 12 12 13 14 15 0 15 16 8 23 24 7 31 8 8 9 10 11 4 4 5 6 7 0 0 1 2 3 Low order address High order address Word address Bit No Remarks 1 The lowest byte is the lowest address 2 The address of word data is specified by the lowest byte s address Figure 2 5 Little Endian Byte Ordering in Double Word Data 16 23 0 31 32 8 7 63 8 0 Low order address High order address Do...

Page 62: ...SDR These instructions are used in pairs to provide an access to misaligned data Accessing misaligned data incurs one additional instruction cycle over that required for accessing aligned data Figure 2 6 shows the access of a misaligned word that has byte address 3 for the little endian conventions Figure 2 6 Misaligned Word Accessing Little Endian 5 6 4 0 15 16 8 23 24 7 31 3 Low order address Hi...

Page 63: ...scriptions of the registers related to the virtual system memory refer to Section 2 4 Memory Management System For the detailed descriptions of the registers related to exception handling refer to Section 2 5 Exception Processing Figure 2 7 CP0 Registers 0 Notes 1 for Memory management 2 for Exception handling Remark RFU Reserved for future use Register No Register name Index Note 1 1 Random Note ...

Page 64: ...rogram Counter 15 PRId Processor revision identifier 16 Config Configuration register specifying memory mode system 17 LLAddr Reserved for future use 18 WatchLo Memory reference trap address low bits 19 WatchHi Memory reference trap address high bits 20 XContext Pointer to kernel virtual PTE in 64 bit mode 21 to 25 Reserved for future use 26 PErr Note Cache parity bits 27 CacheErr Note Index and s...

Page 65: ...Gbyte physical address space The page size can be configured on a per entry basis to map a page size of 1 KB to 256 KB A CP0 register stores the size of the page to be mapped and that size is entered into the TLB when a new entry is written Thus operating systems can provide special purpose maps for example a typical frame buffer can be memory mapped using only one TLB entry Translating a virtual ...

Page 66: ...uently used instruction and addressing modes from these three formats as needed Figure 2 8 MIPS III ISA CPU Instruction Formats I type immediate op 0 15 16 20 21 25 26 31 J type jump op target 0 25 26 31 R type register immediate funct sa rd target 6 bit function field 5 bit shift amount 5 bit destination register specifier 26 bit unconditional branch target address 16 bit immediate value branch d...

Page 67: ...ssors For detail see Section 2 3 Pipeline 2 Store delay slot When a store instruction is writing data to a cache the data cache is kept busy at the DC and WB stages If an instruction such as load that follows directly the store instruction accesses the data cache in the DC stage a hardware driven interlock occurs To overcome this problem the store delay slot should be scheduled Table 2 2 Number of...

Page 68: ...2 1 0 63 0 Doubleword 7 0 0 0 7 6 5 4 3 2 1 0 7 byte 6 0 0 0 6 5 4 3 2 1 0 0 0 1 7 6 5 4 3 2 1 6 byte 5 0 0 0 5 4 3 2 1 0 0 1 0 7 6 5 4 3 2 5 byte 4 0 0 0 4 3 2 1 0 0 1 1 7 6 5 4 3 Word 3 0 0 0 3 2 1 0 1 0 0 7 6 5 4 Triple byte 2 0 0 0 2 1 0 0 0 1 3 2 1 1 0 0 6 5 4 1 0 1 7 6 5 Halfword 1 0 0 0 1 0 0 1 0 3 2 1 0 0 5 4 1 1 0 7 6 Byte 0 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 ...

Page 69: ... 64 bits Load Word Left LWL rt offset base The offset is sign extended and then added to the contents of the register base to form the virtual address Shifts to the left the word whose address is specified so that the address specified byte is at the left most position of the word The result of the shift operation is merged with the contents of register rt and loaded to register rt In the 64 bit m...

Page 70: ...aded to register rt Load Doubleword Right LDR rt offset base The offset is sign extended and then added to the contents of the register base to form the virtual address Shifts to the right the double word whose address is specified so that the address specified byte is at the right most position of the double word The result of the shift operation is merged with the contents of register rt and loa...

Page 71: ...tored into register rt In the 64 bit mode the operand must be sign extended No exception occurs on the generation of integer overflow Set On Less Than Immediate SLTI rt rs immediate The 16 bit immediate is sign extended and then compared to the contents of register rt treating both operands as signed integers If rs is less than the immediate the result is set to 1 otherwise the result is set to 0 ...

Page 72: ...ed into register rd In the 64 bit mode the operand must be sign extended An exception occurs on the generation of integer overflow Subtract Unsigned SUBU rd rs rt The contents of register rt are subtracted from the contents of register rs The 32 bit result is stored into register rd In the 64 bit mode the operand must be sign extended No exception occurs on the generation of integer overflow Set O...

Page 73: ... operand must be sign extended Shift Right Logical SRL rd rs sa The contents of register rt are shifted right by sa bits and zeros are inserted into the emptied higher bits The 32 bit result is stored into register rd In the 64 bit mode the operand must be sign extended Shift Right Arithmetic SRA rd rt sa The contents of register rt are shifted right by sa bits and the emptied higher bits are sign...

Page 74: ...ed into register rd Doubleword Shift Right Logical Variable DSRLV rd rt rs The contents of register rt are shifted right and zeros are inserted into the emptied higher bits The lower six bits of register rs specify the shift count The 64 bit result is stored into register rd Doubleword Shift Right Arithmetic Variable DSRAV rd rt rs The contents of register rt are shifted right and the emptied high...

Page 75: ...ster rt treating both operands as 32 bit signed integers The 32 bit quotient is stored into special register LO and the 32 bit remainder is stored into special register HI In the 64 bit mode the operand must be sign extended Divide Unsigned DIVU rs rt The contents of register rs are divided by that of register rt treating both operands as 32 bit unsigned integers The 32 bit quotient is stored into...

Page 76: ...r rd if h 1 the same data as that stored in register HI is also stored in register rd If u is specified the operand is treated as unsigned data If s is specified registers rs and rd are treated as a 16 bit value 32 bits sign or zero extended and the value obtained by combining registers HI and LO is treated as a 32 bit value 64 bits sign or zero extended Moreover saturation processing is performed...

Page 77: ...of Delay Slot Cycles in Jump and Branch Instructions Instruction Necessary Number of Cycles Branch instruction 1 Jump instruction 1 1 Overview of jump instructions Subroutine calls in high level languages are usually implemented with J or JAL instructions both of which are J type instructions In J type format the 26 bit target address shifts left 2 bits and combines with the high order 4 bits of t...

Page 78: ...ne instruction Jump And Link Register JALR rs rd The program jumps to the address specified in register rs with a delay of one instruction The address of the instruction following the delay slot is stored into rd There are the following common restrictions for Tables 2 17 and 2 18 3 Branch address All branch instruction target addresses are computed by adding the address of the instruction in the ...

Page 79: ...contents of register rs are greater than or equal to zero the program branches to the target address Branch On Less Than Zero And Link BLTZAL rs offset The address of the instruction that follows delay slot is stored to register r31 link register If the contents of register rs are less than zero the program branches to the target address Branch On Greater Than Or Equal To Zero And Link BGEZAL rs o...

Page 80: ...ss If the branch condition is not met the instruction in the delay slot is discarded Branch On Less Than Zero And Link Likely BLTZALL rs offset The address of the instruction that follows delay slot is stored to register r31 link register If the contents of register rs are less than zero the program branches to the target address If the branch condition is not met the instruction in the delay slot...

Page 81: ... register rt treating both operands as signed integers If the contents of register rs are greater than or equal to that of register rt an exception occurs Trap If Greater Than Or Equal Unsigned TGEU rs rt The contents of register rs are compared with that of register rt treating both operands as unsigned integers If the contents of register rs are greater than or equal to that of register rt an ex...

Page 82: ...ng both operands as unsigned integers If the contents of register rs are less than 16 bit sign extended immediate data an exception occurs Trap If Equal Immediate TEQI rs immediate If the contents of register rs and immediate data are equal an exception occurs Trap If Not Equal Immediate TNEI rs immediate If the contents of register rs and immediate data are not equal an exception occurs 2 2 2 5 S...

Page 83: ...es with the contents of entryHi register is loaded into the index register Return From Exception ERET The program returns from exception interrupt or error trap Instruction Format and Description STANDBY STANDBY The processor s operating mode is transited from fullspeed mode to standby mode SUSPEND SUSPEND The processor s operating mode is transited from fullspeed mode to suspend mode HIBERNATE HI...

Page 84: ...struction mode The VR4120A has a five stage instruction pipeline each stage takes one PCycle and each PCycle has two phases Φ1 and Φ2 as shown in Figure 2 9 Thus the execution of each instruction takes at least 5 PCycles An instruction can take longer for example if the required data is not in the cache the data must be retrieved from main memory Figure 2 9 Pipeline Stages MIPS III Instruction Mod...

Page 85: ...1 DC2 WB1 WB2 IF1 IF2 RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2 2 3 1 2 Pipeline activities 1 MIPS III instruction Figure 2 11 shows the activities that can occur during each pipeline stage in MIPS III Instruction mode Table 2 22 describes these pipeline activities Figure 2 11 Pipeline Activities MIPS III IF1 I Fetch and Decode Branch Load Store ALU Cycle Phase PCycle PClock IF2 Φ2 Φ1 Φ2 Φ1 Φ2 Φ1 Φ2 Φ1 Φ2 Φ...

Page 86: ...nstruction cache array access ITC Instruction tag check RF Φ1 IDEC Instruction decode Φ2 RF Register operand fetch BAC Branch address calculation EX Φ1 EX Execution stage DVA Data virtual address calculation SA Store align Φ2 DCA Data cache address decode array access DTLB Data address translation DC Φ1 DLA Data cache load align DTC Data tag check DTD Data transfer to data cache WB Φ1 DCW Data cac...

Page 87: ...delay slot during MIPS III instruction mode Figure 2 12 Branch Delay In MIPS III Instruction Mode Branch delay slot Target Branch Branch delay PCycle IF RF EX DC WB IF RF EX DC WB IF RF EX DC WB 2 3 3 Load delay In the case of a load instruction 2 cycles are required for the DC stage for reading from the data cache and performing data alignment In this case the hardware automatically generates on ...

Page 88: ...e rs and rt fields and the register data is valid at the register file output At the same time bypass multiplexers select inputs from either the EX or DC stage output in addition to the register file output depending on the need for an operand bypass EX stage The ALU controls are set to do an A B operation The operands flow into the ALU inputs and the ALU operation is started The result of the ALU...

Page 89: ...he resulting value is the PC to which the program will eventually return This value is placed in the Link output latch of the Instruction Address unit EX stage The PC 8 value is moved from the Link output latch to the output latch of the EX stage DC stage The PC 8 value is moved from the output latch of the EX stage to the output latch of the DC stage WB stage Refer to the ADD instruction Note tha...

Page 90: ...o operands has equal values If they are equal the PC is set to PC target where target is the sign extended offset field If they are not equal the PC is set to PC 4 EX stage The next PC resulting from the branch comparison is valid at the beginning of Φ2 for instruction fetch DC stage This stage is a NOP for this instruction WB stage This stage is a NOP for this instruction Figure 2 15 BEQ Instruct...

Page 91: ...e if a less than condition is true If this condition is true a Trap exception occurs The value in the PC register is used as an exception vector value and from now on any instruction will be invalid DC stage No operation WB stage The value of the PC is loaded to EPC register if the less than condition was met in the EX stage The Cause register ExCode field and BD bit are updated appropriately as i...

Page 92: ...the sign extended offset field The result of the ALU operation that is latched into the ALU output latch in Φ1 represents the effective virtual address of the operand DVA DC stage The cache tag field is compared with the Page Frame Number PFN field of the TLB entry After passing through the load aligner aligned data is placed in the DC output latch during Φ2 WB stage During Φ1 the cache read data ...

Page 93: ...n the output latches during Φ1 The shift operations are latched in the output latches during Φ2 DC stage Refer to the LW instruction for a description of the cache access WB stage If there was a cache hit the content of the store data output latch is written into the data cache at the appropriate word location Note that all store instructions use the data cache for two consecutive PCycles If the f...

Page 94: ... cycle exception and interlock conditions are checked for all active instructions Because each exception or interlock condition corresponds to a particular pipeline stage a condition can be traced back to the particular instruction in the exception interlock stage as shown in Table 2 23 For instance an LDI Interlock is raised in the Register Fetch RF stage Tables 2 24 and 2 25 describe the pipelin...

Page 95: ...n Description IAErr Instruction Address Error exception NMI Non maskable Interrupt exception ITLB ITLB exception IPErr Instruction Parity Error exception INTr Interrupt exception IBE Instruction Bus Error exception SYSC System Call exception BP Breakpoint exception CUn Coprocessor Unusable exception RSVD Reserved Instruction exception Trap Trap exception OVF Integer overflow exception DAErr Data A...

Page 96: ...t PC is changed to the appropriate exception vector address and the exception bits of earlier pipeline stages are cleared This implementation allows all preceding instructions to complete execution and prevents all subsequent instructions from completing Thus the value in the EPC is sufficient to restart execution It also ensures that exceptions are taken in the order of execution an instruction t...

Page 97: ...ache line to write buffer 2 Get last word into cache and restart pipeline 3 If the cache line to be replaced is dirty the W bit is set the data is moved to the internal write buffer in the next cycle The write back data is returned to memory The last word in the data is returned to the cache at 3 and pipelining restarts Figure 2 22 CACHE Instruction Stall 1 CACHE instruction start IF RF EX DC WB W...

Page 98: ...n attempt to resolve the conflict NOPs will be inserted into the bubble in the pipeline Instructions killed by branch likely instructions ERET or exceptions will not cause slips Figure 2 23 Load Data Interlock 1 ADD A B Load B Load A Bypass Detect load interlock IF RF EX DC WB IF RF EX DC WB IF RF RF EX DC WB IF RF EX DC WB 1 Get the target data 2 2 Load Data Interlock is detected in the RF stage ...

Page 99: ...by load instruction is detected The pipeline begins running again one clock after Coprocessor 0 Interlock is detected in the EX stage and the pipeline slips in the RF stage A coprocessor interlock occurs when an MTC0 instruction for the Configuration or Status register is detected The pipeline begins running again one clock after 2 3 5 4 Bypassing In some cases data and conditions produced in the ...

Page 100: ...late the LL bit LL LLD SC SCD A 16 bit length MIPS16 instruction set is added in the VR4120A but the µPD98502 does not support MIPS16 mode The CP0 hazards of the VR4120A are equally or less stringent than those of other processors for details see APPENDIX B VR4120A COPROCESSOR 0 HAZARDS An instruction for debug has been added for the VR4120A However this instruction cannot be used for the VR4120A ...

Page 101: ...with the ASID field and saved in the EntryHi register If there is a virtual address match or hit in the TLB the physical page number is extracted from the TLB and concatenated with the offset to form the physical address If no match occurs TLB miss an exception is taken and software refills the TLB from the page table resident in memory The software writes to an entry selected using the Index regi...

Page 102: ... 2 40 As shown in Figure 2 25 the virtual address is extended with an address space identifier ASID which reduces the frequency of TLB flushing when switching contexts This 8 bit ASID is in the CP0 EntryHi register described later in this chapter The Global G bit is in the EntryLo0 and EntryLo1 registers described later in this section Figure 2 25 Virtual to Physical Address Translation Virtual ad...

Page 103: ...entry This match is referred to as a TLB hit If there is no match a TLB Mismatch exception is taken by the processor and software is allowed to refill the TLB from a page table of virtual physical addresses in memory If there is a virtual address match in the TLB the physical address is output from the TLB and concatenated with the offset which represents an address within the page frame space The...

Page 104: ...f Figure 2 26 is the virtual address space in which the page size is 256 Kbytes and the offset is 18 bits The 14 bits excluding the ASID field represents the VPN enabling selecting a page table of 16 K entries Figure 2 26 32 bit Mode Virtual Address Translation Bits 31 to 29 of the virtual address select the user supervisor or kernel address space 31 PFN Virtual address for 16 K 2 14 256 Kbyte pag...

Page 105: ... size is 256 Kbytes and the offset is 18 bits The 22 bits excluding the ASID field represents the VPN enabling selecting a page table of 4 M entries Figure 2 27 64 bit Mode Virtual Address Translation 31 PFN 32 bit physical address 10 24 30 8 0 0 9 10 39 40 61 62 63 64 71 ASID Offset TLB 18 24 22 8 0 17 18 39 40 61 62 63 64 71 ASID TLB 0 or 1 0 or 1 VPN Offset VPN Offset Bits 62 and 63 of the virt...

Page 106: ...beled User segment is available its size is 2 Gbyte 2 31 bytes in 32 bit mode useg 1 Tbyte 2 40 bytes in 64 bit mode xuseg Figure 2 28 User Mode Address Space 64 bit mode 32 bit mode Note 8000_0000H FFFF_FFFFH Address error 0000_0100_0000_ 0000H FFFF_FFFF_FFFF_FFFFH Address error xuseg useg 0000_0000H 7FFF_FFFFH 2 Gbytes with TLB mapping 0000_0000_ 0000_ 0000H 0000_00FF_FFFF_FFFFH 1 Tbyte with TLB...

Page 107: ...t Address Range Size Value KSU EXL ERL UX Name 32 bit A31 0 10 0 0 0 useg 0000_0000H to 7FFF_FFFFH 2 Gbytes 2 31 bytes 64 bit A 63 40 0 10 0 0 1 xuseg 0000_0000_0000_0000H to 0000_00FF_FFFF_FFFFH 1 Tbyte 2 40 bytes 1 useg 32 bit mode In User mode when UX 0 in the Status register and the most significant bit of the virtual address is 0 this virtual address space is labeled useg Any attempt to refer...

Page 108: ...xsuseg xsseg csseg BFFF_FFFFH 4000_00FF_FFFF_FFFFH 4000_0100_0000_0000H 0 5 Gbytes with TLB mapping Address error 2 Gbytes with TLB mapping Address error 0 5 Gbytes with TLB mapping Address error 1 Tbyte with TLB mapping Address error 1 Tbyte with TLB mapping FFFF_FFFF_E000_0000H FFFF_FFFF_DFFF_FFFFH FFFF_FFFF_C000_0000H FFFF_FFFF_BFFF_FFFFH 3FFF_FFFF_FFFF_FFFFH 4000_0000_0000_0000H 0000_0000_0000...

Page 109: ... is extended with the contents of the 8 bit ASID field to form a unique virtual address This mapped space begins at virtual address C000_0000H and runs through DFFF_FFFFH 3 xsuseg 64 bit supervisor mode user space When SX 1 in the Status register and bits 63 and 62 of the virtual address space are set to 00 the xsuseg virtual address space is selected it covers 1 Tbyte 2 40 bytes of the current us...

Page 110: ...it kernel space is selected The processor enters Kernel mode whenever an exception is detected and it remains in Kernel mode until an exception return ERET instruction is executed and results in ERL and or EXL 0 The ERET instruction restores the processor to the mode existing prior to the exception Kernel mode virtual address space is divided into regions differentiated by the high order bits of t...

Page 111: ...FFFFH C000_ 00FF_ 8000_ 0000H 0 5 Gbytes with TLB mapping 0 5 Gbytes with TLB mapping 0 5 Gbytes without TLB mapping uncacheable 0 5 Gbytes without TLB mapping cacheable Note 2 Address error With TLB mapping Without TLB mapping Address error 1 Tbyte with TLB mapping Address error 1 Tbyte with TLB mapping 4000_ 00FF_ FFFF_ FFFFH 4000_ 0100_ 0000_ 0000H C000_ 0000_ 0000_ 0000H BFFF_ FFFF_ FFFF_ FFFF...

Page 112: ...llows the Cache Error exception code to operate uncached using r0 as a base register 2 kseg0 32 bit kernel mode kernel space 0 When KX 0 in the Status register and the most significant three bits of the virtual address space are 100 the kseg0 virtual address space is selected it is the current 512 Mbyte 2 29 byte physical space References to kseg0 are not mapped through TLB the physical address se...

Page 113: ...B map 2 40 to 2 31 bytes A 63 62 11 A 63 31 1 1 ckseg0 FFFF_FFFF_8000_0000H to FFFF_FFFF_9FFF_FFFFH 0000_0000H to 1FFF_FFFFH 512 Mbytes 2 29 bytes A 63 62 11 A 63 31 1 1 ckseg1 FFFF_FFFF_A000_0000H to FFFF_FFFF_BFFF_FFFFH 0000_0000H to 1FFF_FFFFH 512 Mbytes 2 29 bytes A 63 62 11 A 63 31 1 1 cksseg FFFF_FFFF_C000_0000H to FFFF_FFFF_DFFF_FFFFH TLB map 512 Mbytes 2 29 bytes A 63 62 11 A 63 31 1 1 cks...

Page 114: ...ress space are 10 the virtual address space is called xkphys and selected as either cached or uncached If any of bits 58 to 32 of the address is 1 an attempt to access that address results in an address error Table 2 31 Cacheability and xkphys Address Space Bits 61 59 Cacheability Start Address 0 Cached 8000_0000_0000_0000H to 8000_0000_FFFF_FFFFH 1 Cached 8800_0000_0000_0000H to 8800_0000_FFFF_FF...

Page 115: ...or ckseg3 each having 512 Mbytes is selected as a compatible space according to the state of the bits 30 and 29 two low order bits of the address The KX bit of the Status register is 1 Bits 63 and 62 of the 64 bit virtual address are 11 Bits 61 to 31 of the virtual address are all 1 a ckseg0 This space is an unmapped region compatible with the 32 bit mode kseg0 space The K0 field of the Config reg...

Page 116: ...H 1000_2000H 1000_1FFFH 1000_3000H 1000_2FFFH 2000_0000H 1FFF_FFFFH FFFF_FFFFH 1F00_0000H 1EFF_FFFFH 1002_0000H 1000_FFFFH ATM Cell Processor 1001_0000H 1001_FFFFH 0000_0000H 4 KB 4 KB 4 KB 64 KB 16 MB 256 MB 1000_4000H 1000_3FFFH 4 KB Actual size of PROM Flash is max 8 MB Configuration 1 MB 1FCF_FFFFH 1FC0_0000H 2 MB 1FDF_FFFFH 1FC0_0000H Actual size of SDRAM is max 32 MB Configuration 04 MB 003F...

Page 117: ...ch of the memory management related registers Remark Each CP0 register has a unique number that identifies it this number is referred to as the register number Figure 2 32 CP0 Registers and TLB 31 0 Remark TLB Safe entries See Random register for TLB Wired boundary 127 255 EntryHi 10 EntryLo0 2 Index 0 Context 4 BadVAddr 8 Compare 11 Count 9 Random 1 EntryLo1 3 PageMask 5 Status 12 Cause 13 WatchL...

Page 118: ...1 64 95 75 74 73 72 71 VPN2 G 0 ASID 59 60 22 4 32 63 37 38 35 34 33 0 PFN C D V 0 1 3 1 1 27 28 22 4 0 31 5 6 3 2 1 0 PFN C D V 0 1 3 1 1 210 211 192 255 203 202 b 64 bit mode 0 MASK 0 190 189 8 2 1 2 22 29 45 8 11 128 191 139 138 137 136 135 R 0 VPN2 G 0 ASID 91 92 22 36 64 127 69 70 67 66 65 0 PFN C D V 0 1 3 1 1 27 28 22 36 0 63 5 6 3 2 1 0 PFN C D V 0 1 3 1 1 167 168 The format of the EntryHi...

Page 119: ... successful Index Specifies an index to a TLB entry that is a target of the TLBR or TLBWI instruction 0 RFU Write 0 in a write operation When this field is read 0 is read 2 4 5 2 Random register 1 The Random register is a read only register The low order 5 bits are used in referencing a TLB entry This register is decremented each time an instruction is executed The values that can be set in the re...

Page 120: ... 0 63 5 6 3 2 1 0 PFN C D V G 1 3 1 1 27 28 22 36 0 63 5 6 3 2 1 0 PFN C D V G 1 3 1 1 PFN Page frame number high order bits of the physical address C Specifies the TLB page attribute see Table 2 33 D Dirty If this bit is set to 1 the page is marked as dirty and therefore writeable This bit is actually a write protect bit that software can use to prevent alteration of data V Valid If this bit is s...

Page 121: ...his register as either a source or a destination Bits 18 to 11 that are targets of comparison are masked during address translation Figure 2 37 Page Mask Register 18 19 0 31 11 10 0 MASK 0 13 8 11 MASK Page comparison mask which determines the virtual page size for the corresponding entry 0 RFU Write 0 in a write operation When this field is read 0 is read Table 2 33 lists the mask pattern for eac...

Page 122: ...s can be overwritten by both instructions Figure 2 38 Positions Indicated by Wired Register 0 31 Value in the Wired register Range of Wired entries Range specified by the Random register The Wired register is set to 0 upon Cold Reset Writing this register also sets the Random register to the value of its upper bound see Section 2 4 5 2 Random register 1 Figure 2 39 shows the format of the Wired re...

Page 123: ...ts multiple processes share the TLB each process has a distinct mapping of otherwise identical virtual page numbers R Space type 00 user 01 supervisor 11 kernel Matches bits 63 and 62 of the virtual address Fill RFU Ignored on write When read returns zero 0 RFU Write 0 in a write operation When this field is read 0 is read 2 4 5 7 Processor revision identifier PRId register 15 The 32 bit read only...

Page 124: ...cy ratio of system interface clock VTCLK read only 0 to 6 RFU 7 Pipeline clock ACLK frequency 1 EP Transfer data pattern cache write back pattern setting 0 DD 1 Word 1 Cycle Others RFU Do not set AD Accelerate data mode 0 VR4000 Series compatible mode 1 RFU M16 MIPS16 ISA mode enable disable indication read only 0 MIPS16 instruction cannot be executed The µPD98502 sets 0 in this bit because it doe...

Page 125: ...ache error processing The Tag registers are written by the CACHE and MTC0 instructions Figures 2 44 and 2 45 show the format of these registers Figure 2 44 TagLo Register a When used with data cache 22 0 31 10 9 8 7 6 PTagLo b When used with instruction cache V D W 0 1 1 1 7 22 0 31 10 9 8 PTagLo V 0 1 9 PTagLo Specifies physical address bits 31 to 10 V Valid bit D Dirty bit However this bit is de...

Page 126: ...tual page number divided by two of each TLB entry In 64 bit mode the high order bits Note 2 of the 64 bit virtual address are compared to the contents of the VPN2 virtual page number divided by two of each TLB entry If a TLB entry matches the physical address and access control bits C D and V are retrieved from the matching TLB entry While the V bit of the entry must be set to 1 for a valid addres...

Page 127: ...match No 32 bit address Yes Yes TLB Mismatch TLB Invalid No No Yes Write Access main memory Access cache memory Exception Address error Address error Address error Exception TLB Modified XTLB Mismatch 2 4 5 12 TLB misses If there is no TLB entry that matches the virtual address a TLB Refill miss exception occurs Note If the access control bits D and V indicate that the access is not valid a TLB Mo...

Page 128: ...lation lookaside buffer read TLBR instruction loads the EntryHi EntryLo0 EntryLo1 and PageMask registers with the content of the TLB entry indicated by the content of the Index register 2 Translation lookaside buffer write index TLBWI The translation lookaside buffer write index TLBWI instruction writes the contents of the EntryHi EntryLo0 EntryLo1 and PageMask registers to the TLB entry indicated...

Page 129: ...s the address of the instruction that caused the exception or if the instruction was executing in a branch delay slot the address of the branch instruction immediately preceding the delay slot The VR4120A processor supports a Supervisor mode and high speed TLB refill for all address spaces The VR4120A CPU also provides the following functions Interrupt enable IE bit Operating mode User Supervisor ...

Page 130: ...Table 2 34 lists these registers along with their number each register has a unique identification number that is referred to as its register number The CP0 registers not listed in the table are used in memory management for details see Section 2 4 Memory Management System The exception handler examines the CP0 registers during exception processing to determine the cause of the exception and the s...

Page 131: ... register Figure 2 47 Context Register Format a 32 bit mode 4 21 7 0 24 24 25 31 4 3 PTEBase BadVPN2 0 b 64 bit mode 4 21 39 0 25 63 4 3 PTEBase BadVPN2 0 PTEBase The PTEBase field is a base address of the PTE entry table BadVPN2 This field holds the value VPN2 obtained by halving the virtual page number of the most recent virtual address for which translation failed 0 RFU Write 0 in a write opera...

Page 132: ...ddress for which an addressing error occurred or for which address translation failed 2 5 3 3 Count register 9 The read write Count register acts as a timer It is incremented in synchronization with the frequencies of MasterOut clock regardless of whether instructions are being executed retired or any forward progress is actually made through the pipeline This register is a free running type When ...

Page 133: ...egister the IP7 bit in the Cause register is set This causes an interrupt as soon as the interrupt is enabled Writing a value to the Compare register as a side effect clears the timer interrupt request For diagnostic purposes the Compare register is a read write register Normally this register should be only used for a write Figure 2 50 shows the format of the Compare register Figure 2 50 Compare ...

Page 134: ...Note never occur in the VR4120A CPU IM 1 0 Software interrupts Note Int 4 0 are internal signals of the CPU core For details about connection to the on chip peripheral units KX Enables 64 bit addressing in Kernel mode 0 32 bit 1 64 bit If this bit is set an XTLB Refill exception occurs if a TLB miss occurs in the Kernel mode address space In addition 64 bit operations are always valid in kernel mo...

Page 135: ...n all of the following conditions are true IE is set to 1 EXL is cleared to 0 ERL is cleared to 0 The appropriate bit of the IM is set to 1 2 Operating modes The following Status register bit settings are required for User Kernel and Supervisor modes The processor is in User mode when KSU 10 EXL 0 and ERL 0 The processor is in Supervisor mode when KSU 01 EXL 0 and ERL 0 The processor is in Kernel ...

Page 136: ... shows the fields of this register Table 2 35 describes the Cause register codes Figure 2 53 Cause Register Format 8 27 16 15 6 7 2 1 0 12 8 1 5 2 31 30 29 28 BD 0 CE 2 1 1 0 IP 7 0 0 ExcCode 0 BD Indicates whether the most recent exception occurred in the branch delay slot 1 In delay slot 0 Normal CE Indicates the coprocessor number in which a Coprocessor Unusable exception occurred This field wi...

Page 137: ...exception 9 Bp Breakpoint exception 10 RI Reserved Instruction exception 11 CpU Coprocessor Unusable exception 12 Ov Integer Overflow exception 13 Tr Trap exception 14 to 22 RFU 23 WATCH Watch exception 24 to 31 RFU The VR4120A CPU has eight interrupt request sources IP7 to IP0 For the detailed description of interrupts refer to Section 2 8 CPU Core Interrupts 1 IP7 This bit indicates whether ther...

Page 138: ... that caused the exception Virtual address of the immediately preceding branch or jump instruction when the instruction associated with the exception is in a branch delay slot and the BD bit in the Cause register is set to 1 The EXL bit in the Status register is set to 1 to keep the processor from overwriting the address of the exception causing instruction contained in the EPC register in the eve...

Page 139: ...he format of the WatchLo and WatchHi registers Figure 2 55 WatchLo Register Format 29 3 2 1 0 31 PAddr0 0 R W 1 1 1 WatchLo Register PAddr0 Specifies physical address bits 31 to 3 R If this bit is set to 1 an exception will occur when a load instruction is executed W If this bit is set to 1 an exception will occur when a store instruction is executed 0 RFU Write 0 in a write operation When this fi...

Page 140: ...f the PTE entry table R Space type 00 User 01 Supervisor 11 Kernel The setting of this field matches virtual address bits 63 and 62 BadVPN2 This field holds the value VPN2 obtained by halving the virtual page number of the most recent virtual address for which translation failed 0 RFU Write 0 in a write operation When this field is read 0 is read The 29 bit BadVPN2 field has bits 39 to 11 of the v...

Page 141: ...rrorEPC register contains the virtual address at which instruction processing can resume after servicing an error This address can be Virtual address of the instruction that caused the exception Virtual address of the immediately preceding branch or jump instruction when the instruction associated with the error exception is in a branch delay slot The contents of the ErrorEPC register do not chang...

Page 142: ...it to 1 so that the saved state is not lost upon the occurrence of another exception while the saved state is being restored Returning from an exception also resets the EXL bit to 0 For details see APPENDIX A MIPS III INSTRUCTION SET DETAILS 2 5 4 2 Exception vector address The Cold Reset Soft Reset and NMI exceptions are always branched to the following reset exception vector address This address...

Page 143: ...0_0000H BEV 0 BFC0_0200H BEV 1 0180H 1 TLB refill exception vector When BEV bit 0 the vector base address virtual for the TLB Refill exception is in kseg0 unmapped space 8000_0000H in 32 bit mode FFFF_FFFF_8000_0000H in 64 bit mode When BEV bit 1 the vector base address virtual for the TLB Refill exception is in kseg1 uncached unmapped space BFC0_0200H in 32 bit mode FFFF_FFFF_BFC0_0200H in 64 bit...

Page 144: ...ft Reset NMI Address Error instruction fetch TLB XTLB Refill instruction fetch TLB Invalid instruction fetch Bus Error instruction fetch System Call Breakpoint Coprocessor Unusable Reserved Instruction Trap Integer Overflow Address Error data access TLB XTLB Refill data access TLB Invalid data access TLB Modified data write Watch Bus Error data access Interrupt other than NMI Hereafter handling ex...

Page 145: ...It also means the processor can fetch and execute instructions while the caches and virtual memory are in an undefined state The contents of all registers in the CPU are undefined when this exception occurs except for the following register fields While the ERL of Status register is 0 the PC value at which an exception occurs is set to the ErrorEPC register TS and SR bits of the Status register ar...

Page 146: ...C0_0000H virtual in 64 bit mode This vector is located within unmapped and uncached address space so that the cache and TLB need not be initialized to process this exception The SR bit of the Status register is set to 1 to distinguish this exception from a Cold Reset exception When this exception occurs the contents of all registers are preserved except for the following registers The PC value at ...

Page 147: ...ed not be initialized to process an NMI exception The SR bit of the Status register is set to 1 to distinguish this exception from a Cold Reset exception Unlike Cold Reset and Soft Reset but like other exceptions NMI is taken only at instruction boundaries The states of the caches and memory system are preserved by this exception When this exception occurs the contents of all registers are preserv...

Page 148: ...address that was not located on a word boundary 2 Processing The common exception vector is used for this exception The AdEL or AdES code in the Cause register is set If this exception has been caused by an instruction reference or load operation AdEL is set If it has been caused by a store operation AdES is set When this exception occurs the BadVAddr register stores the virtual address that was n...

Page 149: ...e TLBL or TLBS code in the ExcCode field of the Cause register If this exception has been caused by an instruction reference or load operation TLBL is set If it has been caused by a store operation TLBS is set When this exception occurs the BadVAddr Context XContext and EntryHi registers hold the virtual address that failed address translation The EntryHi register also contains the ASID from which...

Page 150: ... contains the ASID from which the translation fault occurred The Random register normally stores a valid location in which to place the replacement TLB entry The contents of the EntryLo register are undefined The EPC register contains the address of the instruction that caused the exception However if this instruction is in a branch delay slot the EPC register contains the address of the preceding...

Page 151: ...ister contains the address of the instruction that caused the exception However if this instruction is in a branch delay slot the EPC register contains the address of the preceding jump or branch instruction and the BD bit of the Cause register is set to 1 c Servicing The kernel uses the failed virtual address or virtual page number to identify the corresponding access control bits The page identi...

Page 152: ... instruction that caused the exception However if this instruction is in a branch delay slot the EPC register contains the address of the preceding jump or branch instruction and the BD bit of the Cause register is set to 1 3 Servicing The physical address at which the fault occurred can be computed from information available in the System Control Coprocessor CP0 registers If the IBE code in the C...

Page 153: ...g of the branch instruction is required to resume execution 2 5 4 11 Breakpoint exception 1 Cause A Breakpoint exception occurs when an attempt is made to execute the BREAK instruction This exception is not maskable 2 Processing The common exception vector is used for this exception and the Bp code in the ExcCode field of the Cause register is set The EPC register contains the address of the instr...

Page 154: ...PC register contains the address of the preceding jump or branch instruction and the BD bit of the Cause register is set to 1 3 Servicing The coprocessor unit to which an attempted reference was made is identified by the CE bit of the Cause register One of the following processing is performed by the handler If the process is entitled access to the coprocessor the coprocessor is marked usable and ...

Page 155: ...in Kernel mode regardless of the value of the KX bit in the Status register This exception is not maskable 2 Processing The common exception vector is used for this exception and the RI code in the ExcCode field of the Cause register is set The EPC register contains the address of the instruction that caused the exception However if this instruction is in a branch delay slot the EPC register conta...

Page 156: ...X SIGFPE FPE_INTOVF_TRAP floating point exception integer overflow signal to the current process but the exception is usually fatal 2 5 4 15 Integer overflow exception 1 Cause An Integer Overflow exception occurs when an ADD ADDI SUB DADD DADDI or DSUB instruction results in a 2 s complement overflow This exception is not maskable 2 Processing The common exception vector is used for this exception...

Page 157: ... register is set to 1 and Watch exception is only maskable by setting the EXL bit in the Status register to 1 2 Processing The common exception vector is used for this exception and the Watch code in the ExcCode field of the Cause register is set The EPC register contains the address of the instruction that caused the exception However if this instruction is in a branch delay slot the EPC register...

Page 158: ...e of the bits can be simultaneously set or cleared if the interrupt request signal is asserted and then deasserted before this register is read The EPC register contains the address of the instruction that caused the exception However if this instruction is in a branch delay slot the EPC register contains the address of the preceding jump or branch instruction and the BD bit of the Cause register ...

Page 159: ...ontext VPN2 Entry Hi VPN2 ASID Set Cause register ExcCode CE To guideline to common exception handler Start Yes EXL 1 SR1 No No Yes Instruction in branch delay slot BEV PC FFFF FFFF BFC0 0200H 180H Unmapped uncached space M16 1 config20 PC FFFF FFFF 8000 0000H 180H Unmapped cacheable space No Instruction in delay slot BD bit 1 EPC PC 4 EPC EIM BD bit 0 EPC PC EPC EIM No Yes Yes BD bit 0 EPC PC Bad...

Page 160: ...upt exceptions is disabled by setting EXL 1 Other exceptions are avoided in the OS programs However the Cold Reset Soft Reset and NMI exceptions are enabled Execute MFC0 instruction Status bit setting KSU bit 00 EXL bit 0 IE bit 1 Execute MFC0 instruction X Context register EPC register Status register Cause register ERET Servicing by each exception routine Check the Cause register and jump to eac...

Page 161: ...VPN2 ASID X Context VPN2 Set Cause register ExcCode CE To guideline to TLB XTLB exception handler Start Yes EXL 1 SR1 No No Yes Instruction in branch delay slot BEV PC FFFF FFFF 8000 0000H vector offset Unmapped cacheable space PC FFFF FFFF BFC0 0200H vector offset Unmapped uncached space XTLB Refill Vector offset 080H TLB Refill Vector offset 000H TLB Refill Vector offset 180H No Yes XTLB Excepti...

Page 162: ...y each exception routine The execution of the ERET instruction is disabled in the branch delay slots for other jump instructions The processor does not execute an instruction in the branch delay slot for the ERET instruction PC EPC EXL 0 The physical address for a virtual address that is loaded into the Context register is loaded into the EntryLo register and written to the TLB As long as a data i...

Page 163: ...et exception routine Servicing by Soft Reset exception routine Servicing by NMI exception routine ERET BD bit 1 ErrorEPC PC 4 Random register 31 Wired register 0 Update Config register bit 31 28 Undef 27 23 22 6 Undef 5 0 Set Status register BEV bit 1 TS bit 0 SR bit 0 ERL bit 1 BD bit 0 ErrorEPC PC Cold Reset Exception Yes ERL 1 No No Yes Instruction in branch delay slot Yes NMI No 0 SR bit 1 Yes...

Page 164: ...ion in branch delay slot PC FFFF FFFF BFC0 0000H Software Servicing by Cold Reset exception routine Servicing by Soft Reset exception routine Servicing by NMI exception routine The processor provides no means of distinguishing between an NMI exception and Soft Reset exception so that this must be determined at the system level ERET Yes NMI No 0 SR bit 1 Instruction in delay slot BD bit 1 ErrorEPC ...

Page 165: ...lues of the other registers are undefined 2 6 2 Soft reset A Soft Reset initializes the CPU core without affecting the clocks in other words a Soft Reset is a logic reset In a Soft Reset the CPU core retains as much state information as possible all state information except for the following is retained The TS bit of the Status register is cleared to 0 The SR ERL and BEV bits of the Status registe...

Page 166: ...internal clocks in the CPU core except for PLL timer and interrupt clocks are stopped The VR4120A stops supplying TClock to peripheral units Accordingly during Suspend mode peripheral units can only be activated by a special interrupt unit DCD_B control etc While in this mode the register and cache contents are retained When the SUSPEND instruction completes the WB stage the VR4120A switches the D...

Page 167: ... 2 6 3 3 Reverse endian When the Status register s RE bit has been set the endian ordering is reversed to adopt the user software s perspective However the RE bit of the Status register must be set to 0 since the VR4120A supports the little endian order only 2 6 3 4 Bootstrap exception vector BEV The BEV bit is used to generate an exception during operation testing diagnostic testing of the cache ...

Page 168: ...ches At the same time each functional block takes longer to access than any block above it For instance it takes longer to access data in main memory than in the CPU on chip registers Figure 2 65 Logical Hierarchy of Memory VR4120A CPU core Register Register I cache D cache Cache Main memory Disc CD ROM tape etc Register Cache Memory Memory media Faster access time Increasing data capacity The VR4...

Page 169: ...e instruction data cache is 4 words 16 bytes For the cache tag see 2 7 2 1 Organization of the instruction cache I cache and 2 7 2 2 Organization of the data cache D cache 2 Cache sizes The instruction cache in the VR4120A Core is 16 Kbytes the data cache is 8 Kbytes 2 7 2 1 Organization of the instruction cache I cache Each line of I cache data although it is actually an instruction it is referre...

Page 170: ... 22 bit physical address a Valid bit a Dirty bit and a Write back bit The VR4120A Core D cache has the following characteristics write back direct mapped indexed with a virtual address checked with a physical tag organized with a 4 word 16 byte cache line Figure 2 68 shows the format of a 4 word 16 byte D cache line Figure 2 68 Data Cache Line Format W V D PTag Data Data 24 23 22 21 0 0 63 1 1 1 2...

Page 171: ...mporary data storage and they make the speedup of memory accesses transparent to the user In general the CPU core accesses cache resident instructions or data through the following procedure 1 The CPU core through the on chip cache controller attempts to access the next instruction or data in the appropriate cache 2 The cache controller checks to see if this instruction or data is present in the c...

Page 172: ... cache simultaneously 2 7 4 Cache states 1 Cache line The three terms below are used to describe the state of a cache line Dirty a cache line containing data that has changed since it was loaded from memory Clean a cache line that contains data that has not changed since it was loaded from memory Invalid a cache line that does not contain valid information must be marked invalid and cannot be used...

Page 173: ...tate transition Read 2 indicates a read operation from cache to the CPU core which induces no cache state transition Write 1 indicates a write operation from CPU core to cache inducing a cache state transition Write 2 indicates a write operation from CPU core to cache which induces no cache state transition Figure 2 70 Data Cache State Diagram CACHE op CACHE op Write 1 Write 1 CACHE op Write back ...

Page 174: ...e accesses Figure 2 72 Data Check Flow on Instruction Fetch Start Data Fetch END Tag Check Refill See Figure 2 85 Hit Miss Figure 2 73 Data Check Flow on Load Operations Start Write back and Refill see Data Load to Register END Hit V 0 invalid or W 0 clean Miss or Invalid V bit W bit V 1 valid and W 1 dirty Refill see Figure 2 85 Tag Check Figure 2 86 ...

Page 175: ... Flow on Store Operations Start Write back and Refill see Figure 2 86 END Hit V 0 invalid or W 0 clean Miss V bit W bit V 1 valid and W 1 dirty Refill see Figure 2 85 Tag Check Data Write to Data Cache Figure 2 75 Data Check Flow on Index_Invalidate Operations Start Valid bit Clear END ...

Page 176: ...Check Flow on Index_Writeback_Invalidate Operations 0 Clean Start Write back see Figure 2 84 END 0 Invalid W bit 1 dirty V bit Valid bit and W bit Clear 1 Valid Figure 2 77 Data Check Flow on Index_Load_Tag Operations Start END Tag Read to TagLo W bit Read to TagLo Data cache only ...

Page 177: ...gure 2 78 Data Check Flow on Index_Store_Tag Operations Start Tag Write from TagLo END Figure 2 79 Data Check Flow on Create_Dirty Operations Start Write back see Figure 2 84 END Miss or Invalid V bit W bit 1 dirty Tag Check V bit and W bit set Tag write Hit 0 Clean ...

Page 178: ...0 Data Check Flow on Hit_Invalidate Operations Start Valid bit Clear END Miss or Invalid Tag Check Hit Figure 2 81 Data Check Flow on Hit_Writeback_Invalidate Operations Start Write back see Figure 2 84 END Miss or Invalid W bit 1 dirty Tag Check Valid bit Clear Hit 0 Clean ...

Page 179: ...gure 2 82 Data Check Flow on Fill Operations Start Refill see Figure 2 85 END Figure 2 83 Data Check Flow on Hit_Writeback Operations Start Write back see Figure 2 84 END Miss or Invalid W bit 1 dirty Tag Check Hit 0 Clean W bit clear Data cache only Data cache only ...

Page 180: ...A 180 Preliminary User s Manual S15543EJ1V0UM Figure 2 84 Writeback Flow EOD Yes No Write back to memory Figure 2 85 Refill Flow EOD Yes No Write data to Cache Bus Error Exception Error bit Cache line Invalid OK Error ...

Page 181: ...hecked and data is transferred to the write buffer If an error is detected in the data field the write back is not terminated the erroneous data is still written out to main memory If an error is detected in the tag field the write back bus cycle is not issued The cache data may not be checked during CACHE operation 2 7 7 Manipulation of the caches by an external agent The VR4120A does not provide...

Page 182: ...ternal register 2 8 2 Ordinary interrupts Ordinary interrupts are acknowledged by asserting the Int 4 0 signals internal However Int4 never occurs in the VR4120A This interrupt request can be masked with the IM 6 2 IE and EXL fields of the Status register 2 8 3 Software interrupts generated in CPU core Software interrupts generated in the CPU core use bits 1 and 0 of the IP interrupt pending field...

Page 183: ...ORed with the current value of the Int4 to 0 signals and the result is directly readable as bits 14 to 10 of the Cause register IP1 and IP0 of the Cause register which are described in Section 2 5 Exception Processing are software interrupts There is no hardware mechanism for setting or clearing the software interrupts Figure 2 88 Hardware Interrupt Signals IP2 IP3 IP4 IP5 IP6 IP7 10 11 12 13 14 1...

Page 184: ...produce the CPU core interrupt signal The EXL bit in the Status register also enables these interrupts Figure 2 89 Masking of Interrupt Request Signals Timer interrupt IM0 IE Software interrutpts generated in CPU core Status register SR0 IM1 IM2 IM3 IM4 IM5 IM6 IM7 IP0 IP1 IP2 IP3 IP4 IP5 IP6 IP7 Ordinary interrupts Status register SR 15 8 Cause register 15 8 8 AND OR block AND block 1 1 CPU core ...

Page 185: ...rite command buffer Little endian or big endian byte order Don t support 8 words burst R W on SysAD bus 3 1 2 Memory interface 66 MHz or 100 MHz memory bus Up to 32 MB base memory range supports SDRAM Up to 8 MB write protectable boot memory range supports PROM flash On chip programmable SDRAM refresh controller 4 word 16 byte write data buffer 4 word 16 byte prefetch data buffer memory to CPU PRO...

Page 186: ...no parity bit generation Fully prioritized interrupt control 3 1 5 EEPROM 165 250 kHz clock rate Depend on CPU clock rate 66 100 MHz Support only 3 3 V EEPROM Recommended National Semiconductor s NM93C46 Support Micro Wire interface for Serial EEPROM Support auto load function for two addresses of MAC at system boot 3 1 6 Timer Two 32 bit loadable general purpose timers generating interrupt to CPU...

Page 187: ...ck diagram System Controller IBUS SysAD TIMER IBUS Master IF Flash PROM SDRAM RS 232C Flash IF SDRAM UART Register Memory Arbiter MIF HIF DSU SysAD IF SysAD IF Prefetch Buffer Write Buffer 64 word Read Buffer 64 word Write Buffer Write Buffer IBUS Slave IF Read Buffer MICRO WIRE Serial ROM ...

Page 188: ...AM IF UART REG M emory Arbiter M IF HIF DSU SysAD IF SysAD IF W P W R W R IBUS M aster IF IBUS S lav e IF IBUS SysAD M EM FLASH IF SDRAM IF M emory Arbiter M IF HIF SysAD IF SysAD IF W P W R W R IBUS IBUS M aster IF IBUS S lav e IF SysAD M EM FLASH IF SDRAM IF M emory Arbiter M IF HIF SysAD IF SysAD IF W P W R W R IBUS IBUS M aster IF IBUS S lav e IF M ICRO W IRE Serial ROM TIM ER RS 232C UART REG...

Page 189: ...UARTRBR R W H B UART Receiver Buffer Register DLAB 0 READ 1000_0080H UARTTHR W W H B UART Transmitter Holding Register DLAB 0 WRITE 1000_0080H UARTDLL R W W H B UART Divisor Latch LSB Register DLAB 1 1000_0084H UARTIER R W W H B UART Interrupt Enable Register DLAB 0 1000_0084H UARTDLM R W W H B UART Divisor Latch MSB Register DLAB 1 1000_0088H UARTIIR R W H B UART Interrupt ID Register READ 1000_0...

Page 190: ...emory Bus Control Register 1000_0128H 1000_0FFCH N A Reserved for future use Remarks 1 In the R W field W means writeable R means readable RC means read cleared means not accessible 2 All internal registers are 32 bit word aligned registers 3 The burst access to the internal register is prohibited If such burst access has been occurred IRERR bit in NSR is set and NMI will assert to CPU 4 Read acce...

Page 191: ...reset 0 do nothing 1 perform cold reset same as hardware system reset 3 2 3 S_GSR General Status Register The general status register S_GSR is a read only and 32 bit word aligned register S_GSR indicates the status of external pins of the µPD98502 S_GSR contains the following fields Bits Field R W Default Description 31 3 Reserved R 0 Hardwired to 0 2 MIPS16 R Reflects the status of external pin M...

Page 192: ...upt pending 15 5 Reserved RC 0 Hardwired to 0 4 WUIS RC 0 Wakeup interrupt 0 no wakeup request pending 1 some wakeup request pending 3 EXTIS RC 0 External interrupt 0 no external interrupt pending 1 external interrupt pending 2 UARTIS RC 0 UART interrupt 0 no UART interrupt pending 1 UART interrupt pending UART interruption is one of the following interruptions 1 UART receive data buffer full inte...

Page 193: ...is masked If it is set to 1 the corresponding bit is unmasked When the unmask bit is set and the bit in S_ISR is set system controller asserts interrupt signal to VR4120A S_IMR is initialized to 0 at reset and contains the following fields Bits Field R W Default Description 31 5 Reserved R W 0 Hardwired to 0 4 WUIM R W 0 Wakeup interrupt mask 1 unmask 0 mask 3 EXTIM R W 0 External interrupt mask 1...

Page 194: ...s has been performed 4 EXTNMI RC 0 External NMI 0 external NMI is not asserted 1 external NMI is asserted 3 MAERR RC 0 Memory address error Memory address error includes the memory access to the illegal memory space RFU space and out range of the SDRAM ROM space and the illegal memory access byte or half word ROM access or burst write access to the ROM 0 no such error 1 an address range error occu...

Page 195: ...ntains the following fields Bits Field R W Default Description 31 6 Reserved R W 0 Hardwired to 0 5 IRERRE R W 0 Illegal internal register access error enable 1 enable 0 disable 4 EXTNMIE R W 0 External NMI enable 1 enable 0 disable 3 MAERRE R W 0 Memory address error enable 1 enable 0 disable 2 ITERRE R W 0 IBUS timeout error enable 1 enable 0 disable 1 IBERRE R W 0 IBUS bus error enable 1 enable...

Page 196: ...eserved R W 0 Hardwired to 0 7 POM_OUT7 R W 0 Set output level for POM7 pin 0 deassert POM7 1 assert POM7 6 POM_OUT6 R W 0 Set output level for POM6 pin 0 deassert POM6 1 assert POM6 5 POM_OUT5 R W 0 Set output level for POM5 pin 0 deassert POM5 1 assert POM5 4 POM_OUT4 R W 0 Set output level for POM4 pin 0 deassert POM4 1 assert POM4 3 POM_OUT3 R W 0 Set output level for POM3 pin 0 deassert POM3 ...

Page 197: ...efault Description 31 6 Reserved W 0 Hardwired to 0 5 PCIWR W 0 Warm reset request for PCI Controller 0 do nothing 1 perform warm reset 4 UARTWR W 0 Warm reset request for UART 0 do nothing 1 perform warm reset 3 MAC2WR W 0 Warm reset request for Ethernet Controller 2 0 do nothing 1 perform warm reset 2 ATMWR W 0 Warm reset request for ATM Cell Processor 0 do nothing 1 perform warm reset 1 MACWR W...

Page 198: ... 0 Indicates warm reset status from UART 0 UART is busy to perform the warm reset 1 warm reset has been done UART is ready 3 MAC2WRST R 0 Indicates warm reset status from Ethernet Controller 2 0 Ethernet Controller 2 is busy to perform the warm reset 1 warm reset has been done MAC Ethernet Controller 2 is ready 2 ATMWRST R 0 Indicates warm reset status from ATM Cell Processor 0 ATM Cell Processor ...

Page 199: ...e system clock for Ethernet Controller 2 18 ATMSTOP R W 0 Suspend request for ATM Cell Processor 0 enable system clock for ATM Cell Processor 1 disable system clock for ATM Cell Processor 17 MACSTOP R W 0 Suspend request for Ethernet Controller 1 0 enable system clock for Ethernet Controller 1 1 disable system clock for Ethernet Controller 1 16 USBSTOP R W 0 Suspend request for USB Controller 0 en...

Page 200: ...g 1 wakeup request is pending 9 MACWKUP R 0 Indicates the wakeup request form Ethernet Controller 1 0 no wakeup request is pending 1 wakeup request is pending 8 USBWKUP R 0 Indicates the wakeup request from USB Controller 0 no wakeup request is pending 1 wakeup request is pending 7 6 Reserved R 0 Hardwired to 0 5 PCIIDLE R 0 Indicates the idle status in PCI Controller 0 not in idle state It means ...

Page 201: ... determine the transaction type Ten address ranges can be decoded One range for external boot PROM or flash One range for external SDRAM One range for system controller s internal configuration registers Boot PROM flash is mapped according to its size System controller s internal registers are fixed at base address 1000_0000H to allow the VR4120A to access them during boot before they have been co...

Page 202: ...an Translation Table in Endian Converter CPU access type BIG ENDCEN Before translation SysAD 1 0 After translation SysAD 1 0 Notes 2 word 4 word 1 1 00 00 Valid 01 01 Invalid 10 10 Invalid Block 11 11 Invalid 00 11 Valid 01 10 Valid 10 01 Valid Single 1 byte 1 1 11 00 Valid 00 10 Valid 01 11 Invalid 10 00 Valid Single 2 byte 1 1 11 01 Invalid 00 01 Valid 01 00 Valid 10 11 Invalid Single 3 byte 1 1...

Page 203: ...pend UART source clock R Internal UART register 2 Invalid R Internal UART register 4 Invalid W IBUS target 1 23 W IBUS target 2 23 W IBUS target 4 23 2 1 2 W Internal write command FIFO 1 6 1 wait W Internal write command FIFO 2 6 1 W Internal write command FIFO 4 6 1 1 1 W Internal register except UART 1 7 W Internal register except UART 2 Invalid W Internal register except UART 4 Invalid W Inter...

Page 204: ...3 clocks Endian converter on IBUS slave I F Don t supports 8 word burst R W from SysAD bus 3 4 2 Memory regions The controller connects to memory directly and manages the addresses data and control signals for the following address ranges One boot PROM flash range programmable One system memory range programmable The following types of memory modules as an example but not limited to can be used Fl...

Page 205: ...AS_B CS_B CAS_B WE_B DQM 3 0 CKE CLK 1 0 DQ 31 0 A 13 0 ADDRESS DATA SMA 20 0 SMD 31 0 SMA 20 0 SMD 31 0 Table 3 3 External Pin Mapping External Pin Access to ROM Access to SDRAM Name Bits SMA 13 0 A 13 0 A 13 0 17 14 A 17 14 SDQM 3 0 20 18 A 20 18 SMD 31 0 D 31 0 DQ 31 0 SDCS_B SDCS_B SDRAS_B SDRAS_B SDCAS_B SDCAS_B SDWE_B SDWE_B SDWE_B SDCKE 1 0 SDCKE 1 0 SDCLK 1 0 SDCLK 1 0 SRMCS_B SRMCS_B SRMO...

Page 206: ...formance is calculated by counting the rising edge for CPU clock where the read command is issued by the CPU Because the CPU issues write data with no wait states once the write command is issued the numbers in the table represent the rate at which data is written to memory The sum of the numbers represents the number of cycles between when the write operation was issued and when the next CPU memo...

Page 207: ...e the value on the FSM field after setting a value into the FSM field 3 4 6 RMATR ROM Access Timing Register The ROM access timing register RMATR is a read write and 32 bit word aligned register RMATR is used to set the access time in the PROM flash interface RMATR is initialized to 0 at reset and contains the following fields Bits Field R W Default Description 31 3 Reserved R W 0 Hardwired to 0 F...

Page 208: ..._B SDW E_B H Valid Read Address T0 T1 T2 T3 T4 T0 Hi Z Read Data T1 T2 T3 T4 T5 T6 FLASH M em ory W rite Cycle H Valid W rite Address W rite Data FAT 6 ROM Burst Read Cycle FAT 4 H Valid Read Address T0 T1 T2 T3 T4 Hi Z T5 T6 T7 T8 T9 T10 T11 T12 FAT 4 Valid Read Address Read Data Read Data invalid SM A SDC LK SM D SR M C S_B SR M OE_B SDW E_B ...

Page 209: ...erved 01 2 clocks 10 3 clocks 11 4 clocks default 66 MHz 30 3 ns 66 MHz 45 5 ns 66 MHz 60 6 ns 100 MHz 20 ns 100 MHz 30 ns 100 MHz 40 ns 7 Reserved R W 0 Hardwired to 0 6 4 LTMD R W 011 SDRAM CAS latency 000 reserved 001 reserved 010 2 011 3 default 1xx reserved 3 Reserved R W 0 Hardwired to 0 2 0 BL R W 000 SDRAM burst length 000 1 default 001 reserved 010 reserved 011 reserved 1xx reserved Remar...

Page 210: ...00 4 MBytes default 01 8 MBytes 10 16 MBytes 11 32 MBytes 003F_FFFFH 0000_0000H 007F_FFFFH 0000_0000H 00FF_FFFFH 0000_0000H 01FF_FFFFH 0000_0000H 7 BTM R W 0 Number of bank 0 1 or 2 banks default 1 3 or 4 banks 6 4 RAB R W 000 Total number of SDRAM address bits RAS CAS except bank select pins 000 17 bits default 001 18 bits 010 19 bits 011 20 bits 100 21 bits 101 22 bits 110 reserved 111 reserved ...

Page 211: ...erved 66 MHz 30 3 ns 66 MHz 45 5 ns 66 MHz 60 6 ns 100 MHz 20 ns 100 MHz 30 ns 100 MHz 40 ns Remark Don t set the reserved value to each field in this register 3 4 10 SDRMR SDRAM Refresh Mode Register The SDRAM refresh mode register SDRMR is a read write and 32 bit word aligned register SDRMR is used to initialize the SDRAM refresh controller SDRMR is initialized to 200H at reset and contains the ...

Page 212: ...to select priority for either VR4120A or IBUS to access memory The VR4120A can assign higher priority to CPU request for memory than IBUS request or assign equal priority to VR4120A and IBUS request for memory MBCR is initialized to 0 at reset and contains the following fields Bits Field R W Default Description 31 1 Reserved R W 0 Hardwired to 0 0 BPR R W 0 Priority for memory access 0 SysAD CPU R...

Page 213: ...hrough 1FFF_FFFFH When writes are performed to the ROM flash memory space the controller asserts SDWE_B in conjunction with SRMCS_B When reads are performed the controller asserts SRMOE_B in conjunction with SRMCS_B If the VR4120A attempts to access boot ROM addresses outside the defined size of the flash ROM the controller returns 0 with the data error bit set on SysCMD 0 In addition the NMI stat...

Page 214: ...D 8080_8080H D AAAA_AAAAH D 5555_5555H D 3030_3030H Remark A memory write address D memory write data PA address of flash location to be programmed PD data to be programmed at location PA EA block address of flash location to be erased In case of Flash memory programming please consider following system factors 1 Read cycle can t interrupt these write commands Therefore it is impossible for the µP...

Page 215: ...MOE_B SDW E_B SRMCS_B Example 8 MB PROM SMA 20 0 SMD 31 0 µ PD98502 System Controller µ PD98502 System Controller FLASH ROM Configuration SMD 31 0 SRMOE_B SDW E_B SRMCS_B Example 4 MB FLASH SMD 31 0 1 M x 8 bit x 4 FLASH A 19 0 D 7 0 W E_B CS_B OE_B SMA 19 0 D 7 0 A 20 0 OE_B CS_B 2 M x 8 bit x 4 PROM SMA 20 0 SMA 20 0 ...

Page 216: ...ganization bank x word x bit Quantity 4 MB 12 0 2 x 0 5 M x 16 2 8 MB 12 0 4 x 0 5 M x 32 1 16 MB 13 0 4 x 1 0 M x 16 2 32 MB 13 0 4 x 2 0 M x 16 2 3 4 14 3 SDRAM burst type and banks The terms interleaved and bank have multiple meanings in the context of memory design using SDRAM chips The meanings are Banks applied to memory modules and SDRAM chips in different ways The banks referenced with res...

Page 217: ... Order for Instruction Cache Line Fill SDRAM Chip Burst Type Start Column Address A1 A0 Sequential Interleaved 00 0 1 2 3 Not supported 01 1 2 3 0 Not supported 10 2 3 0 1 Not supported 11 3 0 1 2 Not supported Remark The memory controller does not support the interleaved burst type for SDRAMs It assumes that all SDRAMs are initialized to the sequential burst type using a burst length of 4 words 3...

Page 218: ... 0 SMD 31 0 A 10 0 DQ 15 0 RAS_B CS_B SDRAS_B SDWE_B SDCLK 1 0 SDQM 3 0 SDCS_B CAS_B DQM 3 0 CLK WE_B SMD 15 0 CKE SDCKE 1 0 SMA 10 0 SDCLK 0 SDCKE 0 SDQM 3 0 4 M x 16 SDRAM SMA 13 0 SMD 31 0 A 13 0 DQ 15 0 RAS_B CS_B SDCAS_B SDRAS_B SDWE_B SDCLK 1 0 SDQM 0 2 SDCS_B CAS_B LDQM UDQM CLK WE_B SMD 31 16 SMD 15 0 CKE SDCKE 1 0 SMA 13 0 SDCLK 0 SDCKE 0 SDQM 0 SDQM 1 SDCLK 1 SDCKE 1 SDQM 2 SDQM 3 SMA 13...

Page 219: ...mpts a read from an address immediately following sequential to the address of the last read cycle the first 4 words will supplied from the prefetch FIFO The memory controller compares the current SysAD address with the previous address to determine the sequential nature of the access Prefetched words are retained in the prefetch FIFO if accesses to resources other than system memory are performed...

Page 220: ...s 3 Performs eight sequential auto refreshes CBR 3 4 1 2 Memory initialization sequence using software The SDRAM must be initialized by the software using following sequence after power on initialization 1 Program the SDRAM type selection register SDTSR 2 Program the SDRAM mode register SDMDR 3 Wait for 20 µs 4 Program the DRAM refresh counter register At this point memory is ready to use All othe...

Page 221: ...HSWP bit on S_GMR is enabler for endian converter that is located on space between SysAD interface and IBUS master interface so this works only IBUS target area This converter is effective at the case of address swap mode only This converter performs following data operations Table 3 11 Endian Translation Table for the data swap mode IBUS master HSWP on GMR Data Size offset address 1 0 Note Before...

Page 222: ... is located on space between memory interface and IBUS slave interface so this works only memory access via IBUS slave I F This converter is effective at the case of address swap mode only This converter performs following data operations Table 3 12 Endian Translation Table for the data swap mode IBUS slave MSWP on GMR Before Translation input data 31 0 in Data Phase After Translation output data ...

Page 223: ...IBUS Timeout Timer Set Register This register sets the cycle for Deadman s Switch functions The Deadman s Switch cycle can be set in 1 clock increments in a range from 1 to 232 1 clock The DSUCLRR s DSWCLR bit must be set by means of software within the specified cycle time ITSETR is a 32 bit word aligned register Default is 8000_0000H Bits Field R W Default Description 31 0 ITTIME R W 8000_ 0000H...

Page 224: ...e from 1 to 2 32 1 clock The DSUCLRR s DSWCLR bit must be set by means of software within the specified cycle time DSUSETR is a 32 bit word aligned register Default is 8000_0000H Bits Field R W Default Description 31 0 DEDTIM R W 8000_ 0000H Deadman s Switch cycle setting DSU cycle DEDTIME value system clock period 100 MHz 10 ns 66 MHz 15 ns example DEDTIM 05F5_E100H 100 MHz or 03F9_40AAH 66 MHz D...

Page 225: ...CRTTIM 05F5_E100H 100 MHz or 03F9_40AAH 66 MHz 1 sec CRTTIM 0BEB_C200H 100 MHz or 07F2_8154H 66 MHz 2 sec CRTTIM 11E1_A300H 100 MHz or 0BEB_C200H 66 MHz 3 sec 3 6 6 DSU register setting flow The DSU register setting flow is described below 1 Set the DSU s count up value from 1 to 231 1 The CPU will be reset if it does not clear 1 is not written to DSUCLRR the timer within this period 2 Enable the ...

Page 226: ...resses or Data byte order in the word are not swapped inside the device for accesses from a little endian VR4120A to all local registers and memory when BIG signal is Low Data addresses are swapped inside the device for accesses from a big endian VR4120A to all local registers and memory when BIG signal and ENDCEN signal are High Data byte order in the word are swapped inside the device for access...

Page 227: ...no byte swapping takes place In this case data item bit order is retained between the two endian modes The code that sequentially accesses the half word data array would be identical regardless of the endian mode of its VR4120A The code would be endian independent Figure 3 2 Half word Data Array Example A HW3 Halfword Data Array Big Endian Data extraction using sequential halfword access B C D E F...

Page 228: ...f word data array causes the same problem Such problems also arise when a half word access is made into a 32 bit register whereas a word access into a 32 bit register creates no problem Figure 3 3 Word Data Array Example Word Data Array Big Endian Data extraction using sequential halfword access W1 W0 LSHW MSHW Little Endian MSHW LSHW A B C D E F G H I J K L M N O P A B C D E F G H I J K L M N O P...

Page 229: ...pacity is 50 Mbps 25 Mbps for downstream and 25 Mbps for upstream Supports ATM Adaptation Layers AAL AAL 0 raw cells AAL 2 and AAL 5 are supported Supports Service Classes CBR VBR and UBR Number of VC s Maximum of 64 VC s will be supported Scheduling Cell rate shaping will be performed in one cell time granularity on per VC basis Supports OAM function Supports switching function ATM Cell Processor...

Page 230: ...TM cell processor It consists of a 32 bit MCU Peripherals Interrupt Controller Cell Timer Scheduling Table and Rx Lookup Table DMA controllers a Work RAM and SAR Registers 4 1 2 1 RISC core This block is RISC micro controller Its features are as follows High performance 32 bit RISC micro controller 76 MIPS 66 MHz 32 x 32 bit General Purpose Registers 32 bit ALU 32 bit Shifter 16 x 16 Multiply Adde...

Page 231: ...hrough 30 can be selected by setting command register The first word of cell header and the last two words of payload can be read in Big Endian byte in order to insert extract some special bit fields To avoid Head of line Blocking later cells can pass earlier cells if their destination PHY devices are not ready In Rx side it filters out idle cells and unassigned cells when it detects their pre det...

Page 232: ... Processor supports AAL 5 SAR sublayer and ATM layer functions This block provides LLC encapsulation Figure 4 2 AAL 5 Sublayer and ATM Layer CPCS PDU recovery CPCS UU field notification CPI field notification packet length check notification CRC check CPCS PDU construction CPCS PDU generation padding addition CPCS UU field addition CPI field addition packet length calcuration insertion CRC 32 calc...

Page 233: ... adjust the length of the resulting packet to a multiple of 48 bytes ATM Cell Processor writes zeros to all its bits b CPCS UU field Used to transfer user information The value set in the packet descriptor by the host is written in this field c CPI field The use of this field has yet to be finalized According to the current specifications all its bits must be set to zeros ATM Cell Processor howeve...

Page 234: ...cell payload is user data or management data It also contains congestion information PTI Usage 000 user data cell no congestion SDU type 0 001 user data cell no congestion SDU type 1 010 user data cell congestion occurred SDU type 0 011 user data cell congestion occurred SDU type 1 100 OAM F5 flow cell 101 OAM F5 flow cell 110 reserved for future use 111 reserved for future use Here SDU type 0 all...

Page 235: ...pport non AAL 5 traffic For the VC which is set as the raw cell mode ATM Cell Processor doesn t execute any AAL 5 dependent operation such as calculating CRC 32 and adding trailers In receiving mode the ATM Cell Processor stores received cells with header and 11 bytes indication in SDRAM ATM Cell Processor has a CRC 10 insertion and verification function for non AAL 5 traffic In the case that CRC ...

Page 236: ...ry 4 MB max xx00_0000H xx0F_FFFFH xx40_0000H xx80_0000H xx80_FFFFH xxFF_FFFFH xxFF_F000H Peripheral xxFF_E3FFH xxFF_E000H Internal Data RAM 1 KB RISC Core Memory Space 1001_FFFFH 1001_0000H VR4120A RISC Processor Memory Space W ork RAM Register Space The configuration is shown as Figure 4 6 It contains instruction space shared memory space work RAM internal memory space and peripheral space VR4120...

Page 237: ...nd some other special blocks will be mapped Scheduling table VC lookup table and Cell Timer will be mapped in peripheral space as well 4 2 2 Shared memory ATM Cell Processor can access 4 MB or less of the memory space that is used as cell buffer and packet buffer It is also used for instruction memory This memory will be implemented off the chip RISC Core in the ATM Cell Processor can access this ...

Page 238: ...mand Register 1001_F024H N A Reserved for future use 1001_F028H A_CER R W W Command Extension Register 1001_F02CH 1001_F04CH N A Reserved for future use 1001_F050H A_MSA0 R W W Mailbox0 Start Address Register 1001_F054H A_MSA1 R W W Mailbox1 Start Address Register 1001_F058H A_MSA2 R W W Mailbox2 Start Address Register 1001_F05CH A_MSA3 R W W Mailbox3 Start Address Register 1001_F060H A_MBA0 R W W...

Page 239: ...d If such burst access has been occurred IRERR bit in NSR is set and NMI will assert to CPU 4 Read access to the reserved area will set the CBERR bit in the NSR register and the dummy read response data with the data error bit set on SysCMD 0 is returned 5 Write access to the reserved area will set the CBERR bit in the NSR register and the write data is lost 6 In the Access filed W means that word...

Page 240: ...it in A_IMR Interrupt Mask Register is set to a 0 and the interruption is not masked an interruption is issued to VR4120A The bit in A_GSR is able to be read cleared When the same type of events occurs before the bit has been read the bit will be set again Initial value is all zero Bits Field R W Default Description 31 PI RC 0 0 PHY layer device interruption has not occurred 1 PHY layer device int...

Page 241: ... Field R W Default Description 31 PI R W 0 Mask bit for PHY layer device interruption 0 mask 1 unmask 30 RQA R W 0 Mask bit for Receive Queue Alert 0 mask 1 unmask 29 RQU R W 0 Mask bit for Receive Queue underflow 0 mask 1 unmask 28 24 Reserved R W 0 Reserved for future use Write 0 s 23 SQO R W 0 Mask bit for Scheduling Queue overflow 0 mask 1 unmask 22 Reserved R W 0 Reserved for future use Write...

Page 242: ...ed for future use 7 0 A_RQA 7 0 R 0 0 pool 7 0 has more or equal remaining batches than ALERT LEVEL 1 pool 7 0 has less remaining batches than ALERT LEVEL 4 4 7 A_VER Version Register A_VER shows version number of ATM Cell Processor block Initial value is 0000_0200H Bits Field R W Default Description 31 16 Reserved R 0 Reserved for future use 15 8 MAJOR R 02H Major revision 7 0 MINOR R 00H Minor r...

Page 243: ...Mailbox1 and Transmit mailbox Mailbox2 and Mailbox3 respectively Initial value is all zero Bits Field R W Default Description 31 0 A_MBA0 R W 0 Bottom address of Mailbox0 Bits Field R W Default Description 31 0 A_MBA1 R W 0 Bottom address of Mailbox1 Bits Field R W Default Description 31 0 A_MBA2 R W 0 Bottom address of Mailbox2 Bits Field R W Default Description 31 0 A_MBA3 R W 0 Bottom address o...

Page 244: ...s Field R W Default Description 31 0 A_RCC R 0 Number of valid received cells 4 4 15 A_TCC Valid Transmitted Cell Counter A_TCC counts the number of valid transmitted cells It is a 32 bit counter Overflow of this counter does NOT cause any interruption Initial value is zero Bits Field R W Default Description 31 0 A_TCC R 0 Number of valid transmitted cells 4 4 16 A_RUEC Receive Unprovisioned VPI V...

Page 245: ...sor 4 4 20 A_IBBAR IBUS Base Address Register A_IBBAR contains the base address for the access thorough IBUS to outside RISC Core space is addressed using 24 bit address while VR4120A RISC Processor space is addressed using 32 bit address Therefore the extension of address is necessary when the access from the inside of this block to the outside is requested Initial value is zero Bits Field R W De...

Page 246: ...in 16 bit transfer mode EM bit can change the data alignment as shown below VR4120A 0 31 a b c d 0 a b 15 PHY EM 1 VR4120A 0 31 a b c d 0 a b 15 PHY EM 0 Initial value of A_UMCMD is zero Bits Field R W Default Description 31 Reserved R W 0 Reserved for future use Write 0 s 30 BM R W 0 0 8 bit transfer mode 1 16 bit transfer mode 29 EM R W 0 0 data let straight 1 data let cross 28 3 Reserved R W 0 ...

Page 247: ...or It consists of a packet descriptor some buffer directories and data buffers A Rx buffer structure and a Tx buffer structure are similar so that reconstructing buffer structure is not needed when sending out a received packet Figure 4 8 Tx Packet Tx buffer desc Tx buffer desc Tx buffer desc Data Buffer Data Buffer Tx buffer desc L 1 Data Buffer Data Buffer Link pointer Tx buffer desc Null pointe...

Page 248: ...er desciptor 1 Tx buffer desciptor 2 Tx buffer desciptor 3 Tx buffer desciptor 4 Tx buffer desciptor N Tx link pointer Tx buffer descriptor 31 0 16 15 Buffer Address L Size Tx packet descriptor 31 0 16 15 Tx buffer directory Address Attribute CPCS UU CPI DL 0 0 DL Figure 4 9 shows Tx buffer elements Each element consists of a couple of 32 bit words in sequential address Detail is given in followin...

Page 249: ...etail will be given in Operation chapter Table 4 1 List of Tx Packet Attribute Field Description ENC It contains Encapsulation bits to specify Encapsulation modes CLPM It contains CLP bit to be set in Tx cell header PTI It contains PTI bit to be set in Tx cell header GFC It contains GFC bit to be set in Tx cell header IM It disables interruption and indication when Tx is completed C10 It enables g...

Page 250: ...own as Figure 4 11 L bit bit 31 is fixed to zero If there is no buffer directory to be linked directory address of link pointer must be zero as a null pointer Figure 4 11 Tx Buffer Descriptor Link Pointer Tx buffer directory Address Tx link pointer Attribute Tx buffer descriptor 31 30 0 16 15 Attribute Size L 0 Buffer Address 31 0 DL 31 30 0 DL 4 5 1 4 Data buffer Data buffer contains actual packe...

Page 251: ...Buffer Rx buffer directory Rx pool0 descriptor Rx pool1 descriptor Rx pool7 descriptor Data Buffer Data Buffer Data Buffer Size 1 to 64 kBytes Rx buffer desc Rx buffer desc Rx buffer desc Rx buffer desc Rx buffer desc Rx link pointer Rx buffer desc Rx buffer desc Rx buffer desc Null pointer Rx buffer desc Rx buffer desc Rx buffer desc Rx link pointer Rx buffer desc Null pointer Rx buffer dir Rx bu...

Page 252: ... 31 0 31 0 Rx buffer desciptor 0 Rx buffer desciptor 1 Rx buffer desciptor 2 Rx buffer desciptor 3 Rx buffer desciptor 4 Rx buffer desciptor 5 Rx link pointer Rx buffer descriptor 31 0 16 15 Buffer Address Attribute Size Rx pool descriptor 31 0 16 15 Rx buffer directory Address Attribute Figure 4 13 shows Rx buffer elements Each element consists of a couple of 32 bit words of sequential address De...

Page 253: ...ntains address of the first buffer directory in the pool 4 5 2 2 Rx buffer directory Rx buffer directory contains some buffer descriptors up to 255 and a link pointer Number of buffer descriptors in each directory in one pool is identical Number can vary in different pools Address of buffer directory is word aligned The end of buffer directory must be a link pointer Buffer descriptor must be read ...

Page 254: ...r Link Pointer Rx link pointer Rx buffer descriptor 31 30 0 16 15 Attribute Size L Buffer Address 31 0 1 31 30 0 16 15 Reserved 0 Directory Address 31 0 0 4 5 2 4 Rx data buffer Rx Data buffer contains actual received cell data Size of a buffer can vary from 1 byte to 64 kbytes Its address is byte aligned ...

Page 255: ...g initialization Instruction memory space will be placed in the system memory space to achieve faster instruction fetch VR4120A has to transfer RISC Core F W to the assigned SDRAM area as well as its own S W in its initialization as shown in Figure 4 16 After transferring F W it sets base address of RISC Core F W in A_INBAR At the same time base address of shared memory space has to be set in A_IB...

Page 256: ...placement Lower 8 KB of Instruction space in RISC Core will be copied on Instruction RAM because it will contain interruption vector table The other part of the space is accessed through 8 KB of Instruction cache In case that the total size of F W is smaller than 16 KB RISC Core can run fastest because once all necessary instruction code is copied in no cache miss will occur Figure 4 17 Instructio...

Page 257: ...the command register and checks if busy bit is 0 before issues new command 1 Commands which ATM Cell Processor returns command indication When ATM Cell Processor receives Open_Channel Close_Channel Open_IP_Channel Close_IP_Channel Tx_Ready and Add_Buffers command it writes command indication in command register VR4120A RISC Processor has to read command indication after issuing these commands Howe...

Page 258: ...ng 2 e 1 m 512 nz cells sec Re served nz e m 15 14 13 9 8 0 4 7 2 Open_Channel command This command is used to open a new channel to be used for a send or receive operation When the channel is opened ATM Cell Processor reserves the area for the VC table in Work RAM and returns the VC Number as an indication The indication that ATM Cell Processor returns for this command is of the following format ...

Page 259: ... 0 0 1 R T 0 VC Number 0 31 30 29 28 27 26 25 24 18 17 6 5 0 Close_Channel command indication CMR Undefined E Undefined VC Number 0 31 25 24 23 18 17 6 5 0 Close_Channel command R T Indicates whether the channel to be closed is a send or a receive channel 1 Receive channel 0 Transmit channel VC Number VC Number of the channel that VR4120A intends to close Close_Channel command indication E Error b...

Page 260: ...he following format Figure 4 21 Tx_Ready Command and Indication Tx_Ready command CMR 0 1 1 0 0 1 0 VC Number 0 31 30 29 28 27 26 25 24 18 17 6 5 0 CER Packet Descriptor Address 31 0 Tx_Ready command indication CMR 0 1 1 0 0 1 E 0 VC Number 0 31 30 29 28 27 26 25 24 23 18 17 6 5 0 Tx_Ready command VC Number The VC number of the channel which VR4120A intends to start transmission Packet descriptor a...

Page 261: ...29 28 27 26 25 24 23 21 20 16 15 0 Add_Buffers command Pool No Number of the pool to which buffer directories are to be added Since ATM Cell Processor supports only 8 pools 0 to 7 Bit 19 and 20 should be set to a 0 Number of Buffer Directories Number of new buffer directories to be added Buffer Directory Pointer Start address of the first buffer directory in the list of new buffer directories to b...

Page 262: ...address is used as is The low order two bits of the address must be 0 that is the address must be a word address 4 8 Operations In this section functional specifications mainly SAR function is described 4 8 1 Work RAM usage The size of the Work RAM is 16 Kbytes This memory is used for following five purposes 1 Temporary data The data which are exchanged with SDRAM using DMA The data stored in this...

Page 263: ...low Table Pool 4 W ords x 64 1024 bytes Pool Descriptor 2 W ords x 8 xx80_0000H xx80_0040H xx80_1040H xx80_1440H xx80_1840H xx80_3FFFH W ork RAM 10 Kbytes 4 8 2 Transmission function VR4120A sets the VC information in VC table prior to the every packet transmission and issue Tx_Ready command with VC number in order to transmit packet belongs to the VC The transmitting data structure is described i...

Page 264: ...segment is indicated by the Buffer Read Address field in the VC table When the 53rd byte of the segment is written SAR FIFO is updated 3 Calculating the CRC 32 value and the length Each time a segment is read from SDRAM the CRC 32 value is calculated for that segment and transmitted bytes are also counted ATM Cell Processor writes those results in VC table 4 Updating the VC table Updates Buffer Re...

Page 265: ...cketInfo Structure PacketInfo Structure PacketInfo Structure 1 Packet info structure The Maximum number of Packet Info Structure for each VC is 16 However since total number of Packet Info Structure is 128 some VC may not obtain 16 Packet Info Structure depend on the queue length of other VCs When ATM Cell Processor can not obtain any Packet Info Structure ATM Cell Processor returns an error indic...

Page 266: ... be set by user If this value is set treats as 010 100 OAM F5 cell used to carry information between segments 101 OAM F5 cell used to carry information between end to end 110 Prohibited to be set by user PTI 111 Prohibited to be set by user GFC GFC field in the packet header is indicated IM Indicates if ATM Cell Processor issues the transmitting indication to VR4120A 1 Doesn t send any transmittin...

Page 267: ...MAINING BYTES IN CURRENT BUFFER 31 16 15 0 Word 3 CRC 32 COUNT 31 0 Word 4 BUFFER READ ADDRESS 31 0 Word 5 NEXT BUFFER ADDRESS 31 0 Word 6 MBS0 MBS RESERVED PHY No 31 5 4 0 Word 7 A 0 0 31 30 16 15 0 Word 8 0 PCR 31 16 15 0 Word 9 0 MCR 31 16 15 0 Word 10 RESERVED FOR SCHEDULING 31 0 Word 11 0 0 RESERVED FOR ABR USE 31 29 28 26 25 0 Word 12 RESERVED FOR ABR USE 31 0 Word 13 RESERVED 31 0 Word 14 R...

Page 268: ...o A Active bit indicating whether the VC table is in the active or idle state 1 Active state 0 Idle state MCR Minimum Cell Rate In VBR mode SCR has to be set in this field PCR Peak Cell Rate Word 10 These fields are used internally for scheduling use Word 11 Word 12 These fields are used internally FIRST PACKET INFO The start address of the first Packet Info structure in transmit queue for this VC...

Page 269: ... sending of the packet to PMD has been completed Upon storing a send indication into the mailbox ATM Cell Processor sets the corresponding MM bit of the A_GSR register to a 1 and issues an interrupt if it is not masked The indication that ATM Cell Processor sends to the host during transmission is of the following format Figure 4 30 Send Indication Format E VC Number A PACKET QUEUE POINTER 31 30 1...

Page 270: ...ble VR4120A sets the 16 word assigned blocks in Work RAM as the receive VC table for each VC d Setting up the Rx lookup table The VPI VCI of the receive cell are set in the Rx lookup table e Receiving the first cell of the packet Upon ATM Cell Processor receiving a cell it checks if the VPI VCI of the received cell has been registered in Rx lookup table If not registered the cell is discarded If r...

Page 271: ...OF BYTES 31 16 15 0 Word 3 CRC 32 COUNT 31 0 Word 4 BUFFER WRITE ADDRESS 31 0 Word 5 CURRENT BUFFER ADDRESS 31 0 Word 6 PACKET START ADDRESS 31 0 Word 7 T1D 0 31 17 16 15 0 Word 8 RESERVED FOR ABR USE 31 0 Word 9 RESERVED FOR ABR USE 31 0 Word 10 RESERVED FOR ABR USE 31 0 Word 11 RESERVED FOR ABR USE 31 0 Word 12 RIF0 RDF0 0 ECI ENI ER enb EER 31 28 27 24 23 19 18 17 16 15 0 Word 13 RESERVED 31 0 ...

Page 272: ...ress of the batch assigned first WORD 6 to WORD 12 These fields are used internally BACKWARD POINTER VC Number of the VC linked before this VC in the T1 link list LST Set to a 1 if the VC is the last one linked in the T1 link list FORWARD POINTER VC Number of the VC linked after this VC in the T1 link list 4 8 3 2 Non AAL 5 traffic support Every time ATM Cell Processor receives a raw cell it makes...

Page 273: ... 8 3 3 Receive indication For each packet ATM Cell Processor writes a receive indication as the reception completion status in the mailbox The mailbox used for reception is mailbox 0 and 1 More specifically ATM Cell Processor writes a receive indication at the following case 1 All cell data that belong to a packet are received No error is detected CRC 32 error or Length error is detected 2 An erro...

Page 274: ...rs ATM Cell Processor checks errors while a packet is being received and also after the packet has been received Upon detecting an error it reports the type of error the start address and the amount of data that had been transferred to system memory prior to the error being detected using the receive indication in the mailbox Upon receiving a receive indication containing the error status the VR41...

Page 275: ...e RID bit is set and the remaining cells of the packet that caused this error including the last cell are discarded The table below lists the errors that can occur with any of the first cell the immediate cells and the last cell of a packet Table 4 4 Reception Errors That Can Occur During Packet Reception Error When a cell is discarded When a receive indication is issued Handling of other cells af...

Page 276: ...MWA 3 0 sets the MM bit for the corresponding mailbox in the A_GSR register and issues an interrupt if it is not masked When updating the write pointer A_MWA 3 0 ATM Cell Processor causes A_MWA 3 0 to jump to the start address A_MSA 3 0 if A_MWA 3 0 has reached the bottom address A_MBA 3 0 To read an indication VR4120A uses the read pointer A_MTA 3 0 A_MTA 3 0 is managed by the VR4120A Each time V...

Page 277: ...ernet controller block The following list describes this block s hardware components and Figure 5 1 shows a block diagram of this block IBUS Interface Data transfer is done through this IBUS interface between CPU and Ethernet Controller or memory and Ethernet Controller This performance is approximately 2 Gbps 32 bits x 66 MHz Also in this block IBUS protocol operation is done retry disconnect and...

Page 278: ...Preliminary User s Manual S15543EJ1V0UM Figure 5 1 Block Diagram of Ethernet Controller TPO TPO TPI TPI Transceiver MII I O buffer MAC Core Ethernet Controller Block FIFO Cont Tx FIFO Rx FIFO DMA Master I F Slave I F IBUS µ µ µ µPD98502 ...

Page 279: ...ontrol Registers map is shown in Table 5 2 Table 5 2 MAC Control Register Map Offset Address Register Name R W Access Description 1000_m000H En_MACC1 R W W MAC Configuration Register 1 1000_m004H En_MACC2 R W W MAC Configuration Register 2 1000_m008H En_IPGT R W W Back to Back IPG Register 1000_m00CH En_IPGR R W W Non Back to Back IPG Register 1000_m010H En_CLRT R W W Collision Register 1000_m014H...

Page 280: ... occurred IRERR bit in NSR is set and NMI will assert to CPU 5 Read access to the reserved area will set the CBERR bit in the NSR register and the dummy read response data with the data error bit set on SysCMD 0 is returned 6 Write access to the reserved area will set the CBERR bit in the NSR register and the write data is lost 7 In the Access filed W means that word access is valid H means that h...

Page 281: ...me is received which is less than 64 bytes in length and contains a invalid FCS includes alignment error 1000_m17CH En_RJBR R W W Receive Error Oversize Packet Counter This counter is incremented each time a frame is received which exceeds 1518 bytes length and contains an invalid FCS or includes an alignment error 1000_m180H En_R64 R W W Receive 64 Byte Frame Counter This counter is incremented f...

Page 282: ...ransmitted which carrier sense error occurs during transmission 1000_m1FCH En_TIME R W W Transmit Internal MAC Error Counter This counter is incremented for each frame transmitted in which an internal MAC error occurs during transmission Remarks 1 In the Offset Address field and in the Register Name field Ethernet Controller 1 m 2 n 1 Ethernet Controller 2 m 3 n 2 2 In the R W field W means writea...

Page 283: ...er Remarks 1 In the Offset Address field and in the Register Name field Ethernet Controller 1 m 2 n 1 Ethernet Controller 2 m 3 n 2 2 In the R W field W means writeable R means readable RC means read cleared means not accessible 3 All internal registers are 32 bit word aligned registers 4 The burst access to the internal register is prohibited If such burst access has been occurred IRERR bit in NS...

Page 284: ...le RC means read cleared means not accessible 3 All internal registers are 32 bit word aligned registers 4 The burst access to the internal register is prohibited If such burst access has been occurred IRERR bit in NSR is set and NMI will assert to CPU 5 Read access to the reserved area will set the CBERR bit in the NSR register and the dummy read response data with the data error bit set on SysCM...

Page 285: ...preamble Setting this bit to a 1 allows the recognition of start of a new packet only when a pure preamble 0101 only is captured 6 FLCHT R W 0 Length field check When this bit is set to a 1 MAC Control Block compares the length field value in the packet to the actual packet length and indicates the result in the status vector When this bit is set 0 MAC does not check the Frame length field 5 NOBO ...

Page 286: ...ansmit packet is equal to the value in the En_VLTP register MAC pads the current packet as a VLAN packet when the current packet should be padded 4 VPD R W 0 VLAN PAD mode When this bit is set to a 1 MAC Control Block always pads the current packet as a VLAN packet when the current packet should be padded 3 0 Reserved R W 0 Reserved for future use Write 0s 5 2 4 En_IPGT Back to Back IPG Register B...

Page 287: ...in En_MACC1 register is set to a 0 Receive If the current receive packet length is greater than the value of MAXF MAC Control Block terminates the reception Transmit If the current transmit packet length is greater than the value of MAXF MAC Control Block aborts the transmission 5 2 8 En_RETX Retry Count Register Bits Field R W Default Description 31 4 Reserved R W 0 Reserved for future use Write ...

Page 288: ...k software reset Setting this bit to a 1 forces the MII Management Interface Block to transit to a software reset operation In order to complete the software reset this bit needs to be cleared 14 4 Reserved R W 0 Reserved for future use Write 0s 3 2 CLKS R W 0 Select frequency range This field sets the frequency range of the internal clock MDC is generated by dividing down the internal clock and t...

Page 289: ...gh the MII management interface 5 2 17 En_MRDD MII Read Data Register Bits Field R W Default Description 31 16 Reserved R 0 Reserved for future use 15 0 CTLD R 0 MII read data This field indicates the MII management read data for read access through the MII management interface 5 2 18 En_MIND MII Indicate Register Bits Field R W Default Description 31 3 Reserved R 0 Reserved for future use 2 NVALI...

Page 290: ...le are accepted Please refer to 5 3 6 0 ABC R W 0 Accept Broadcast When this bit is set to a 1 all broadcast packets are accepted Please refer to 5 3 6 5 2 20 En_HT1 Hash Table Register 1 Bits Field R W Default Description 31 0 HT1 R W 0 Hash table 1 This register is used with the HT2 register as the hash table It is used for detection of qualified multicast packets This register sets the upper 32...

Page 291: ...T R W 0 En_RVBT counter carry bit 14 C1UT R W 0 En_TUCA counter carry bit 13 C1BT R W 0 En_TBCA counter carry bit 12 C1MT R W 0 En_TMCA counter carry bit 11 C1PT R W 0 En_TPCT counter carry bit 10 C1TB R W 0 En_TBYT counter carry bit 9 C1MX R W 0 En_RMAX counter carry bit 8 C11K R W 0 En_R1K counter carry bit 7 C1FE R W 0 En_R511 counter carry bit 6 C1TF R W 0 En_R255 counter carry bit 5 C1OT R W ...

Page 292: ... R W 0 En_TXCL counter carry bit 18 C2LC R W 0 En_TLCL counter carry bit 17 C2MC R W 0 En_TMCL counter carry bit 16 C2SC R W 0 En_TSCL counter carry bit 15 C2XD R W 0 En_TXDF counter carry bit 14 C2DF R W 0 En_TDFR counter carry bit 13 C2XF R W 0 En_TXPF counter carry bit 12 C2TE R W 0 En_TFCS counter carry bit 11 C2JB R W 0 En_RJBR counter carry bit 10 C2FG R W 0 En_RFRG counter carry bit 9 C2OV ...

Page 293: ... carry mask bit 13 M1BT R W 0 En_TBCA counter carry mask bit 12 M1MT R W 0 En_TMCA counter carry mask bit 11 M1PT R W 0 En_TPCT counter carry mask bit 10 M1TB R W 0 En_TBYT counter carry mask bit 9 M1MX R W 0 En_RMAX counter carry mask bit 8 M11K R W 0 En_R1K counter carry mask bit 7 M1FE R W 0 En_R511 counter carry mask bit 6 M1TF R W 0 En_R255 counter carry mask bit 5 M1OT R W 0 En_R127 counter ...

Page 294: ...FCS counter carry mask bit 11 M2JB R W 0 En_RJBR counter carry mask bit 10 M2FG R W 0 En_RFRG counter carry mask bit 9 M2OV R W 0 En_ROVR counter carry mask bit 8 M2UN R W 0 En_RUND counter carry mask bit 7 M2FC R W 0 En_RFCR counter carry mask bit 6 M2CD R W 0 En_RCDE counter carry mask bit 5 M2FO R W 0 En_RFLR counter carry mask bit 4 M2AL R W 0 En_RALN counter carry mask bit 3 M2UO R W 0 En_RXU...

Page 295: ...inter this MAC Control Block sends an Abort Packet Please see the Figure 5 2 This is a word pointer 9 8 Reserved R W 0 Reserved for future use Write 0s 7 2 TX_FRTH R W 30H Transmit Fill Threshold Level This threshold is enable to transmit data to the FIFO from the internal bus through the DMAC of this block Please see the Figure 5 2 This is a word pointer 1 0 Reserved R W 0 Reserved for future use...

Page 296: ...se Write 0s 5 2 29 En_RXCR Receive Configuration Register Bits Field R W Default Description 31 RXE R W 0 Receive Enable 0 Disable 1 Enable 30 19 Reserved R W 0 Reserved for future use Write 0s 18 16 DRBS 2 0 R W 0 DMA Receive Burst Size 000 1 Word 4 bytes 001 2 Word 8 bytes 010 4 Word 16 bytes 011 8 Word 32 bytes 100 16 Word 64 bytes 101 32 Word 128 bytes 110 64 Word 256 bytes 111 Reserved for fu...

Page 297: ...ure use Write 0s 7 2 RX_DRTH R W 10H Receive Drain Threshold Level This threshold is enable to the transmit data to the IBUS via internal DMAC form the FIFO Please see the Figure 5 3 This pointer is a word pointer 1 0 Reserved R W 0 Reserved for future use Write 0s Figure 5 3 Rx FIFO Control Mechanism DRTH DRTH DRTH Rx_FIFO 256 Bytes DRTH EOF No Packet data Beginning of the frame Request to transm...

Page 298: ...are Reset 5 2 34 En_ISR Interrupt Serves Register Bits Field R W Default Description 31 16 Reserved RC 0 Reserved for future use 15 XMTDN RC 0 Transmit Done 14 TBDR RC 0 Transmit Buffer Descriptor Request at Null 13 TFLE RC 0 Transmit Frame Length Exceed 12 UR RC 0 Underrun 11 TABR RC 0 Transmit Aborted 9 8 Reserved RC 0 Reserved for future use 10 TCFRI RC 0 Control Frame Transmit 7 RCVDN RC 0 Rec...

Page 299: ...mit Done 14 TBDR R W 0 Transmit Buffer Descriptor Request at Null 13 TFLE R W 0 Transmit Frame Length Exceed 12 UR R W 0 Underrun 11 TABR R W 0 Transmit Aborted 9 8 Reserved R W 0 Reserved for future use Write 0s 10 TCFRI R W 0 Control Frame Transmit 7 RCVDN R W 0 Receive Done 6 RBDRS R W 0 Receive Buffer Descriptor Request at alert level 5 RBDRU R W 0 Receive Buffer Descriptor Request at zero 4 O...

Page 300: ... iii MII Management Registers iv Pool Buffer Descriptor Registers 5 3 2 Buffer structure for Ethernet Controller block The data buffer structure for Ethernet Controller is shown in Figure 5 4 Figure 5 4 Buffer Structure for Ethernet Block Buffer Descriptor Buffer Descriptor Buffer Descriptor Link Pointer Data Buffer Data Buffer Data Buffer Buffer Descriptor Buffer Descriptor Buffer Descriptor Link...

Page 301: ...er 1 Ethernet Controller 0 VR4120A Ethernet Controller sets this bit after it began to transfer data into each descriptor 28 DBRE Data Buffer Read Error 27 TUDR Transmit Underrun Error 26 CSE Carrier Sense Lost Error 25 LCOL Late Collision 24 ECOL Excessive Collision 23 EDFR Excessive Deferral 22 19 Reserved for future use Write 0s 18 TGNT Transmit Giant Frame 17 Reserved for future use Write 0s 1...

Page 302: ...or Pointer Register En_TXDPR and the Transmit Enable TXE Ethernet Controller fetches the first Transmit Data Buffer from Buffer Descriptor When the drain threshold level of the transmit FIFO was over the MAC Controller Block transmit logic will start transmitting the preamble sequence the start frame delimiter and then the frame information However the controller defers the transmission if the lin...

Page 303: ... Controller writes the transmission status into the last descriptor L 1 and generates an interrupt to indicates the end of transmission After this Ethernet Controller fetches the next Transmit Buffer Descriptor and then if the next data is available it will be sent out in the same manner When Ethernet Controller received the pause control frame and if it is active Ethernet Controller transmitter s...

Page 304: ...Negotiation Link Configuration Prepare Buffer Descriptors and Transmit Data mem Set Transmit Descriptor address Set XMDP Set Transmit Enable Set TXE Get transmit data Exceed TXDRTH Send Preamble SFD and Data FCS mem Write TX_Status and Read next Descriptor data Generate interrupt Transmit done Interrupt Carrier Sense Status Check and Preparation for next data Carrier Sense Encode Scramble ...

Page 305: ...g packet If the PA SFD is valid it will be stripped and the frame will be processed by the receiver If a valid PA SFD is not found the frame will be ignored Once a collision window 64 bytes of data has been received and if address recognition has not rejected the frame Ethernet Controller starts transferring the incoming frame to the receive data buffer If the frame is a runt due to collision or i...

Page 306: ...thernet Controller then waits for a new frame Receive procedure is as follows Figure 5 8 Figure 5 8 Receive Procedure VR4120A Ethernet Controller External PHY Device Initialize Registers Initialize Auto Negotiation Link Configuration Prepare Buffer Descriptors mem Set Receive Descriptor address Set Receive Enable Set RCVDP Set RXE Decode Descramble Exceed RXDRTH Transfer Receive Data mem If data b...

Page 307: ...ng The Ethernet Controller can parse a destination address in a received packet The destination address is filtered using the condition in En_AFR register set by VR4120 The condition for unicast multicast and broadcast can be configured independently 1 Unicast address filtering The destination address in a received packet is compared with the station address in En_LSA1 and En_LSA2 registers When b...

Page 308: ...s to be received Filtering procedure is as follows At first SRXEN bit in En_MACC1 register is set to a 1 In this case the received data interface is disabled Then the station address is set in En_LSA1 and En_LSA2 registers En_AFR register is also set for enabling of unicast multicast and broadcast reception In addition En_HT1 and En_HT2 registers should be set when multicast address filtering with...

Page 309: ...ts a built in 64 byte Tx FIFO for Control transfer Supports a built in 128 byte Tx FIFO for Isochronous transfer Supports a built in 128 byte Tx FIFO for Bulk transfer Supports a built in 64 byte Tx FIFO for Interrupt transfer Supports a built in 128 byte shared Rx FIFO for Control Isochronous Bulk Interrupt transfer Supports a DMA function for transferring transmit receive data Supports Control S...

Page 310: ...el conversion NRZI encoding decoding CRC calculation etc EPC EndPoints Controller Performs data transmission reception for each Endpoint Tx FIFO Transmit FIFO FIFO for transmitting data Rx FIFO Receive FIFO FIFO for receiving data MCONT Main Controller Block for controlling transmission and reception DMAC DMA Controller Block for controlling DMA transfer Master_if Master Interface Master section o...

Page 311: ...40H U_CMR R W W USB Command Register 1000_1044H U_CA R W W H B USB Command Address Register 1000_1048H U_TEPSR R W H B USB Tx EndPoint Status Register 1000_104CH N A Reserved for future use 1000_1050H U_RP0IR R W W H B USB Rx Pool0 Information Register 1000_1054H U_RP0AR R W H B USB Rx Pool0 Address Register 1000_1058H U_RP1IR R W W H B USB Rx Pool1 Information Register 1000_105CH U_RP1AR R W H B ...

Page 312: ...the CBERR bit in the NSR register and the dummy read response data with the data error bit set on SysCMD 0 is returned 5 Write access to the reserved area will set the CBERR bit in the NSR register and the write data is lost 6 In the Access filed W means that word access is valid H means that half word access is valid B means that byte access is valid 7 Write access to the read only register cause...

Page 313: ... not care the timing between two consecutive SOF packets 7 3 Reserved R W 0 Reserved for future use Writes 0 s 2 AU R W 0 Auto Update Frame Number auto updating enable To set to a 1 causes Frame Number Register to be updated though a received SOF packet is corrupted 1 LE R W 0 Loopback Enable Bit for enabling internal loopback mode When this bit is set to a 1 USB Controller operates in loopback mo...

Page 314: ...set to a 0 when the VR4120A reads this register 18 RPA2 RC 0 Rx Pool2 Alert This bit is set to a 1 when the number of Buffer Directories remaining in receive Pool2 gets equal to 4 times of the AL field value in the Rx Pool2 Information Register This bit is reset to a 0 when the VR4120A reads this register 17 RPA1 RC 0 Rx Pool1 Alert This bit is set to a 1 when the number of Buffer Directories rema...

Page 315: ...et to a 0 when the VR4120A reads this register 4 EP3TF RC 0 EP3 Tx Finished Bit that indicates that EndPoint3 Bulk IN has completed the transmitting of a data segment and issued the Tx Indication This bit is reset to a 0 when the VR4120A reads this register 3 EP2RF RC 0 EP2 Rx Finished Bit that indicates that EndPoint2 Isochronous OUT has completed the receiving of a data segment and issued the Rx...

Page 316: ... W 0 Tx MailBox Full 1 unmask 0 mask 22 RMF R W 0 Rx MailBox Full 1 unmask 0 mask 21 RPE2 R W 0 Rx Pool2 Empty 1 unmask 0 mask 20 RPE1 R W 0 Rx Pool1 Empty 1 unmask 0 mask 19 RPE0 R W 0 Rx Pool0 Empty 1 unmask 0 mask 18 RPA2 R W 0 Rx Pool2 Alert 1 unmask 0 mask 17 RPA1 R W 0 Rx Pool1 Alert 1 unmask 0 mask 16 RPA0 R W 0 Rx Pool0 Alert 1 unmask 0 mask 15 11 Reserved R W 0 Reserved for future use Wri...

Page 317: ...17 Bits Field R W Default Description 4 EP3TF R W 0 EP3 Tx Finished 1 unmask 0 mask 3 EP2RF R W 0 EP2 Rx Finished 1 unmask 0 mask 2 EP1TF R W 0 EP1 Tx Finished 1 unmask 0 mask 1 EP0RF R W 0 EP0 Rx Finished 1 unmask 0 mask 0 EP0TF R W 0 EP0 Tx Finished 1 unmask 0 mask ...

Page 318: ... Extra Data on EndPoint2 This bit is set to a 1 when an extra data packet is detected on Isochronous EndPoint EP2 In the case that EP2EN bit in U_EP2CR is set to a 0 this bit will not be set even if the USB Controller detects an extra data on EP2 5 EP2ND RC 0 Isochronous Data Corrupted on EndPoint2 Bit that indicates that Isochronous data is corrupted on EP2 In the case that EP2EN bit in U_EP2CR i...

Page 319: ...0 IFN R W 0 Incorrect Frame Number 1 unmask 0 mask 19 IEA R W 0 Incorrect EndPoint Access 1 unmask 0 mask 18 URSM R W 0 USB Resume 1 unmask 0 mask 17 URST R W 0 USB Reset 1 unmask 0 mask 16 USPD R W 0 USB Suspend 1 unmask 0 mask 15 8 Reserved R W 0 Reserved for future use Writes 0 s 7 EP2OS R W 0 Over Size 1 unmask 0 mask 6 EP2ED R W 0 Extra Data on EndPoint2 1 unmask 0 mask 5 EP2ND R W 0 Isochron...

Page 320: ...his bit to a 1 a NAK packet is sent at the Data Phase 18 OSS R W 0 OUT Transmit Stall When the VR4120A sets this bit to a 1 a STALL handshake is performed at the Handshake Phase Receiving a SETUP packet causes this bit to be a 0 17 NHSK0 R W 0 No Handshake When the VR4120A sets this bit to a 1 No Handshake is performed at the Handshake Phase 16 ONAK R W 0 OUT NAK When the VR4120A sets this bit to ...

Page 321: ... USB EP2 Control Register This register is used for setting the operation of EndPoint2 If the value in the MAXP field is rewritten during receiving operation the operation of USB Controller may become unpredictable Therefore the MAXP can be written only when initial setting is being performed Bits Field R W Default Description 31 EP2EN R W 0 EndPoint Enable When the VR4120A sets this bit to a 1 En...

Page 322: ...d for future use Writes 0 s 19 TM3 R W 0 Tx Mode Bit for setting the transmit mode When this bit is set to a 0 transmitting is performed in SZLP Mode When this bit is set to a 1 transmitting is performed in NZLP Mode For a detailed explanation of the transmit modes see Section 6 5 3 18 SS3 R W 0 Transmit Stall When the VR4120A sets this bit to a 1 a STALL packet is sent from EndPoint3 17 Reserved ...

Page 323: ...ode When these bits are set to 00 or 01 data receiving is performed in Normal Mode When these bits are set to 10 data receiving is performed in Assemble Mode When these bits are set to 11 data receiving is performed in Separate Mode For a detailed explanation of the receive modes see Section 6 6 4 18 SS4 R W 0 Transmit Stall When the VR4120A sets this bit to a 1 a STALL handshake is performed at E...

Page 324: ... Reserved for future use Writes 0 s 6 0 MAXP5 R W 0 MAX Packet size The Max Packet Size for EndPoint5 Prior to the start of a USB transaction the VR4120A must set an appropriate value into this register 6 2 14 U_EP6CR USB EP6 Control Register This register is used for setting the operation of EndPoint6 If the value in the MAXP field is rewritten during receiving operation the operation of USB Cont...

Page 325: ...ransmitting at EndPoint1 010 Data transmitting at EndPoint3 011 Data transmitting at EndPoint5 100 Addition of Buffer Directories to Pool0 101 Addition of Buffer Directories to Pool1 110 Addition of Buffer Directories to Pool2 111 Reserved Don t Use 23 16 Reserved R W 0 Reserved for future use Writes 0 s 15 0 Data Size NOD R W 0 Data Size Number Of Buffer Directory The meaning of this field depend...

Page 326: ... two data items that are scheduled to be sent Busy 7 2 Reserved R 0 Reserved for future use 1 0 EP0TS R 0 EP0 Tx Status Register that indicates the transmit status of EndPoint0 This register is not cleared even if read 00 There is no data scheduled to be sent Idle 01 There is one data item scheduled to be sent 10 There are two data items that are scheduled to be sent Busy 6 2 18 U_RP0IR USB Rx Poo...

Page 327: ...ries remaining in this pool equals the value set in this field USB Controller sets the RPA1 bit in the USB General Status Register1 to a 1 Writing N in this field is equivalent to specifying N x 4 remaining number of Buffer Directories 4 8 12 28 When 000 is written into this field this function is disabled and no notification is posted to the VR4120A 27 16 Reserved R W 0 Reserved for future use Wr...

Page 328: ...er 6 2 23 U_RP2AR USB Rx Pool2 Address Register This register indicates the start address of Buffer Directory which is currently used The way to set up Rx Pool is described at Section 6 6 3 Receive pool settings Bits Field R W Default Description 31 0 Address R 0 Buffer Directory Address Register that indicates the start address of the first Buffer Directory in Pool2 The VR4120A can only read this...

Page 329: ... MailBox Bottom Address Register Bits Field R W Default Description 31 0 Address R W 0 Register that indicates the end address of the receive MailBox area The VR4120A must set a value in this field only at initialization 6 2 30 U_RMRA USB Rx MailBox Read Address Register Bits Field R W Default Description 31 0 Address R W 0 Register that indicates the address of the area that will be read next by ...

Page 330: ... port of the µPD98502 is attached to a HUB 2 Notification that a new device µPD98502 has been connected to the HUB is posted to a Host PC 3 The Host PC issues Reset Signaling to reset the port to which the device has been connected 4 Once 10 ms have elapsed the Host PC halts the issue of the Reset Signaling 5 Notification of the Reset Signaling performed by the Host PC is posted to USB Controller ...

Page 331: ...gister Address 1000_1084H When Tx MailBox Start Address Register is set the value in the register is copied to Tx MailBox Read Address Register Address 1000_1078H and Tx MailBox Write Address Register Address 1000_107CH In same way when Rx MailBox Start Address Register is set the value in the register is copied to Rx MailBox Read Address Register Address 1000_1088H and Rx MailBox Write Address Re...

Page 332: ...RMSA USB Rx MailBox Start Address Register 1000_1080H U_RMBA USB Rx MailBox Bottom Address Register 1000_1084H U_RMRA USB Rx MailBox Read Address Register 1000_1088H U_RMWA USB Rx MailBox Write Address Register 1000_108CH Remarks 1 When the VR4120A writes the value to U_TMSA firstly after reset USB Controller automatically copies the value to U_TMRA and U_TMWA internally Similarly when VR4120A wri...

Page 333: ...RA or U_RMRA to prevent the overwriting of those indications that the VR4120A has not yet read out The read pointer U_TMRA or U_RMRA is managed by the VR4120A Each time the VR4120A reads an indication from a MailBox it writes the address to be read next time into the read pointer register U_TMRA or U_RMRA When both the write pointer U_TMWA or U_RMWA and read pointer U_TMRA or U_RMRA point to the s...

Page 334: ...B packet size is equal to the value in the MAXP field a zero length USB packet will be transmitted after the last item of the divided data in transmit SZLP Mode In transmit NZLP Mode a zero length USB packet is not transmitted For an explanation of the transmit modes see Section 6 5 3 Data transmit modes After all the data segments have been transferred USB Controller writes the transmit indicatio...

Page 335: ...a Buffer Buffer desc L 1 Data Buffer Data Buffer Link pointer Buffer descriptor Data Buffer Tx Packet Buffer Directory A transmit packet is configured by breaking up multiple data buffers in system memory These data buffers are bundled together in the buffer directory The formats of the Buffer directory Buffer descriptor and Link Pointer in the Tx buffer are as shown below ...

Page 336: ...ffer Descriptor This is the Tx buffer descriptor It maintains the data in the Tx BUFFER When Bit 31 Last bit is set the Buffer Descriptor indicates the last buffer in a packet Bit30 is used to discriminate between the Buffer Descriptor and Link Pointer When set to 1 this bit indicates the Buffer Descriptor The Size field indicates the buffer size As the buffer size a value between 1 and 65535 byte...

Page 337: ...ies only to EndPoint1 and EndPoint3 2 When EndPoint0 and EndPoint5 are used to transmit data only NZLP mode is used 1 SZLP Transmit Zero Length Packet mode In this mode when the last USB packet size of a data segment is equal to the value in the MAXP field a zero length packet is transmitted after the completion of data segment transmitting When the last packet size is less than the value in the M...

Page 338: ...repare Tx data in the memory Reads USB Tx EndPoint Status Register Reads USB Command Register Busy bit 1 EndPoint is Busy Yes Yes No No Issues transmit command Reads USB General Status Register Reads register TMRA which addresses transmit mailbox Reads Tx indication Updates read pointer of mailbox Issue processing of Tx command Read processing of Tx indication 1 2 4 5 6 9 7 10 11 3 End of transmis...

Page 339: ... of a data segment can be scheduled A transmit command is issued by writing a value into the registers listed below When writing it is necessary to write first to the USB Command Extension Register then the USB Command Register If data size field of USB Command Register is 0 USB Controller transmits Zero Length Packet The size of data set by the transmission command and the total size of data buff...

Page 340: ...reliminary User s Manual S15543EJ1V0UM Figure 6 9 Transmit Status Register 31 15 EP3 0 16 23 8 EP5 EP0 7 EP1 24 USB Tx EndPoint Status Register 48H Corresponding to each EndPoint 00 Idle 01 Sending one data 10 Sending two data Busy ...

Page 341: ...al register and clears USB Command Register Busy bit Rest area of Tx FIFO Buffer size Yes No No Transfers to USB Updates write pointer of Tx mailbox Sets Tx End bit in UGSR1 register 1 5 6 7 9 8 10 13 3 Specified EndPoint is Busy Yes W ait until the EndPoint can execute Tx command Reads buffer descriptor DMA transfers from buffer to FIFO DMA transfer from buffer to FIFO Reads next buffer descripto...

Page 342: ...criptor 7 USB Controller compares the size of the area remaining in the Tx FIFO with the buffer size of the buffer descriptor read in the previous step 8 If step 7 reveals that the area remaining in the Tx FIFO is smaller USB Controller transfers the data from the buffer until the Tx FIFO is full by DMA 9 Once the Tx FIFO is full USB Controller transfers the data to the USB 10 If step 7 reveals th...

Page 343: ...11 3 Status Field that indicates the status upon data transmitting Bit10 When set to a 0 indicates that an IBUS error has not occurred When set to a 1 indicates that processing is terminated abnormally due to an IBUS error Bit9 When set to a 0 indicates that a buffer underrun did not occur during data transmitting When set to a 1 indicates that a buffer underrun occurred This bit is set only when ...

Page 344: ...e divided to USB packets with the same byte size as a value set in the MAXP field the last USB packet of the data segment will be smaller than the value set in the MAXP field 40 bytes in the example shown above As a result USB Controller can identify the boundary between data segments If the last USB buffer size is equal to the value in the MAXP field a zero length USB packet will be transmitted f...

Page 345: ...uffer Configuration Buffer descriptor Buffer descriptor Buffer descriptor Data Buffer Data Buffer Data Buffer Link pointer Buffer descriptor Data Buffer Data Buffer Buffer descriptor Buffer Directory Link pointer Size 1 64k Bytes Buffer descriptor Data Buffer The receive buffer is composed of the Buffer Directory and Data Buffer The receive buffer is prepared in system memory by the VR4120A The fo...

Page 346: ...riptors Rx Buffer Descriptor Contains the Rx buffer data When Bit31 Last bit is set to a 1 that Buffer Descriptor indicates the last buffer in the pool Bit30 is used to discriminate between the Buffer Descriptor and Link Pointer When set to 1 this bit indicates the Buffer Descriptor The Size field indicates the buffer size As the buffer size a value between 1 and 65535 bytes can be set The Buffer ...

Page 347: ...ories to a receive pool the VR4120A performs the following processing 1 The VR4120A places the Buffer Directory to be added to the pool and the buffer in system memory When multiple Buffer Directories are to be added they are linked in advance 2 The VR4120A sets the start address of the Buffer Directory to be added into the link pointer to the last Buffer Directory in the list of dependent Buffer ...

Page 348: ...D field of the command into the RNOD field of the Pool Information Register Furthermore it loads the value written in the USB Command Extension Register into the Pool Address Register 6 6 4 Data receive mode USB Controller has different receive processing every EndPoint and receive mode The receive mode is determined by RM field Bits 20 19 in USB EP2 Control Register Address 1000_1028H and USB EP4...

Page 349: ...ndication to the Mailbox USB Controller updates the size field and Last field in Buffer Descriptor every USB packet before writing Rx Indication 2 EndPoint2 EndPoint4 normal mode The processing in EndPoint2 EndPoint4 receive Normal mode is explained below Figure 6 17 EndPoint2 EndPoint4 Receive Normal Mode D0 µ PD98502 Buffer Directory D1 D2 D3 D0 D1 D2 Rx Indication Rx Indication Rx Indication D0...

Page 350: ... Controller updates Size field Last bit in last Buffer Descriptor and issues Rx indication 4 EndPoint2 EndPoint4 separate mode The processing in EndPoint2 EndPoint4 receive separate mode is explained below Figure 6 19 EndPoint2 EndPoint4 Receive Separate Mode D0 µ PD98502 Buffer Directory D1 D2 D1 D2 D2 Rx Indication Rx Indication Rx Indication Rx Indication D0 D0 D1 D2 In this mode after USB Cont...

Page 351: ...ool Numbers 1 to 7 do not indicate the order in which the VR4120A must perform processing Instead these numbers correspond to those in the following explanation 1 First as part of initialization the VR4120A must set Pool configuration 2 For receiving the VR4120A must add Buffer Directories to the Pool if necessary 3 The VR4120A reads the USB General Status Register 4 The VR4120A checks whether rec...

Page 352: ... performed by USB Controller in Normal Mode Figure 6 21 USB Controller Receive Operations Normal Mode Stores the data from USB to receive FIFO Receives data from USB CRC verify Bit Stuffing verify NRZI decode Encounters link pointer Yes No DMA transfers to system memory Writes Rx indication Updates write pointer Sets Rx completion bit of corresponding EndPoint in U_GSR register 1 2 5 7 8 9 3 Waits...

Page 353: ...tch a new buffer descriptor 5 USB Controller checks whether the fetched buffer descriptor is a link pointer or not 6 If the fetched buffer descriptor is a link pointer USB Controller updates the Pool Information Registers and restarts to fetch a new buffer descriptor 7 USB Controller then DMA transfers data from the FIFO to system memory 8 If USB Controller finds that the transferred data is the l...

Page 354: ...ode Stores the data from USB to receive FIFO Receives data from USB CRC verify Bit Stuffing verify NRZI decode Buffer is remaining in system memory area Yes No DMA transfers to system memory W rites Rx indication Updates write pointer Sets Rx completion bit of corresponding EndPoint in UGSR register 1 2 4 8 10 11 3 W aits data Fetches new buffer descriptor Encounters link pointer Updates Pool Info...

Page 355: ... remaining in system memory area USB Controller starts to fetch new buffer descriptor 6 USB Controller checks whether the fetched buffer descriptor is a link pointer or not 7 If the fetched buffer descriptor is a link pointer USB Controller updates the Pool Information Registers and restarts to fetch a new buffer descriptor 8 USB Controller then DMA transfers data from the FIFO to system memory 9 ...

Page 356: ...e data from USB to receive FIFO Receives data from USB CRC verify Bit Stuffing verify NRZI decode Buffer is remaining in system memory area Yes No DMA transfers to system memory W rites Rx indication Updates write pointer Sets Rx completion bit of corresponding EndPoint in UGSR register 1 2 4 8 10 11 3 W aits data Fetches new buffer descriptor Encounters link pointer Updates Pool Information Regis...

Page 357: ...ning in system memory area USB Controller starts to fetch new buffer descriptor 6 USB Controller checks whether the fetched buffer descriptor is a link pointer or not 7 If the fetched buffer descriptor is a link pointer USB Controller updates the Pool Information Registers and restarts to fetch a new buffer descriptor 8 USB Controller then DMA transfers data from the FIFO to system memory 9 USB Co...

Page 358: ...l Status Register 3 If Extra Data error has occurred EP2ED bit Bit 6 in USB General Status Register 2 will be set In this case USB Controller only reflect the error to USB General Status Register 4 If Extra SOF error has occurred ES bit Bit 1 in USB General Status Register 2 will be set In this case USB Controller only reflect the error to USB General Status Register USB Controller can detect the ...

Page 359: ...EndPoint1 If IN TOKEN packet for EndPoint2 comes which between two SOFs USB Controller will set EP1ET bit Bit 3 in USB General Status Register 2 In this case USB Controller will transmit data only once No Token on EndPoint1 If IN TOKEN packet for EndPoint2 does not come between two SOFs USB Controller will set EP1NT bit Bit 4 in USB General Status Register 2 ...

Page 360: ...ch addresses Data Buffer by Max Packet Size No DMA transfer occurs USB Controller writes Rx indications which indicates that received data is corrupted on Isochronous EndPoint c Rx separate mode USB Controller sets EP2ND EndPoint2 No Data bit Bit 6 in USB General Status Register 2 USB Controller writes dummy data to Data Buffer In fact USB Controller only increment pointer which addresses Data Buf...

Page 361: ...fer Directory Valid Corrupted Data Max Packet Size Max Packet Size 6 6 9 Rx FIFO overrun On Isochronous Rx EndPoint EP2 if data reading from Rx FIFO is delayed by some problem Rx FIFO Overrun will occur In the case of corruption action of USB Controller varies according to Rx Mode a Rx normal mode USB Controller sets EP2FO EndPoint2 No Data bit Bit 9 in USB General Status Register 2 USB Controller...

Page 362: ...to the receive MailBox After writing a receive indication USB Controller sets the receive completion bit of the USB General Status Register to a 1 and issues an interrupt if it is not masked The format of the receive indication is as shown below Figure 6 26 Receive Indication Format 31 15 0 16 Status Size Address 26 Reserved 25 EPN 30 29 Word1 Word2 28 Remark Bit28 to Bit26 are reserved EPN Field ...

Page 363: ... to 1 when receiving data from the Isochronous EndPoint EndPoint2 it indicates that the data stored in system memory contains a Bit Stuffing Error This bit is set only when receiving the data from the EndPoint2 In the assemble mode this bit is set only the following case the USB packet which is received at last has error Bit18 When set to a 0 indicates that the size of the received data is up to 6...

Page 364: ... m s If USB has no activity for m ore than 3 ms the device connected to USB transits in Suspend state Sets USPD bit Bit16 in USB General Status Register 2 to a 1 issues the interruption to VR4120A Receives USB interruption reads status register Recognizes USB became suspend state Host PC 2 Transits in suspend state because USB has no activity for m ore than 3 m s 3 4 2 1 µ PD98502 1 The host place...

Page 365: ... Signaling transits to Resume state Ends of Resum e processing 2 3 4 5 6 µ PD98502 1 The Host PC starts Resume Signaling The Resume Signaling is passed to every device connected to the USB 2 After at least 20 ms have elapsed the Host PC stops the Resume Signaling then performs EOP Signaling for a 2bit time duration 3 This causes the Host PC to terminate its Resume processing 4 USB Controller recei...

Page 366: ...de Register in order to switch the USB in the Suspend status to the Resume status 3 Once the RR bit of the USB General Mode Register has been set USB Controller starts K state Signaling for the USB 4 The VR4120A can continue to set transmit data for the USB Specifically the VR4120A prepares transmit data in system memory then writes data into the USB Command Register Address 1000_1040H and the USB...

Page 367: ...orrect SOF 0 Just load the received Frame Number FW bit is set to 1 1 Just load the received Frame Number FW bit is set to 1 Loss of SOF 0 Not updated SL bit is set to 1 1 Increment the current FN FW bit and SL bit are set to 1 Extra SOF 0 Not updated ES bit is set to 1 1 Not updated ES bit is set to 1 Bit Stuff Error 0 Just load the received Frame Number FW bit is set to 1 1 Increment the current...

Page 368: ... and receiving should be performed using the normal settings The Tx and Rx indications are issued as normal The internal data flow is as shown below Figure 6 31 Data Flow in Loopback Mode IBUS I F Controller Tx data Rx data EP Controller SIE Tx FIFO Rx FIFO As shown in the figure in loopback mode data reception from the USB and data transmission to the USB are not performed All data is returned by...

Page 369: ...V power supply to indicate the presence of a full speed device To avoid current floating on the integrated USB Buffer it is recommended to place a 51 kΩ pull down resistor between the D pin and the GND The circuit must be designed such that the µPD98502 power supply is turned on and off together with the external 3 3 V power supply If the µPD98502 power supply is off but the external 3 3 V power s...

Page 370: ...he PCI Controller are as follows 32 bit PCI Interface 33 MHz PCI frequency capable Compliant to PCI Local Bus Specification Rev 2 2 Compliant to PCI bus Power Management Interface Rev 1 1 Supports up to 16 word burst access Supports posted write function Supports Delayed Non Delayed read write cycle Implements PCI bus arbiter that supports up to 4 external PCI master devices at Host mode Figure 7 ...

Page 371: ...e that Cache Line Size register is valid which means Cache Line Size is 4 or 8 or 16 or 32 the PCI Controller uses 3 kinds of PCI memory commands for read transactions in accordance with the recommendation in PCI Specification Memory Read The case of reading a single 32 bit word Memory Read Line The case of reading more than a 32 bit word up to the next cache line boundary Memory Read Multiple The...

Page 372: ... the new write transaction on internal bus again Note Internal bus block is a block connecting to the internal bus like USB controller All of other internal bus devices than the PCI Controller can issue access cycle to external PCI devices The VR4120A can also issue access cycles to the PCI devices through the system controller Figure 7 2 Posted Write Transaction from Internal Bus to PCI PCI Contr...

Page 373: ...r issues disconnect to the internal bus block that try to continue the write access as the burst transfer The internal bus block should terminate the transaction as soon as possible Note Internal bus feature is not described in this document Internal bus has a similar feature to PCI bus Then internal bus supports disconnect function Figure 7 3 Non Posted Write Transaction from Internal Bus to PCI ...

Page 374: ...ntroller issues retry to other accesses 6 When the same access comes which means the access with the same address and the same command the PCI Controller accepts this access and returns the data from the internal FIFO Figure 7 4 Delayed Read Transaction from Internal Bus to PCI PCI Controller PCI Target Device Internal Bus Block 1 4 2 3 5 6 The maximum burst size is 16 words so that when more than...

Page 375: ...this access 5 The PCI Controller returns the read 1 word data to internal bus block At the same time the PCI Controller issues disconnect to internal bus block when the block tries to continue the burst read transaction The internal bus block must terminate the transaction as soon as possible Figure 7 5 Non Delayed Read Transaction from Internal Bus to PCI PCI Controller PCI Target Device Internal...

Page 376: ...in order to read write to the internal registers of the PCI Controller When the issued burst transfer goes over the boundary of the address space the PCI Controller issues disconnect at the boundary 7 2 2 2 Access type 1 PCI target The acceptable PCI commands for the PCI Controller are as follows C BE 3 0 PCI commands As PCI Target 0000 Interrupt Acknowledge Ignored 0001 Special Cycle Ignored 0010...

Page 377: ...rite transaction to the internal bus target block 4 The internal bus target block accepts this access and the PCI Controller completes the write transaction to it After the completion of the transaction the PCI Controller can accepts the new write access on PCI bus again Figure 7 6 Posted Write Transaction from PCI to Internal bus PCI Controller PCI Master Device Internal Bus Block 1 2 3 4 The max...

Page 378: ...bus target block accepts this access and the PCI Controller writes the first word which is latched to it 5 The PCI Controller asserts TRDY_B in order to indicate that first data phase is completed Then the PCI Controller issues disconnect to PCI master device when it issues the burst transfer PCI master device should terminates the transaction as soon as possible Figure 7 7 Non Posted Write Transa...

Page 379: ... FIFO Figure 7 8 Delayed Read Transaction from PCI to Internal bus PCI Controller PCI Master Device Internal Bus Block 1 4 2 3 5 6 As the issued burst size cannot be known until the transaction is completed the PCI Controller decides the prefetched word size based on the issued PCI command when Cache Line Size is valid When Memory Read command is used the prefetched word size is 1 word When Memory...

Page 380: ...rget block accepts this access and the PCI Controller read a word from it 5 The PCI Controller asserts TRDY_B and return the 1 word data to PCI master device Then the PCI Controller issues disconnect to PCI master device when it issues the burst transfer The PCI master device must terminates the transaction as soon as possible Figure 7 9 Non Delayed Read Transaction from PCI to Internal bus PCI Co...

Page 381: ...Parity Error Response bit in configuration register is set the PCI Controller asserts PERR signal and set Master Data Parity Error bit in configuration register However the PCI Controller does not terminate the current transfer and continues it 2 Received master abort as PCI master When the PCI Controller receives master abort on PCI bus as master the PCI Controller sets Received Master Abort bit ...

Page 382: ...ntroller stops the access and returns to the state in which the PCI Controller can accept a new access 7 2 4 Warning for Deadlocks The PCI Controller can use Non Delayed Read rule and Non Posted Write rule for each direction In these rules the PCI Controller does not release the bus until it completes the transaction on the other bus Therefore if the PCI Controller is set to use Non Delayed Read r...

Page 383: ... the power management state in which clock is suspended D3cold as the power management state in which clock is suspended and power is removed 7 3 2 Power management event The PCI Controller supports Power Management Events PME from D0 D1 and D3hot PME shows the event that issues the transition of the power state from device The PME is reported to an external PCI Host device by asserting PME_B The ...

Page 384: ...ip is used in if needed 7 When the VR4120A is ready for the transition the VR4120A writes a 1 to PMRDY bit in P_PPCR register 8 An external PCI Host device is able to know that the chip is ready by reading PMRDY bit The PCI Host device does not need to wait the completion of the preparation of the chip Therefore power and clock may be removed suddenly Figure 7 10 The Sequence of the Transition by ...

Page 385: ...SR register or writes a 0 to PME_En bit in PMCSR register in order to clear PME_B 4 The PCI Controller deasserts PME_B Hereafter as same case of the transition is issued by PCI Host Figure 7 11 The Sequence of the Transition by PME Sam e with the case that PCI Host requests the transition of the power state clear PME by writing 1 to PME_Status bit in PMCSR register or by making PME_En bit 0 in PMC...

Page 386: ...re two types of Configuration Cycle Type0 for PCI devices except for PCI bridges and Type1 for PCI bridges in PCI specification The PCI Controller can generate both types of Configuration Cycle When Type1 Configuration Cycle is generated the content to be set to P_PCAR register is as below Figure 7 12 The Content of P_PCAR Register for Type0 Configuration Cycle En 31 30 29 28 27 26 25 24 23 22 21 ...

Page 387: ...0 0000 0000 0000 0100 00011 0000 0000 0000 1000 00100 0000 0000 0001 0000 00101 0000 0000 0010 0000 00110 0000 0000 0100 0000 00111 0000 0000 1000 0000 01000 0000 0001 0000 0000 01001 0000 0010 0000 0000 01010 0000 0100 0000 0000 01011 0000 1000 0000 0000 01100 0001 0000 0000 0000 01101 0010 0000 0000 0000 01110 0100 0000 0000 0000 01111 1000 0000 0000 0000 1xxxx 0000 0000 0000 0000 The bits of AD...

Page 388: ...n there are less than 4 PCI master devices on PCI bus and this arbiter is used REQ_B pins that are not used should be pull up This internal arbiter has 2 modes for arbitration algorithm These modes can be selected by PARBM bit in P_HMCR register 7 4 2 1 Alternating mode PCI master devices except the PCI Controller are arbitrated as one group in this mode Priority alternates The PCI Controller with...

Page 389: ...l for PCI bus when PRSTO bit in P_HMCR register is set to a 1 In order to deassert the signal the VR4120A should reset PRSTO bit to a 0 7 4 4 Interrupt input The PCI Controller has an interrupt input port and the SERR_B input port so as to receive interrupts and SERR_B from PCI devices If any of PCI interrupts is asserted PINTR bit in P_IGSR register is set and the PCI Controller issues an interru...

Page 390: ..._404CH N A Reserved 1000_4050H P_BCNT R W R W W H B Bridge Control Register 1000_4054H P_PPCR R W R W H B Power Control Register 1000_4058H P_SWRR W W Software Reset Register 1000_405CH P_RTMR R W R W W H B Retry Timer register 1000_4060H 1000_40FCH N A Reserved 1000_4100H 1000_41FCH P_CONFIG See 7 5 19 See 7 5 19 W H B PCI Configuration Registers Remarks 1 In the R W field W means writeable R mea...

Page 391: ...s register contains internal bus base address When the access from PCI side to internal bus side comes the PCI Controller replaces the upper 10 bits of the address on PCI with the upper 10 bits of this register and issues as the address on internal bus R W Bits Field Internal bus PCI Default Description 31 0 IBBA R W upper 10 bits R lower 22 bits R W upper 10 bits R lower 22 bits 0 Internal bus ba...

Page 392: ...is set to a 0 reading from writing to PCDR does not generate Configuration Cycle 30 24 Reserved 0 Hardwired to 0 s 23 16 BUSNM R W R 0 Bus Number 15 11 DEVNM R W R 0 Device Number 10 8 FNCNM R W R 0 Function Number 7 2 REGAC R W R 0 Offset Address for each device 1 0 CYCTP R W R 00 Select Configuration Cycle Type 00 Configuration Type 0 01 Configuration Type 1 7 5 6 P_PCDR PCI Configuration Data R...

Page 393: ...20A should check PPCR register to know which state the PCI Controller moves to 7 SRREQ R R 0 Software Reset is issued 1 indicates that PCI Host issues Software Reset when PCI Host writes to SWRS register the VR4120A should be set SWRDN bit in PGSR register to a 1 after the completion of software reset 6 IRBER R R 0 Internal bus Error in read transaction 1 indicates that the PCI Controller has rece...

Page 394: ...ked 10 PSERI R W R W 0 Mask bit for the PCI SERR 0 means masked 1 means unmasked 9 PPERR R W R W 0 Mask bit for PCI Parity Error 0 means masked 1 means unmasked 8 PPREQ R W R W 0 Mask bit for the state transition for PPMI 0 means masked 1 means unmasked 7 SRREQ R W R W 0 Mask bit for the Software Reset issue 0 means masked 1 means unmasked 6 IRBER R W R W 0 Mask bit for internal bus Error in read ...

Page 395: ...he VR4120A should check PPCR register to know which state the PCI Controller moves to 7 SRREQ R R 0 Software Reset is issued 1 indicates that PCI Host issues Software Reset when PCI Host writes to SWRS register the VR4120A should be set SWRDN bit in PGSR register to a 1 after the completion of software reset 6 IRBER R R 0 Internal bus Error in read transaction 1 indicates that the PCI Controller h...

Page 396: ...es that the software reset has been done 8 DPERR R R 0 Detected PCI Parity Error 1 indicates that the PCI Controller has detected a parity error on PCI bus 7 SSERR R R 0 Signaled SERR 1 indicates that the PCI Controller has asserted SERR_B 6 RMABT R R 0 Received Master Abort 1 indicates that the PCI Controller has received Master Abort as master 5 RTABT R R 0 Received Target Abort 1 indicates that...

Page 397: ...he state transition for PPMI 0 means masked 1 means unmasked 9 SWRDN R W R W 0 Mask bit for Software Reset done 0 means masked 1 means unmasked 8 DPERR R W R W 0 Mask bit for Detected Parity Error 0 means masked 1 means unmasked 7 SSERR R W R W 0 Mask bit for Signaled SERR_B 0 means masked 1 means unmasked 6 RMABT R W R W 0 Mask bit for Received Master Abort 0 means masked 1 means unmasked 5 RTABT...

Page 398: ...he VR4120A should be set the value to this register as initialization The unit of data is 0 01Watts R W Bits Field Internal bus PCI Default Description 31 24 D3CSP R W R 00H D3 Power Consumption Data 23 16 Reserved 00H Hardwired to 00H 15 8 D1CSP R W R 00H D1 Power Consumption Data 7 0 D0CSP R W R 00H D0 Power Consumption Data 7 5 14 P_PDDR Power Dissipation Data Register This register is used to ...

Page 399: ...ual Address Cycle Enable Reserved for the future use The bit has to be set to 0 3 PDRTD R W R W 0 PCI Delayed Read Transaction Disable 1 disables the PCI Controller to generate Delayed Read Transaction on PCI bus PCI Read transactions are executed as None Delayed Read Transaction 2 PPWRD R W R W 0 PCI Posted Write Transaction Disable 1 disables the PCI Controller to generate Posted Write Transacti...

Page 400: ...ower state issued 1 indicates that PCI Host issues the transition to D0 state The VR4120A should write 1 to this bit in order to clear after the recognition that this bit is set 2 PMRQ1 R W R 0 The transition to D1 power state issued 1 indicates that PCI Host issues the transition to D1 state The VR4120A should write 1 to this bit in order to clear after the recognition that this bit is set 1 Rese...

Page 401: ...ote 31 24 23 16 15 8 7 0 1000_4100H Device ID Vendor ID 1000_4104H Status Command 1000_4108H Class Code Revision ID 1000_410CH Reserved Header Type Latency Timer Cache Line Size 1000_4110H Window Memory Base Address Register 1000_4114H Register Memory Base Address Register 1000_4118H Reserved 1000_411CH Reserved 1000_4120H Reserved 1000_4124H Reserved 1000_4128H Reserved 1000_412CH Subsystem ID Su...

Page 402: ...served 4 Reserved 1000_4120H Reserved 4 Reserved 1000_4124H Reserved 4 Reserved 1000_4128H Reserved 4 Reserved 1000_412CH Subsystem Vendor ID 2 R W R Subsystem Vendor ID 1000_412EH Subsystem ID 2 R W R Subsystem ID 1000_4130H Reserved 4 Reserved 1000_4134H Cap_Ptr 1 R R Capabilities Pointer 40H 1000_4135H Reserved 3 Reserved 1000_4138H Reserved 4 Reserved 1000_413CH Interrupt Line 1 R W R W Interr...

Page 403: ...r NEC is 1033H R W Bits Field Internal bus PCI Default Description 15 0 Vendor ID R R 1033H Hardwired to 1033H which means the Vendor ID of NEC 7 5 19 3 Device ID register This register identifies the particular device The manufacturer of the device allocates this identifier R W Bits Field Internal bus PCI Default Description 15 0 Device ID R R 00A7H Hardwired to 00A7H ...

Page 404: ... Parity Error status bit bit15 in the Status register if an error is detected but does not assert PERR_B and continues normal operation 5 VGA Palette Snoop Enable R R 0 Hardwired to a 0 because the PCI Controller does not have VGA function 4 Memory Write and Invalidate Enable R W R W 0 This is an enable bit for using the Memory Write and Invalidate command When this bit is set to a 1 the PCI Contr...

Page 405: ...rminated as master device 11 Signaled Target Abort R W R W 0 This bit is set to a 1 when the PCI Controller terminates a transaction with Target Abort as target device 10 9 DEVSEL_B timing R R 01 Hardwired to 01 because the PCI Controller asserts DEVSEL_B at medium speed 8 Master Data Parity Error R W R W 0 This bit is set when three conditions as the follows are met 1 The bus agent asserted PERR_...

Page 406: ... ATM controller should be returned as the class code of the µPD98502 Please change code on the Host driver side 7 5 19 8 Cache line size register This register specifies the system cache line size in units of words 32 bit length The value in this register is also used to determine whether to use Memory Read Memory Read Line Memory Read Multiple Memory Write and Invalidate commands for accessing me...

Page 407: ...in this register are writeable The lower 22 bits are hardwired to 0 in order to indicate that the area with 2 MB is required in the 32 bit Memory Space 7 5 19 12 Register memory base address register This register specifies the base address of the PCI Memory space for the registers R W Bits Field Internal bus PCI Default Description 31 0 Register Memory Base Address R W upper 20 bits R lower 12 bi...

Page 408: ...rst term of the new capabilities list 7 5 19 16 Interrupt line register The Interrupt Line register is used to communicate interrupt line routing information R W Bits Field Internal bus PCI Default Description 7 0 Interrupt Line R W R W 0 The value in this register shows the input of the system interrupt controller that the interrupt pin is connected 7 5 19 17 Interrupt pin register This register ...

Page 409: ... is the last item in the capabilities list for The PCI Controller 7 5 19 22 PMC register The Power Management Capabilities register provides information on the capabilities of the function related to power management R W Bits Field Internal bus PCI Default Description 15 11 PME_Support R W R 0 The VR4120A should set the bits of the power state in which the chip supports PME_B assertion 10 D2_Suppo...

Page 410: ...Consumed 1H D1 Power Consumed 3H D3 Power Consumed 4H D0 Power Dissipated 5H D1 Power Dissipated 7H D3 Power Dissipated Other values all 0 8 PME_En R R W 0 Set a 1 enables the function to assert PME_B When 0 PME assertion is disabled 7 2 Reserved R R 0 Hardwired to 0 1 0 PowerState R W R W 0 This field is used both to determine the current power state and to set the PCI Controller into a new power...

Page 411: ...d in PMCSR register in order to indicate that chip can be run Sets a 1 to PMRDY bit in P_PPCR register to indicate that the issue for the transition of power state is acceptable Sets a 1 to INITD bit in P_BCNT register in order to indicate that the Initialization of the PCI Controller has been completed 2 Initialization by PCI Host After the time INITD bit is set the PCI Controller can accepts the...

Page 412: ...or each blocks inside chip if it wants to reset the chip 5 Transition of Power State When PCI Host writes to PowerState field in PMCSR register to change the power state of the chip the PCI Controller resets PMRDY bit in P_PPCR register sets PPREQ bit in P_IGSR register and reports to the VR4120A by interrupt if not masked What transition is required is indicated by PMRQ0 bit PMRQ1 bit and PMRQ3 b...

Page 413: ...d the PCI Controller uses on Internal bus I O or memory by ICMDS bit in P_BCNT register Sets which the PCI Controller uses DAC on PCI bus or not by DACEN bit in P_BCNT register Sets data transfer mode by PDRTD bit PPWRD bit IDRTD bit IPWRD bit in P_BCNT register Sets 00 to PowerState field in PMCSR register in order to indicate that chip can be run Sets a 1 to INITD bit in P_BCNT register in order...

Page 414: ... EG IST ER DIVISOR LAT C H LS DIVISOR LAT C H M S LINE ST AT US R EG IST ER T R ANSM IT T ER HOLDING R EG IST ER M ODEM C ONT R OL R EG IST ER INT ERR UPT ENABLE R EG IST ER INT ERR UPT ID R EG IST ER FIFO C ONT R OL R EG IST ER T R ANSM IT T ER SHIFT R EG IST ER T R ANSM IT T ER T IM ING C ONT R OL R ECEIVER T IM ING C ONT R OL R ECEIVER SHIFT R EG IST ER R ECEIVER FIFO T R ANSM IT T ER FIFO INT ...

Page 415: ...egister 1000_0090H UARTMCR R W W H B UART Modem Control Register 1000_0094H UARTLSR R W W H B UART Line status Register 1000_0098H UARTMSR R W W H B UART Modem Status Register 1000_009CH UARTSCR R W W H B UART Scratch Register Remarks 1 In the R W field W means writeable R means readable RC means read cleared means not accessible 2 All internal registers are 32 bit word aligned registers 3 The bur...

Page 416: ...rrupt Mask Register S_IMR is a global enable for interrupt sources enabled by this register Bits Field R W Default Description 31 4 Reserved R W 0 Hardwired to 0 3 ERBMI R W 0 UART Modem status Interrupts 1 Enable Modem status change interrupt 0 Disable such interrupts Modem status changes are reported to UARTMSR 2 ERBLI R W 0 UART Line status Interrupts 1 Enable Line status error interrupt 0 Disa...

Page 417: ...75H 0 15335 3BE7H 1 23234 5AC2H 1 150 7680 1E00H 0 13750 35B6H 1 20833 5161H 1 300 3840 F00H 0 6875 1ADBH 1 10417 28B1H 1 600 1920 780H 0 3438 D6EH 1 5208 1458H 1 1200 920 398H 0 1719 6B7H 1 2604 A2CH 1 1800 640 280H 0 1146 47AH 1 1736 6C8H 1 2000 573 23DH 0 1031 407H 1 1562 61AH 1 2400 480 1E0H 0 859 35BH 1 1302 516H 1 3600 320 140H 0 573 23DH 1 868 364H 1 4800 240 F0H 0 430 1AEH 1 651 28BH 1 720...

Page 418: ... 7 6 UFIFOEN R 00 UART FIFO is enable read only Both bits set to 1 when the transmit receive FIFO is enabled in the UFIFOEN0 bit is set in the UARTFCR 5 4 Reserved R 00 Hardwired to 0 3 1 UIID R 000 Indicates the priority level of pending interrupt 011 1st Priority Receiver Line status Overrun Error Parity Framing Error or Break interrupt 010 2nd Priority Received data available Receiver Data Avai...

Page 419: ...le by the ERBFI bit in the UARTIER Number of bytes in Receive FIFO is following 00 1 byte 01 4 bytes 10 8 bytes 11 14 bytes 5 4 Reserved W 0 Hardwired to 0 3 FIFOMD W 0 Switch between 16550 mode and FIFO mode 1 From 16550 mode to FIFO mode 0 From FIFO mode to 16550 mode 2 UTFRST W 0 UART Transmitter FIFO Reset write only 1 clear transmit FIFO and reset counter 0 no clear 1 URFRST W 0 UART Receiver...

Page 420: ...4H When this bit is set UART accesses the UART Divisor Latch LSB Register UARTDLM at offset 84H When cleared the UART accesses the Receiver Data Buffer Register UARTRBR on reads at offset 80H the UARTTHR on writes at offset 80H and UARTIER on any accesses at offset 84H 6 USB R W 0 Send Break 1 force URSDO signal output Low 0 normal operation 5 USP R W 0 Stick parity 1 force URSDO signal output Low...

Page 421: ... 2 internal signal 1 OUT2_B internal state active 0 OUT2_B internal state inactive reset value This is a user defined bit that has no associated external signal Software can write to the bit but this has no effect 2 OUT1 R W 0 Out 1 internal signal 1 OUT1_B internal state active 0 OUT1_B internal state inactive reset value This is a user defined bit that has no associated external signal Software ...

Page 422: ... R W 1 Transmitter Holding Register Empty 1 transmitter holding register empty 0 transmitter holding register not empty Transmit data is stored in the UART Transmitter Data Holding Register UARTTHR 4 BI R W 0 Break Interrupt 1 break received on URSDI signal 0 no break 3 FE R W 0 Receive Data Framing Error 1 framing error on receive data 0 no such error 2 PE R W 0 Receive Data Parity Error 1 parity...

Page 423: ... UARTMCR 4 CTS R W 0 Clear To Send 1 URCTS_B state active 0 URCTS_B state inactive This bit is the complement of the URCTS_B input signal If the LOOP bit in the UART Modem Control Register UARTMCR is set to 1 the CTS bit is equivalent to the RTS bit in the UARTMCR 3 DDCD R W 0 Delta Data Carrier Detect 1 URDCD_B state changed since this register was last read 0 no such change 2 TERI R W 0 Trailing...

Page 424: ...isters TM0CSR or TM1CSR have different offset from the read register so write registers are not affected while a value is read from the read registers TM0CCR TM1CCR which indicate a running count of the timer counter at a given time Once a value is loaded in the TM0CSR TM1CSR it stays there until Timer s interrupts are cleared in the Interrupt Status Register S_ISR The original value can be reload...

Page 425: ... on SysCMD 0 is returned 5 Write access to the reserved area will set the CBERR bit in the NSR register and the write data is lost 6 In the Access filed W means that word access is valid H means that half word access is valid B means that byte access is valid 7 Write access to the read only register cause no error but the write data is lost 8 The CPU can access all internal registers but IBUS mast...

Page 426: ...hes 0000_0000H it generates an interrupt to the CPU via Interrupt Status Register ISR if the TM1IS in ISR is not masked by TM1IM in IMR TM1CSR is initialized to 0 at reset and contains the following field Bits Field R W Default Description 31 0 TM1SET R W 0 Initial and Reload Value for Timer CH1 9 3 5 TM0CCR Timer CH0 Current Count Register The Timer CH0 Current Count Register TM0CCR is read only ...

Page 427: ...0 and stores the data in the EDAT field After issuing the command the VR4120A checks that the MSB bit of the ERDR register is set to 0 then obtains the data To write data into or erase data from the EEPROM the VR4120A must enable write and erase operations using the EWEN command in advance When no EEPROM is connected accessing these registers is meaningless This Micro Wire interface has also auto ...

Page 428: ...CAR3 15 0 06H MAC2 Address data 47 32 MACAR3 31 16 10 2 2 Accessing to EEPROM Access to EEPROM starts by writing to the ECCR EEPROM Command Control Register Write command 3 bits and address 6 bits of EEPROM into lower 9 bits of ECCR There is a difference between write command and read command 1 Write command Write data into upper 16 bits of ECCR 2 Read command Data is loaded into lower 16bits of E...

Page 429: ...EEPROM No meaning in case of data read 15 9 Reserved W 0 Reserved 8 6 CMD W 0 Serial EEPROM command 5 0 ADDRESS W 0 Serial EEPROM address 10 3 3 ERDR EEPROM Read Data Register Bits Field R W Default Description 31 B R 1 Operation status of Micro Wire block 1 busy 0 idle 30 16 Reserved R 0 Reserved 15 0 READ DATA R 0 Read data from Serial EEPROM 10 3 4 MACAR1 MAC Address Register 1 Bits Field R W D...

Page 430: ...Preliminary User s Manual S15543EJ1V0UM 10 3 6 MACAR3 MAC Address Register 3 Bits Field R W Default Description 31 16 SERIAL EEPROM 06H ADDRESS R 0 Stored Serial EEPROM data of address 05H 06H 15 0 SERIAL EEPROM 05H ADDRESS R 0 ...

Page 431: ...s For example we use base instead of rs in the format for load and store instructions Such an alias is always lower case since it refers to a variable subfield Figures with the actual bit encoding for all the mnemonics are located at the end of this chapter A 6 CPU Instruction Opcode Bit Encoding and the bit encoding also accompanies each instruction In the instruction descriptions that follow the...

Page 432: ...oadMemory and StoreMemory and the endianness of Kernel and Supervisor mode execution However this value is always 0 since the VR4120A CPU supports the little endian order only ReverseEndian Signal to reverse the endianness of load and store instructions This feature is available in User mode only and is effected by setting the RE bit of the Status register Thus ReverseEndian may be computed as SR2...

Page 433: ...le A 2 Load and Store Common Functions Function Description AddressTranslation Uses the TLB to find the physical address given the virtual address The function fails and an exception is taken if the required translation is not present in the TLB LoadMemory Uses the cache and main memory to find the contents of the word containing the specified physical address The low order three bits of the addre...

Page 434: ...following a jump or branch that is occupying the delay slot is always executed while the target instruction is being fetched from storage A delay slot may not itself be occupied by a jump or branch instruction however this error is not detected and the results of such an operation are undefined If an exception or interrupt prevents the completion of a legal instruction during a delay slot the hard...

Page 435: ...exception handling and memory management Therefore the move to from coprocessor instructions are the only valid mechanism for writing to and reading from the CP0 registers Several CP0 instructions are defined to directly read write and probe TLB entries and to modify the operating modes in preparation for returning to User mode or interrupt enabled states A 5 CPU Instruction This section describes...

Page 436: ...ntents of general register rt are added to form the result The result is placed into general register rd In 64 bit mode the operands must be valid sign extended 32 bit values An overflow exception occurs if the carries out of bits 30 and 31 differ 2 s complement overflow The destination register rd is not modified when an integer overflow exception occurs Operation 32 T GPR rd GPR rs GPR rt 64 T t...

Page 437: ... register rs to form the result The result is placed into general register rt In 64 bit mode the operand must be valid sign extended 32 bit values An overflow exception occurs if carries out of bits 30 and 31 differ 2 s complement overflow The destination register rt is not modified when an integer overflow exception occurs Operation 32 T GPR rt GPR rs immediate15 16 immediate15 0 64 T temp GPR rs...

Page 438: ...s of general register rs to form the result The result is placed into general register rt No integer overflow exception occurs under any circumstances In 64 bit mode the operand must be valid sign extended 32 bit values The only difference between this instruction and the ADDI instruction is that ADDIU never causes an integer overflow exception Operation 32 T GPR rt GPR rs immediate 15 16 immediat...

Page 439: ...er rs and the contents of general register rt are added to form the result The result is placed into general register rd No integer overflow exception occurs under any circumstances In 64 bit mode the operands must be valid sign extended 32 bit values The only difference between this instruction and the ADD instruction is that ADDU never causes an integer overflow exception Operation 32 T GPR rd G...

Page 440: ...1 0 0 1 0 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format AND rd rs rt Description The contents of general register rs are combined with the contents of general register rt in a bit wise logical AND operation The result is placed into general register rd Operation 32 T GPR rd GPR rs and GPR rt 64 T GPR rd GPR rs and GPR rt Exceptions None ...

Page 441: ... 25 21 20 16 15 0 6 5 5 16 Format ANDI rt rs immediate Description The 16 bit immediate is zero extended and combined with the contents of general register rs in a bit wise logical AND operation The result is placed into general register rt Operation 32 T GPR rt 0 16 immediate and GPR rs 15 0 64 T GPR rt 0 48 immediate and GPR rs 15 0 Exceptions None ...

Page 442: ...s to the target address with a delay of one instruction Because the condition line is sampled during the previous instruction there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line Operation 32 T 1 condition not SR18 T target offset15 14 offset 0 2 T 1 if condition then PC PC target endif 64 T 1 condition not SR18 T target offs...

Page 443: ...get address is branched to with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Because the condition line is sampled during the previous instruction there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line Operation 32 T 1 condition not SR18 T target offset1...

Page 444: ...Preliminary User s Manual S15543EJ1V0UM BC0FL Branch On Coprocessor 0 False Likely 2 2 BC0FL Opcode Table 31 0 30 1 29 0 28 0 27 0 26 0 25 0 24 1 23 0 22 0 21 0 20 0 19 0 18 0 17 1 16 0 0 BC0FL Opcode Coprocessor number BC sub opcode Branch condition ...

Page 445: ...address with a delay of one instruction Because the condition line is sampled during the previous instruction there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line Operation 32 T 1 condition SR18 T target offset15 14 offset 02 T 1 if condition then PC PC target endif 64 T 1 condition SR18 T target offset15 46 offset 0 2 T 1 if...

Page 446: ...target address is branched to with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Because the condition line is sampled during the previous instruction there must be at least one instruction between this instruction and a coprocessor instruction that changes the condition line Operation 32 T 1 condition SR18 T target offset15...

Page 447: ...iminary User s Manual S15543EJ1V0UM 447 BC0TL Branch On Coprocessor 0 True Likely 2 2 BC0TL Opcode Table 31 0 30 1 29 0 28 0 27 0 26 0 25 0 24 1 23 0 22 0 21 0 20 0 19 0 18 0 17 1 16 1 0 BC0TL Opcode Coprocessor number BC sub opcode Branch condition ...

Page 448: ... delay slot and the 16 bit offset shifted left two bits and sign extended The contents of general register rs and the contents of general register rt are compared If the two registers are equal then the program branches to the target address with a delay of one instruction Operation 32 T target offset15 14 offset 0 2 condition GPR rs GPR rt T 1 if condition then PC PC target endif 64 T target offs...

Page 449: ...extended The contents of general register rs and the contents of general register rt are compared If the two registers are equal the target address is branched to with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Operation 32 T target offset15 14 offset 0 2 condition GPR rs GPR rt T 1 if condition then PC PC target else Nul...

Page 450: ... of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the contents of general register rs are zero or greater when compared to zero then the program branches to the target address with a delay of one instruction Operation 32 T target offset15 14 offset 0 2 condition GPR rs 31 0 T 1 if condition then PC PC target endif 64 T target offs...

Page 451: ...address of the instruction after the delay slot is placed in the link register r31 If the contents of general register rs are zero or greater when compared to zero then the program branches to the target address with a delay of one instruction General register rs may not be general register r31 because such an instruction is not restartable An attempt to execute this instruction is not trapped how...

Page 452: ...r r31 If the contents of general register rs are zero or greater when compared to zero then the program branches to the target address with a delay of one instruction General register r31 should not be specified as general register rs If register r31 is specified restarting may be impossible due to the destruction of rs contents caused by storing a link address Even such instructions are executed ...

Page 453: ...et shifted left two bits and sign extended If the contents of general register rs are zero or greater when compared to zero then the program branches to the target address with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Operation 32 T target offset15 14 offset 0 2 condition GPR rs 31 0 T 1 if condition then PC PC target e...

Page 454: ...nstruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the contents of general register rs are zero or greater when compared to zero then the program branches to the target address with a delay of one instruction Operation 32 T target offset15 14 offset 0 2 condition GPR rs 31 0 and GPR rs 0 32 T 1 if condition then PC PC target endif 64 T target offset15 46 ...

Page 455: ...The contents of general register rs are compared to zero If the contents of general register rs are greater than zero then the program branches to the target address with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Operation 32 T target offset15 14 offset 0 2 condition GPR rs 31 0 and GPR rs 0 32 T 1 if condition then PC P...

Page 456: ... delay slot and the 16 bit offset shifted left two bits and sign extended The contents of general register rs are compared to zero If the contents of general register rs are zero or smaller than zero then the program branches to the target address with a delay of one instruction Operation 32 T target offset15 14 offset 0 2 condition GPR rs 31 1 or GPR rs 0 32 T 1 if condition then PC PC target end...

Page 457: ...d The contents of general register rs is compared to zero If the contents of general register rs are zero or smaller than zero then the program branches to the target address with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Operation 32 T target offset15 14 offset 0 2 condition GPR rs 31 1 or GPR rs 0 32 T 1 if condition t...

Page 458: ...sum of the address of the instruction in the delay slot and the 16 bit offset shifted left two bits and sign extended If the contents of general register rs are smaller than zero then the program branches to the target address with a delay of one instruction Operation 32 T target offset15 14 offset 0 2 condition GPR rs 31 1 T 1 if condition then PC PC target endif 64 T target offset15 46 offset 0 ...

Page 459: ...n the link register r31 If the contents of general register rs are smaller than zero when compared to zero then the program branches to the target address with a delay of one instruction General register r31 should not be specified as general register rs If register r31 is specified restarting may be impossible due to the destruction of rs contents caused by storing a link address Even such instru...

Page 460: ... the contents of general register rs are smaller than zero when compared to zero then the program branches to the target address with a delay of one instruction General register r31 should not be specified as general register rs If register r31 is specified restarting may be impossible due to the destruction of rs contents caused by storing a link address Even such instructions are executed an exc...

Page 461: ...d left two bits and sign extended If the contents of general register rs are smaller than zero when compared to zero then the program branches to the target address with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Operation 32 T target offset15 14 offset 0 2 condition GPR rs 31 1 T 1 if condition then PC PC target else Nul...

Page 462: ... delay slot and the 16 bit offset shifted left two bits and sign extended The contents of general register rs and the contents of general register rt are compared If the two registers are not equal then the program branches to the target address with a delay of one instruction Operation 32 T target offset15 14 offset 0 2 condition GPR rs GPR rt T 1 if condition then PC PC target endif 64 T target ...

Page 463: ...d The contents of general register rs and the contents of general register rt are compared If the two registers are not equal then the program branches to the target address with a delay of one instruction If the conditional branch is not taken the instruction in the branch delay slot is nullified Operation 32 T target offset15 14 offset 0 2 condition GPR rs GPR rt T 1 if condition then PC PC targ...

Page 464: ...6 Format BREAK Description A breakpoint trap occurs immediately and unconditionally transferring control to the exception handler The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Operation 32 64 T BreakpointException Exceptions Breakpoint exception ...

Page 465: ...e combination not listed below or on a secondary cache that is not incorporated in VR4120A CPU is undefined The operation of this instruction on uncached addresses is also undefined The Index operation uses part of the virtual address to specify a cache block For a primary cache of 2 CACHEBITS bytes with 2 LINEBITS bytes per tag vAddrCACHEBITS LINEBITS specifies the block Index_Load_Tag also uses ...

Page 466: ...ions Note for addresses in the unmapped areas unmapped addresses may be used to avoid TLB exceptions Index operations never cause a TLB Modified exception Bits 17 and 16 of the instruction code specify the cache for which the operation is to be performed as follows Code Name Cache 0 I Instruction cache 1 D Data cache 2 Reserved 3 Reserved Note Physical addresses here are used to index the cache an...

Page 467: ... registers 3 D Create_Dirty_ Exclusive This operation is used to avoid loading data needlessly from memory when writing new contents into an entire cache block If the cache block does not contain the specified address and the block is dirty write it back to the memory In all cases set the cache state to Dirty 4 I D Hit_Invalidate If the cache block contains the specified address mark the cache blo...

Page 468: ...HE Cache 4 4 CACHE Operation 32 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA CacheOp op vAddr pAddr Exceptions Coprocessor unusable exception TLB Refill exception TLB Invalid exception Bus Error exception Address Error exception Cache Error exception ...

Page 469: ...he result The result is placed into general register rd An overflow exception occurs if the carries out of bits 62 and 63 differ 2 s complement overflow The destination register rd is not modified when an integer overflow exception occurs This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction e...

Page 470: ...ult is placed into general register rt An overflow exception occurs if carries out of bits 62 and 63 differ 2 s complement overflow The destination register rt is not modified when an integer overflow exception occurs This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64...

Page 471: ... immediate is sign extended and added to the contents of general register rs to form the result The result is placed into general register rt No integer overflow exception occurs under any circumstances The only difference between this instruction and the DADDI instruction is that DADDIU never causes an overflow exception Operation 64 T GPR rt GPR rs immediate15 48 immediate15 0 Exceptions Reserve...

Page 472: ...rt Description The contents of general register rs and the contents of general register rt are added to form the result The result is placed into general register rd No overflow exception occurs under any circumstances The only difference between this instruction and the DADD instruction is that DADDU never causes an overflow exception Operation 64 T GPR rd GPR rs GPR rt Exceptions Reserved instru...

Page 473: ... for a zero divisor and for overflow When the operation completes the quotient word of the double result is loaded into special register LO and the remainder word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of those instructions are undefined Correct operation requires separating reads of HI or LO from writes by tw...

Page 474: ...a zero divisor inserted by the programmer When the operation completes the quotient word of the double result is loaded into special register LO and the remainder word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of those instructions are undefined Correct operation requires separating reads of HI or LO from writes ...

Page 475: ...ction is typically followed by additional instructions to check for a zero divisor and for overflow When the operation completes the quotient word of the double result is loaded into special register LO and the remainder word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of those instructions are undefined Correct op...

Page 476: ...s instruction is typically followed by additional instructions to check for a zero divisor When the operation completes the quotient word of the double result is loaded into special register LO and the remainder word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of those instructions are undefined Correct operation r...

Page 477: ...nds are set as us 1 DMACCUS instruction the contents are handled as 16 bit unsigned data If they are set as us 0 DMACCS instruction the contents are handled as 16 bit signed integers Sign zero expansion by software is required for any bits exceeding 16 bits in the operands The product of this multiply operation is added to the value in the LO special register If us 1 this add operation handles the...

Page 478: ... the same as the data loaded to the HI special register is also loaded to the rd general register When hi 0 data that is the same as the data loaded to the LO special register is also loaded to the rd general register Overflow exceptions do not occur These operations are defined for 64 bit mode and 32 bit kernel mode A reserved instruction exception occurs if one of these instructions is executed ...

Page 479: ...emp1 LO LO temp2 GPR rd LO 64 sat 0 us 1 DMACCU instruction T temp1 0 32 GPR rs 0 32 GPR rt temp2 temp1 LO LO temp2 GPR rd LO 64 sat 1 us 0 DMACCS instruction T temp1 GPR rs 31 32 GPR rs GPR rt 31 32 GPR rt temp2 saturation temp1 LO LO temp2 GPR rd LO 64 sat 1 us 1 DMACCUS instruction T temp1 0 32 GPR rs 0 32 GPR rt temp2 saturation temp1 LO LO temp2 GPR rd LO Exceptions Reserved instruction excep...

Page 480: ...ral register rt This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception All 64 bits of the general register destination are written from the coprocessor register source The operation of DMFC0 on a 32 bit coprocessor 0 register is undefined Operation 64 T data CPR 0 rd T 1 GPR rt data E...

Page 481: ... bit user or supervisor mode causes a reserved instruction exception All 64 bits of the coprocessor 0 register are written from the general register source The operation of DMTC0 on a 32 bit coprocessor 0 register is undefined Because the state of the virtual address translation system may be altered by this instruction the operation of load instructions store instructions and TLB operations immed...

Page 482: ...ult is loaded into special register LO and the high order word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of these instructions are undefined Correct operation requires separating reads of HI or LO from writes by a minimum of two other instructions This operation is defined in 64 bit mode or in 32 bit kernel mode ...

Page 483: ...of the double result is loaded into special register LO and the high order word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of these instructions are undefined Correct operation requires separating reads of HI or LO from writes by a minimum of two instructions This operation is defined in 64 bit mode or in 32 bit k...

Page 484: ...rt sa Description The contents of general register rt are shifted left by sa bits inserting zeros into the low order bits The result is placed in register rd This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T s 0 sa GPR rd GPR rt 63 s 0 0s Exceptions Reserved instru...

Page 485: ...eral register rt are shifted left by the number of bits specified by the low order six bits contained in general register rs inserting zeros into the low order bits The result is placed in register rd This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T s GPR rs 5 0 G...

Page 486: ... rd rt sa Description The contents of general register rt are shifted left by 32 sa bits inserting zeros into the low order bits The result is placed in register rd This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T s 1 sa GPR rd GPR rt 63 s 0 0s Exceptions Reserved...

Page 487: ...rt sa Description The contents of general register rt are shifted right by sa bits sign extending the high order bits The result is placed in register rd This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T s 0 sa GPR rd GPR rt 63 s GPR rt 63 s Exceptions Reserved ins...

Page 488: ...of general register rt are shifted right by the number of bits specified by the low order six bits of general register rs sign extending the high order bits The result is placed in register rd This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T s GPR rs 5 0 GPR rd GP...

Page 489: ... rd rt sa Description The contents of general register rt are shifted right by 32 sa bits sign extending the high order bits The result is placed in register rd This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T s 1 sa GPR rd GPR rt 63 s GPR rt 63 s Exceptions Reser...

Page 490: ...rt sa Description The contents of general register rt are shifted right by sa bits inserting zeros into the high order bits The result is placed in register rd This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T s 0 sa GPR rd 0 s GPR rt 63 s Exceptions Reserved instr...

Page 491: ...f general register rt are shifted right by the number of bits specified by the low order six bits of general register rs inserting zeros into the high order bits The result is placed in register rd This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T s GPR rs 5 0 GPR ...

Page 492: ... rd rt sa Description The contents of general register rt are shifted right by 32 sa bits inserting zeros into the high order bits The result is placed in register rd This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T s 1 sa GPR rd 0 s GPR rt 63 s Exceptions Reserve...

Page 493: ... result The result is placed into general register rd An integer overflow exception takes place if the carries out of bits 62 and 63 differ 2 s complement overflow The destination register rd is not modified when an integer overflow exception occurs This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved in...

Page 494: ... of general register rs to form a result The result is placed into general register rd The only difference between this instruction and the DSUB instruction is that DSUBU never traps on overflow No integer overflow exception occurs under any circumstances This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reser...

Page 495: ...p SR2 1 then load the PC from the ErrorEPC register and clear the ERL bit of the Status register SR2 Otherwise SR2 0 load the PC from the EPC register and clear the EXL bit of the Status register SR1 0 When a MIPS16 instruction can be executed the value of clearing the least significant bit of the EPC or error EPC register to 0 is loaded to PC This means the content of the least significant bit is...

Page 496: ...ription HIBERNATE instruction starts mode transition from Fullspeed mode to Hibernate mode When the HIBERNATE instruction finishes the WB stage the processor wait by the SysAD bus is idle state after then the internal clocks and the system interface clocks will shut down thus freezing the pipeline Cold Reset causes the Hibernate mode to the Fullspeed mode transition Operation 32 64 T T 1 Hibernate...

Page 497: ...target Description The 26 bit target address is shifted left two bits and combined with the high order four bits of the address of the delay slot The program unconditionally jumps to this calculated address with a delay of one instruction Operation 32 T temp target T 1 PC PC31 28 temp 02 64 T temp target T 1 PC PC63 28 temp 02 Exceptions None ...

Page 498: ... with a delay of one instruction The address of the instruction after the delay slot is placed in the link register r31 The address of the instruction immediately after a delay slot is placed in the link register r31 When a MIPS16 instruction can be executed the value of bit 0 of r31 indicates the ISA mode bit before jump Operation 32 T temp target If MIPS16En 1 then GPR 31 PC 8 31 1 ISA MODE else...

Page 499: ...lt value of rd if omitted in the assembly language instruction is 31 When a MIPS16 instruction can be executed the value of bit 0 of rd indicates the ISA mode bit before jump Register specifiers rs and rd may not be equal because such an instruction does not have the same effect when re executed Because storing a link address destroys the contents of rs if they are equal However an attempt to exec...

Page 500: ...nconditionally jumps to the target address with a delay of one instruction The address of the instruction that follows the delay slot is stored to the link register r31 The ISA mode bit is inverted with a delay of one instruction The value of bit 0 of the link register r31 indicates the ISA mode bit before jump Operation 32 T temp target GPR 31 PC 8 31 1 ISA MODE T 1 PC PC31 28 temp 0 2 64 T temp ...

Page 501: ...address indicated by the value of clearing the least significant bit of the general register rs to 0 Then the content of the least significant bit of the general register rs is set to the ISA mode bit internal Since 32 bit length instructions must be word aligned a JR instruction must specify a target register rs that contains an address whose two low order bits are zero when a MIPS16 instruction ...

Page 502: ...eral register rt Operation 32 T vAddr offset15 16 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian3 mem LoadMemory uncached BYTE pAddr vAddr DATA byte vAddr2 0 xor BigEndianCPU3 GPR rt mem7 8 byte 24 mem7 8 byte 8 byte 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0...

Page 503: ... loaded into general register rt Operation 32 T vAddr offset15 16 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian3 mem LoadMemory uncached BYTE pAddr vAddr DATA byte vAddr2 0 xor BigEndianCPU3 GPR rt 0 24 mem7 8 byte 8 byte 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pA...

Page 504: ...to general register rt If any of the three least significant bits of the effective address are non zero an address error exception occurs This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr...

Page 505: ...rd The LDL instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address that can specify an arbitrary byte It reads bytes only from the doubleword in memory that contains the specified starting byte From one to eight bytes will be loaded depending on the starting byte specified Conceptually it starts at the specified byte in memory and loads t...

Page 506: ...fies register rt No address error exceptions due to alignment are possible This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian3 if BigEn...

Page 507: ...LEM 0 1 2 3 4 5 6 7 P B C D E F GH O P C D E F GH N OP D E F GH M NO P E F GH L MNOP F GH K L MNOP GH J K L MNO P H I J K L MNOP 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Remark LEM Little endian memory BigEndianMem 0 Type AccessType see Table 2 3 Byte Specification Related to Load and Store Instructions sent to memory Offset pAddr2 0 sent to memory Exceptions TLB refill exception TLB invalid exception Bus ...

Page 508: ... 16 bit offset to the contents of general register base to form a virtual address that can specify an arbitrary byte It reads bytes only from the doubleword in memory that contains the specified starting byte From one to eight bytes will be loaded depending on the starting byte specified Conceptually it starts at the specified byte in memory and loads that byte into the low order right most byte o...

Page 509: ...egister rt No address error exceptions due to alignment are possible This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian3 if BigEndianMe...

Page 510: ...1 2 3 4 5 6 7 I J K L MNOP A I J K L MNO A B I J K L MN A B C I J K L M A B C D I J K L A B C D E I J K A B C D E F I J A B C D E F G I 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 Remark LEM Little endian memory BigEndianMem 0 Type AccessType see Table 2 3 Byte Specification Related to Load and Store Instructions sent to memory Offset pAddr2 0 sent to memory Exceptions TLB refill exception TLB invalid excepti...

Page 511: ...ective address is non zero an address error exception occurs Operation 32 T vAddr offset15 16 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian2 0 mem LoadMemory uncached HALFWORD pAddr vAddr DATA byte vAddr2 0 xor BigEndianCPU2 0 GPR rt mem15 8 byte 16 mem15 8 byte 8 byte 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached Addre...

Page 512: ...nt bit of the effective address is non zero an address error exception occurs Operation 32 T vAddr offset15 16 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian2 0 mem LoadMemory uncached HALFWORD pAddr vAddr DATA byte vAddr2 0 xor BigEndianCPU2 0 GPR rt 0 16 mem15 8 byte 8 byte 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached...

Page 513: ... immediate 31 26 25 21 20 16 15 0 6 5 5 16 Format LUI rt immediate Description The 16 bit immediate is shifted left 16 bits and concatenated to 16 bits of zeros The result is placed into general register rt In 64 bit mode the loaded word is sign extended Operation 32 T GPR rt immediate 0 16 64 T GPR rt immediate15 32 immediate 016 Exceptions None ...

Page 514: ...st significant bits of the effective address is non zero an address error exception occurs Operation 32 T vAddr offset15 16 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian 02 mem LoadMemory uncached WORD pAddr vAddr DATA byte vAddr2 0 xor BigEndianCPU 02 GPR rt mem31 8 byte 8 byte 64 T vAddr offset15 48 offset15 0 GPR base pAddr unca...

Page 515: ...L instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address that can specify an arbitrary byte It reads bytes only from the word in memory that contains the specified starting byte From one to four bytes will be loaded depending on the starting byte specified In 64 bit mode the loaded word is sign extended Conceptually it starts at the spec...

Page 516: ...r uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian3 if BigEndianMem 0 then pAddr pAddrPSIZE 1 2 02 endif byte vAddr1 0 xor BigEndianCPU2 word vAddr2 xor BigEndianCPU mem LoadMemory uncached byte pAddr vAddr DATA temp mem32 word 8 byte 7 32 word GPR rt 23 8 byte 0 GPR rt temp 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DAT...

Page 517: ...ffset LEM 0 1 2 3 4 5 6 7 S S S S P F GH S S S S OP GH S S S S NO P H S S S SMNOP S S S S L F GH S S S S K L GH S S S S J K L H S S S S I J K L 0 1 2 3 0 1 2 3 0 0 0 0 4 4 4 4 Remark LEM Little endian memory BigEndianMem 0 Type AccessType see Table 2 3 Byte Specification Related to Load and Store Instructions sent to memory Offset pAddr2 0 sent to memory S sign extend of destination bit 31 Excepti...

Page 518: ...WR instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address that can specify an arbitrary byte It reads bytes only from the word in memory that contains the specified starting byte From one to four bytes will be loaded depending on the starting byte specified In 64 bit mode the loaded word is sign extended Conceptually it starts at the spe...

Page 519: ...ncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian3 if BigEndianMem 1 then pAddr pAddrPSIZE 1 3 03 endif byte vAddr1 0 xor BigEndianCPU2 word vAddr2 xor BigEndianCPU mem LoadMemory uncached 0 byte pAddr vAddr DATA temp GPR rt 31 32 8 byte mem31 32 word 32 word 8 byte GPR rt temp 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DA...

Page 520: ...et LEM 0 1 2 3 4 5 6 7 S S S SMNOP S S S S EMNO S S S S E F MN S S S S E F GM S S S S I J K L S S S S E I J K S S S S E F I J S S S S E F G I 3 2 1 0 3 2 1 0 0 1 2 3 4 5 6 7 Remark LEM Little endian memory BigEndianMem 0 Type AccessType see Table 2 3 Byte Specification Related to Load and Store Instructions sent to memory Offset pAddr2 0 sent to memory S sign extend of destination31 Exceptions TLB...

Page 521: ...ed in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 32 T vAddr offset15 16 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian 02 mem LoadMemory uncached WORD pAddr vAddr DATA byte vAddr2 0 xor BigEndianCPU 02 GPR rt 0 32 mem31 8 byte...

Page 522: ... MACCUS MACCHIUS instructions the contents are handled as 16 bit unsigned data If they are set as us 0 MACCS MACCHIS instructions the contents are handled as 16 bit signed integers Sign zero expansion by software is required for any bits exceeding 16 bits in the operands The product of this multiply operation is added to a 64 bit value of which only the low order 32 bits are valid that is linked t...

Page 523: ...add operation is loaded to the LO special register and the high order word is loaded to the HI special register When hi 1 MACCHI MACCHIU instructions data that is the same as the data loaded to the HI special register is also loaded to the rd general register When hi 0 MACC MACCU instructions data that is the same as the data loaded to the LO special register is also loaded to the rd general regis...

Page 524: ... LO temp263 32 HI temp231 0 GPR rd LO 32 sat 0 hi 1 us 0 MACCHI instruction T temp1 GPR rs GPR rt temp2 temp1 HI LO LO temp263 32 HI temp231 0 GPR rd HI 32 sat 0 hi 1 us 1 MACCHIU instruction T temp1 0 GPR rs 0 GPR rt temp2 temp1 0 HI 0 LO LO temp263 32 HI temp231 0 GPR rd HI 32 sat 1 hi 0 us 0 MACCS instruction T temp1 GPR rs GPR rt temp2 saturation temp1 HI LO LO temp263 32 HI temp231 0 GPR rd L...

Page 525: ...uction T temp1 GPR rs 31 32 GPR rs GPR rt 31 32 GPR rt temp2 temp1 HI31 0 LO31 0 LO temp263 32 temp263 32 HI temp231 32 temp231 0 GPR rd LO 64 sat 0 hi 0 us 1 MACCU instruction T temp1 0 32 GPR rs 0 32 GPR rt temp2 temp1 HI31 0 LO31 0 LO temp263 32 temp263 32 HI temp231 32 temp231 0 GPR rd LO 64 sat 0 hi 1 us 0 MACCHI instruction T temp1 GPR rs 31 32 GPR rs GPR rt 31 32 GPR rt temp2 temp1 HI31 0 L...

Page 526: ...0 us 1 MACCUS instruction T temp1 0 32 GPR rs 0 32 GPR rt temp2 saturation temp1 HI31 0 LO31 0 LO temp263 32 temp263 32 HI temp231 32 temp231 0 GPR rd LO 64 sat 1 hi 1 us 0 MACCHIS instruction T temp1 GPR rs 31 32 GPR rs GPR rt 31 32 GPR rt temp2 saturation temp1 HI31 0 LO31 0 LO temp263 32 temp263 32 HI temp231 32 temp231 0 GPR rd HI 64 sat 1 hi 1 us 1 MACCHIUS instruction T temp1 0 32 GPR rs 0 3...

Page 527: ... 0 0 0 0 0 0 0 0 0 31 26 25 21 20 16 15 0 6 5 5 5 11 10 11 rd Format MFC0 rt rd Description The contents of coprocessor register rd of the CP0 are loaded into general register rt Operation 32 T data CPR 0 rd T 1 GPR rt data 64 T data CPR 0 rd T 1 GPR rt data31 32 data31 0 Exceptions Coprocessor unusable exception in 64 bit 32 bit user and supervisor mode if CP0 not enabled ...

Page 528: ... 0 0 0 MFHI 0 1 0 0 0 0 5 6 5 Format MFHI rd Description The contents of special register HI are loaded into general register rd To ensure proper operation in the event of interruptions the two instructions which follow a MFHI instruction may not be any of the instructions which modify the HI register MULT MULTU DIV DIVU MTHI DMULT DMULTU DDIV DDIVU Operation 32 64 T GPR rd HI Exceptions None ...

Page 529: ... 0 0 0 MFLO 0 1 0 0 1 0 5 6 5 Format MFLO rd Description The contents of special register LO are loaded into general register rd To ensure proper operation in the event of interruptions the two instructions which follow a MFLO instruction may not be any of the instructions which modify the LO register MULT MULTU DIV DIVU MTLO DMULT DMULTU DDIV DDIVU Operation 32 64 T GPR rd LO Exceptions None ...

Page 530: ...tate of the virtual address translation system may be altered by this instruction the operation of load instructions store instructions and TLB operations immediately prior to and after this instruction are undefined When using a register used by the MTC0 by means of instructions before and after it refer to APPENDIX B VR4120A COPROCESSOR 0 HAZARDS and place the instructions in the appropriate loc...

Page 531: ...5 21 20 6 5 0 6 5 6 15 MTHI Format MTHI rs Description The contents of general register rs are loaded into special register HI If a MTHI operation is executed following a MULT MULTU DIV or DIVU instruction but before any MFLO MFHI MTLO or MTHI instructions the contents of special register HI are undefined Operation 32 64 T 2 HI undefined T 1 HI undefined T HI GPR rs Exceptions None ...

Page 532: ... 26 25 21 20 6 5 0 6 5 6 15 Format MTLO rs Description The contents of general register rs are loaded into special register LO If an MTLO operation is executed following a MULT MULTU DIV or DIVU instruction but before any MFLO MFHI MTLO or MTHI instructions the contents of special register LO are undefined Operation 32 64 T 2 LO undefined T 1 LO undefined T LO GPR rs Exceptions None ...

Page 533: ...extended values When the operation completes the low order word of the double result is loaded into special register LO and the high order word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of these instructions are undefined Correct operation requires separating reads of HI or LO from writes by a minimum of two othe...

Page 534: ...d 32 bit sign extended values When the operation completes the low order word of the double result is loaded into special register LO and the high order word of the double result is loaded into special register HI If either of the two preceding instructions is MFHI or MFLO the results of these instructions are undefined Correct operation requires separating reads of HI or LO from writes by a minim...

Page 535: ...0 0 0 0 0 NOR 1 0 0 1 1 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format NOR rd rs rt Description The contents of general register rs are combined with the contents of general register rt in a bit wise logical NOR operation The result is placed into general register rd Operation 32 64 T GPR rd GPR rs nor GPR rt Exceptions None ...

Page 536: ...0 0 0 0 0 OR 1 0 0 1 0 1 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format OR rd rs rt Description The contents of general register rs are combined with the contents of general register rt in a bit wise logical OR operation The result is placed into general register rd Operation 32 64 T GPR rd GPR rs or GPR rt Exceptions None ...

Page 537: ...0 16 15 0 6 5 5 16 Format ORI rt rs immediate Description The 16 bit immediate is zero extended and combined with the contents of general register rs in a bit wise logical OR operation The result is placed into general register rt Operation 32 T GPR rt GPR rs 31 16 immediate or GPR rs 15 0 64 T GPR rt GPR rs 63 16 immediate or GPR rs 15 0 Exceptions None ...

Page 538: ... offset15 16 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian3 byte vAddr2 0 xor BigEndianCPU3 data GPR rt 63 8 byte 0 0 8 byte StoreMemory uncached BYTE data pAddr vAddr DATA 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian3 byte vAddr2 0 xor BigEn...

Page 539: ...her of the three least significant bits of the effective address are non zero an address error exception occurs This operation is defined in 64 bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA data GPR rt StoreMem...

Page 540: ...ubleword The SDL instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address that may specify an arbitrary byte It alters only the word in memory that contains that byte From one to four bytes will be stored depending on the starting byte specified Conceptually it starts at the most significant byte of the register and copies it to the specif...

Page 541: ...bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian 3 if BigEndianMem 0 then pAddr pAddrPSIZE 1 3 0 3 endif byte vAddr2 0 xor BigEndianCPU 3 data 0 56 8 byte GPR rt 63 ...

Page 542: ... 5 6 7 I J K L MNOA I J K L MN A B I J K L MA B C I J K L A B C D I J K A B C D E I J A B CD E F I A B C D E F G A B C D E F GH 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Remark LEM Little endian memory BigEndianMem 0 Type AccessType see Table 2 3 Byte Specification Related to Load and Store Instructions sent to memory Offset pAddr2 0 sent to memory Exceptions TLB refill exception TLB invalid exception TLB m...

Page 543: ...ord of memory The SDR instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address that may specify an arbitrary byte It alters only the word in memory that contains that byte From one to eight bytes will be stored depending on the starting byte specified Conceptually it starts at the least significant byte of the register and copies it to the...

Page 544: ...bit mode or in 32 bit kernel mode Execution of this instruction in 32 bit user or supervisor mode causes a reserved instruction exception Operation 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian3 if BigEndianMem 0 then pAddr pAddrPSIZE 1 3 03 endif byte vAddr2 0 xor BigEndianCPU3 data GPR rt 63 8 byte 0 8 byte...

Page 545: ...0 1 2 3 4 5 6 7 A B C D E F GH B C D E F GH P C D E F GHOP D E F GHNOP E F GHMNOP F GH L MNOP G H K L MNOP H J K L MNOP 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 Remark LEM Little endian memory BigEndianMem 0 Type AccessType see Table 2 3 Byte Specification Related to Load and Store Instructions sent to memory Offset pAddr2 0 sent to memory Exceptions TLB refill exception TLB invalid exception TLB modificat...

Page 546: ... address error exception occurs Operation 32 T vAddr offset15 16 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian2 0 byte vAddr2 0 xor BigEndianCPU2 0 data GPR rt 63 8 byte 0 0 8 byte StoreMemory uncached HALFWORD data pAddr vAddr DATA 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrP...

Page 547: ... in the destination register It is sign extended for all shift amounts including zero SLL with zero shift amount truncates a 64 bit value to 32 bits and then sign extends this 32 bit value SLL unlike nearly all other word operations does not require an operand to be a properly sign extended word value to produce a valid sign extended word result Operation 32 T GPR rd GPR rt 31 sa 0 0 sa 64 T s 0 s...

Page 548: ...esult is sign extended when placed in the destination register It is sign extended for all shift amounts including zero SLLV with zero shift amount truncates a 64 bit value to 32 bits and then sign extends this 32 bit value SLLV unlike nearly all other word operations does not require an operand to be a properly sign extended word value to produce a valid sign extended word result Operation 32 T s...

Page 549: ...f general register rs Considering both quantities as signed integers if the contents of general register rs are less than the contents of general register rt the result is set to one otherwise the result is set to zero No integer overflow exception occurs under any circumstances The comparison is valid even if the subtraction used during the comparison overflows Operation 32 T if GPR rs GPR rt the...

Page 550: ...ral register rs Considering both quantities as signed integers if rs is less than the sign extended immediate the result is set to 1 otherwise the result is set to 0 No integer overflow exception occurs under any circumstances The comparison is valid even if the subtraction used during the comparison overflows Operation 32 T if GPR rs immediate15 16 immediate15 0 then GPR rt 0 31 1 else GPR rt 0 3...

Page 551: ...neral register rs Considering both quantities as unsigned integers if rs is less than the sign extended immediate the result is set to 1 otherwise the result is set to 0 No integer overflow exception occurs under any circumstances The comparison is valid even if the subtraction used during the comparison overflows Operation 32 T if 0 GPR rs 0 immediate15 16 immediate15 0 then GPR rt 0 31 1 else GP...

Page 552: ...ts of general register rs Considering both quantities as unsigned integers if the contents of general register rs are less than the contents of general register rt the result is set to 1 otherwise the result is set to 0 No integer overflow exception occurs under any circumstances The comparison is valid even if the subtraction used during the comparison overflows Operation 32 T if 0 GPR rs 0 GPR r...

Page 553: ...6 15 11 10 6 5 0 6 5 5 5 5 6 Format SRA rd rt sa Description The contents of general register rt are shifted right by sa bits sign extending the high order bits The result is placed in register rd In 64 bit mode the operand must be a valid sign extended 32 bit value Operation 32 T GPR rd GPR rt 31 sa GPR rt 31 sa 64 T s 0 sa temp GPR rt 31 s GPR rt 31 s GPR rd temp31 32 temp Exceptions None ...

Page 554: ...AV rd rt rs Description The contents of general register rt are shifted right by the number of bits specified by the low order five bits of general register rs sign extending the high order bits The result is placed in register rd In 64 bit mode the operand must be a valid sign extended 32 bit value Operation 32 T s GPR rs 4 0 GPR rd GPR rt 31 s GPR rt 31 s 64 T s GPR rs 4 0 temp GPR rt 31 s GPR r...

Page 555: ...20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format SRL rd rt sa Description The contents of general register rt are shifted right by sa bits inserting zeros into the high order bits The result is placed in register rd In 64 bit mode the operand must be a valid sign extended 32 bit value Operation 32 T GPR rd 0 sa GPR rt 31 sa 64 T s 0 sa temp 0 s GPR rt 31 s GPR rd temp31 32 temp Exceptions None ...

Page 556: ... SRLV rd rt rs Description The contents of general register rt are shifted right by the number of bits specified by the low order five bits of general register rs inserting zeros into the high order bits The result is placed in register rd In 64 bit mode the operand must be a valid sign extended 32 bit value Operation 32 T s GPR rs 4 0 GPR rd 0 s GPR rt 31 s 64 T s GPR rs 4 0 temp 0 s GPR rt 31 s ...

Page 557: ...SysAD bus is idle state after then the internal clocks will shut down thus freezing the pipeline The PLL Timer Interrupt clocks and the internal bus clocks TClock and MasterOut will continue to run Once this processor is in Standby mode any interrupt including the internally generated timer interrupt NMI Soft Reset and Cold Reset will cause this processor to exit Standby mode and to enter Fullspee...

Page 558: ...ult The result is placed into general register rd In 64 bit mode the operands must be valid sign extended 32 bit values The only difference between this instruction and the SUBU instruction is that SUBU never traps on overflow An integer overflow exception takes place if the carries out of bits 30 and 31 differ 2 s complement overflow The destination register rd is not modified when an integer ove...

Page 559: ...escription The contents of general register rt are subtracted from the contents of general register rs to form a result The result is placed into general register rd In 64 bit mode the operands must be valid sign extended 32 bit values The only difference between this instruction and the SUB instruction is that SUBU never traps on overflow Operation 32 T GPR rd GPR rs GPR rt 64 T temp GPR rs GPR r...

Page 560: ...by the SysAD bus is idle state after then the internal clocks including the TClock will shut down thus freezing the pipeline The PLL Timer Interrupt clocks and MasterOut will continue to run Once this processor is in Suspend mode any interrupt including the internally generated timer interrupt NMI Soft Reset and Cold Reset will cause this processor to exit Suspend mode and to enter Fullspeed mode ...

Page 561: ...ss are non zero an address error exception occurs Operation 32 T vAddr offset15 16 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian 02 byte vAddr2 0 xor BigEndianCPU 02 data GPR rt 63 8 byte 0 8 byte StoreMemory uncached WORD data pAddr vAddr DATA 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA ...

Page 562: ... of the low order word The SWL instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address that may specify an arbitrary byte It alters only the word in memory that contains that byte From one to four bytes will be stored depending on the starting byte specified Conceptually it starts at the most significant byte of the register and copies it...

Page 563: ... BigEndianCPU 0 then data 0 32 0 24 8 byte GPR rt 31 24 8 byte else data 0 24 8 byte GPR rt 31 24 8 byte 0 32 endif StoreMemory uncached byte data pAddr vAddr DATA 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian3 if BigEndianMem 0 then pAddr pAddrPSIZE 1 2 02 endif byte vAddr1 0 xor BigEndianCPU2 if vAddr2 xor ...

Page 564: ...tion Type Offset LEM 0 1 2 3 4 5 6 7 I J K L MNOE I J K L MN E F I J K L ME F G I J K L E F GH I J K EMNOP I J E F MNOP I E F GMNOP E F GHMNOP 0 1 2 3 0 1 2 3 0 0 0 0 4 4 4 4 Remark LEM Little endian memory BigEndianMem 0 Type AccessType see Table 2 3 Byte Specification Related to Load and Store Instructions sent to memory Offset pAddr2 0 sent to memory Exceptions TLB refill exception TLB invalid ...

Page 565: ...low order word of memory The SWR instruction adds its sign extended 16 bit offset to the contents of general register base to form a virtual address that may specify an arbitrary byte It alters only the word in memory that contains that byte From one to four bytes will be stored depending on the starting byte specified Conceptually it starts at the least significant rightmost byte of the register ...

Page 566: ...r2 xor BigEndianCPU 0 then data 0 32 GPR rt 31 8 byte 0 0 8 byte else data GPR rt 31 8 byte 0 8 byte 0 32 endif StoreMemory uncached WORD byte data pAddr vAddr DATA 64 T vAddr offset15 48 offset15 0 GPR base pAddr uncached AddressTranslation vAddr DATA pAddr pAddrPSIZE 1 3 pAddr2 0 xor ReverseEndian3 if BigEndianMem 1 then pAddr pAddrPSIZE 1 2 02 endif byte vAddr1 0 xor BigEndianCPU2 if vAddr2 xor...

Page 567: ...Destination Type Offset LEM 0 1 2 3 4 5 6 7 I J K L E F GH I J K L F GH P I J K L GHOP I J K L HNOP E F GHMNOP F GH L MNOP G H K L MNOP H J K L MNOP 3 2 1 0 3 2 1 0 0 1 2 3 4 5 6 7 Remark LEM Little endian memory BigEndianMem 0 Type AccessType see Table 2 3 Byte Specification Related to Load and Store Instructions sent to memory Offset pAddr2 0 sent to memory Exceptions TLB refill exception TLB in...

Page 568: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 31 26 25 6 5 0 6 20 SYNC 0 0 1 1 1 1 6 Format SYNC Description The SYNC instruction is executed as a NOP on the VR4121 This operation maintains compatibility with code compiled for the VR4000 This instruction is defined to maintain the compatibility with VR4000 and VR4400 Operation 32 64 T SyncOperation Exceptions None ...

Page 569: ... Format SYSCALL Description A system call exception occurs immediately and unconditionally transferring control to the exception handler The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Operation 32 64 T SystemCallException Exceptions System Call exception ...

Page 570: ...ts of general register rt are compared to general register rs If the contents of general register rs are equal to the contents of general register rt a trap exception occurs The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Operation 32 64 T if GPR rs GPR rt then TrapExcept...

Page 571: ...ormat TEQI rs immediate Description The 16 bit immediate is sign extended and compared to the contents of general register rs If the contents of general register rs are equal to the sign extended immediate a trap exception occurs Operation 32 T if GPR rs immediate15 16 immediate15 0 then TrapException endif 64 T if GPR rs immediate15 48 immediate15 0 then TrapException endif Exceptions Trap except...

Page 572: ...ompared to the contents of general register rs Considering both quantities as signed integers if the contents of general register rs are greater than or equal to the contents of general register rt a trap exception occurs The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Op...

Page 573: ... Description The 16 bit immediate is sign extended and compared to the contents of general register rs Considering both quantities as signed integers if the contents of general register rs are greater than or equal to the sign extended immediate a trap exception occurs Operation 32 T if GPR rs immediate15 16 immediate15 0 then TrapException endif 64 T if GPR rs immediate15 48 immediate15 0 then Tr...

Page 574: ...e Description The 16 bit immediate is sign extended and compared to the contents of general register rs Considering both quantities as unsigned integers if the contents of general register rs are greater than or equal to the sign extended immediate a trap exception occurs Operation 32 T if 0 GPR rs 0 immediate15 16 immediate15 0 then TrapException endif 64 T if 0 GPR rs 0 immediate15 48 immediate1...

Page 575: ...e compared to the contents of general register rs Considering both quantities as unsigned integers if the contents of general register rs are greater than or equal to the contents of general register rt a trap exception occurs The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instructi...

Page 576: ...register is set The architecture does not specify the operation of memory references associated with the instruction immediately after a TLBP instruction nor is the operation specified if more than one TLB entry matches Operation 32 T Index 1 0 25 Undefined6 for i in 0 TLBEntries 1 if TLB i 95 77 EntryHi31 13 and TLB i 76 or TLB i 71 64 EntryHi7 0 then Index 0 26 i5 0 endif endfor 64 T Index 1 0 2...

Page 577: ...he TLB is written into both of the EntryLo0 and EntryLo1 registers The operation is invalid and the results are unspecified if the contents of the TLB Index register are greater than the number of TLB entries in the processor Operation 32 T PageMask TLB Index5 0 127 96 EntryHi TLB Index5 0 95 64 and not TLB Index5 0 127 96 EntryLo1 TLB Index5 0 63 33 TLB Index5 0 76 EntryLo0 TLB Index5 0 31 1 TLB ...

Page 578: ...contents of the TLB Index register is loaded with the contents of the EntryHi and EntryLo registers The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers The operation is invalid and the results are unspecified if the contents of the TLB Index register are greater than the number of TLB entries in the processor Operation 32 64 T TLB Index5 0 Page...

Page 579: ...5 0 6 19 6 CO 1 1 24 Format TLBWR Description The TLB entry pointed at by the contents of the TLB Random register is loaded with the contents of the EntryHi and EntryLo registers The G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers Operation 32 64 T TLB Random5 0 PageMask EntryHi and not PageMask EntryLo1 EntryLo0 Exceptions Coprocessor unusable...

Page 580: ... rt are compared to general register rs Considering both quantities as signed integers if the contents of general register rs are less than the contents of general register rt a trap exception occurs The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Operation 32 64 T if GPR...

Page 581: ...e Description The 16 bit immediate is sign extended and compared to the contents of general register rs Considering both quantities as signed integers if the contents of general register rs are less than the sign extended immediate a trap exception occurs Operation 32 T if GPR rs immediate15 16 immediate15 0 then TrapException endif 64 T if GPR rs immediate15 48 immediate15 0 then TrapException en...

Page 582: ...ate Description The 16 bit immediate is sign extended and compared to the contents of general register rs Considering both quantities as unsigned integers if the contents of general register rs are less than the sign extended immediate a trap exception occurs Operation 32 T if 0 GPR rs 0 immediate15 16 immediate15 0 then TrapException endif 64 T if 0 GPR rs 0 immediate15 48 immediate15 0 then Trap...

Page 583: ...ster rt are compared to general register rs Considering both quantities as unsigned integers if the contents of general register rs are less than the contents of general register rt a trap exception occurs The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Operation 32 64 T ...

Page 584: ...ts of general register rt are compared to general register rs If the contents of general register rs are not equal to the contents of general register rt a trap exception occurs The code field is available for use as software parameters but is retrieved by the exception handler only by loading the contents of the memory word containing the instruction Operation 32 64 T if GPR rs GPR rt then TrapEx...

Page 585: ...ormat TNEI rs immediate Description The 16 bit immediate is sign extended and compared to the contents of general register rs If the contents of general register rs are not equal to the sign extended immediate a trap exception occurs Operation 32 T if GPR rs immediate15 16 immediate15 0 then TrapException endif 64 T if GPR rs immediate15 48 immediate15 0 then TrapException endif Exceptions Trap ex...

Page 586: ...0 0 0 0 0 XOR 1 0 0 1 1 0 31 26 25 21 20 16 15 11 10 6 5 0 6 5 5 5 5 6 Format XOR rd rs rt Description The contents of general register rs are combined with the contents of general register rt in a bit wise logical exclusive OR operation The result is placed into general register rd Operation 32 64 T GPR rd GPR rs xor GPR rt Exceptions None ...

Page 587: ...31 26 25 21 20 16 15 0 6 5 5 16 Format XORI rt rs immediate Description The 16 bit immediate is zero extended and combined with the contents of general register rs in a bit wise logical exclusive OR operation The result is placed into general register rt Operation 32 T GPR rt GPR rs xor 0 16 immediate 64 T GPR rt GPR rs xor 0 48 immediate Exceptions None ...

Page 588: ... LDLε LDRε JALXθ 4 LB LH LWL LW LBU LHU LWR LWUε 5 SB SH SWL SW SDLε SDRε SWR CACHEδ 6 π π π π LDε 7 π π π π SDε 2 0 SPECIAL function 5 3 0 1 2 3 4 5 6 7 0 SLL SRL SRA SLLV SRLV SRAV 1 JR JALR SYSCALL BREAK SYNC 2 MFHI MTHI MFLO MTLO DSLLVε DSRLVε DSRAVε 3 MULT MULTU DIV DIVU DMULTε DMULTUε DDIVε DDIVUε 4 ADD ADDU SUB SUBU AND OR XOR NOR 5 MACC DMACC SLT SLTU DADDε DADDUε DSUBε DSUBUε 6 TGE TGEU T...

Page 589: ...ction exception They are reserved for future versions of the architecture δ Operation codes marked with a delta are valid only for VR4400 Series processors with CP0 enabled and cause a reserved instruction exception on other processors φ Operation codes marked with a phi are invalid but do not cause reserved instruction exceptions in VR4121 implementations ξ Operation codes marked with a xi cause ...

Page 590: ...he CP0 hazards of the VR4120A core are as or less stringent than those of the VR4000 Table B 1 lists the Coprocessor 0 hazards of the VR4120A core Code that complies with these hazards will run without modification on the VR4000 The contents of the CP0 registers or the bits in the Source column of this table can be used as a source after they are fixed The contents of the CP0 registers or the bits...

Page 591: ... ERL 2 Instruction fetch EntryHi ASID Status KSU Status EXL Status ERL Status RE Config K0C 2 TLB 2 Instruction fetch EPC Status 4 exception Cause BadVAddr Context XContext 5 Interrupt signals Cause IP Status IM Status IE Status EXL Status ERL 2 Load Store EntryHi ASID Status KSU Status EXL Status ERL Status RE Config K0C TLB 3 Config AD Config EP 3 WatchHi WatchLo 3 Load Store exception EPC Statu...

Page 592: ...s used to specify a TLB entry Destination The completion of writing to TLB by these instructions 5 TLBP Source The confirmation of the PageMask register and the EntryHi register before the execution of TLBP Destination The completion of writing the result of execution of TLBP to the Index register 6 ERET Source The confirmation of registers containing information necessary for executing ERET Desti...

Page 593: ...etch 12 Interrupts Source The confirmation of registers judging the condition of occurrence of interrupt when an interrupt factor is detected 13 Loads Sores Source The confirmation of the operating mode related to the address generation of Load Store instructions TLB entries the cache mode set in the K0 bit of the Config register and the registers setting the condition of occurrence of a Watch exc...

Page 594: ... 2 5 2 1 MTC0 Status CU Coprocessor instruction that requires the setting of CU Status CU 2 5 2 1 TLBR MFC0 EntryHi EntryHi 1 5 3 1 MTC0 EntryLo0 TLBWR TLBWI EntryLo0 2 5 2 1 TLBP MFC0 Index Index 2 6 3 1 MTC0 EntryHi TLBP EntryHi 2 5 2 1 MTC0 EPC ERET EPC 2 5 2 1 MTC0 Status ERET Status 2 5 2 1 MTC0 Status IE Note Instruction that causes an interrupt Status IE 2 5 2 1 Note The number of hazards i...

Page 595: ... 886 2 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Market Communication Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6462 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 81 44 435 9608 ...

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