NEC MultiSync FP1370, Service Manual

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9. DYNAMIC CONVERGENCE CORRECTION CIRCUIT
The dynamic convergence correction circuit consists of the digital convergence circuit(IC8U1 and IC8U2) and
the DSP convergence correction circuit(IC501) and the output circuit(IC8P2, and IC8P1).
1) Digital Convergence Circuit
The digital convergence circuit make three correction signals(4H and 4V).
4H :R-B(X) convergence can be adjusted.
4V :R-B(Y) convergence can be adjusted.
These signals can change individually at 165 blocks(ROW:1-11,COLUMN:1-15) on the picture.
When the power turn on, the convergence correction data which is held at IC802 is sent to IC8U2 through
IC801 and IC8U1, then the data is output from IC8U1. The timing of the output data corresponds with AFC
and V_PUMP timing. The output data is converted to analog signals by R-2R ladder resistance (MR8U1 and
MR8U2). The MUTE signal which stop convergence correction current is output from IC8U1 at pin 95. This
signal work during the degauss is proceeded.
2) DSP Convergence Correction Circuit
The DSP convergence circuit make two correction signals (XSC and YSC).
These signals are composed of DC, vertical saw wave and vertical parabolic wave. The fig.9.3 show the
relationship between the waveform and picture image.
IC501
HE6-0092 (DSP)
IC802
(E
2
PROM
)
IC801
(CPU)
IC8U1
uPD93299GD
(Digital
Convergence
correction IC)
XSC
YSC
IC8U2(SRAM)
6H
4H
4V
AFC
MUTE
V_PUMP
I
2
C-bus
VIDEO PWB
OSC PWB
CONV PWB
IC8P1(STK391-110)
IC8P1(STK391-110)
4V correction
coil (on CRT)
4H correction
coil (on CRT)
N.C
(Fig. 9.1) Dynamic Convergence Correction Circuit