8-26
4) Plug and Play (DDC 1 / 2)
VESA Display Data Channels (DDC)
a. DDC1
When the monitor is turned on, the operation mode starts in DDC1 mode. When the VCLK (SYNC) is
provided to IC8A1 pin 7, serial data stream is generated from the IC8A1 pin 5 by synchronizing with the
rising edge of the VCLK. The contents of the serial data (SDA) is called EDID, and it contains the
information of monitor’s specification and supported signals. The EDID is composed of 8 bits, 128 bytes,
but the individual data is composed of 9 bits. The 9th bit is always low and is ignored. If 128 bytes are
finished to generate, then the 24LCS21A starts to generate the first byte. This operation lasts
continuously until the operation mode changes to DDC2B.
b. DDC2B
When the SCL (IC8A1 pin 6) input is changed from high to low, the operation mode changes from DDC1
to DDC2B. The output data is the same as DDC1 (EDID), but the communication protocol is different. In
DDC2B mode, the serial data is communicated by I
2
C-bus protocol. The operation mode never go back
from DDC2B to DDC1 except by turning off the monitor.
1 2
3 4 5 6 7 8 9 1 2
SDA
VCLK
SDA
SCL
VCLK
DDC1 mode
DDC2B mode
Summary of Contents for MultiSync FP1370
Page 13: ...4 4 REMARK SYMBOL Mount the EMF PWB 121E REMARK SYMBOL Clamp the connector ...
Page 14: ...4 5 REMARK SYMBOL COIL FORMING UPPER SIDE REMARK SYMBOL COIL FORMING LOWER SIDE ...
Page 23: ...4 14 REMARK SYMBOL REMARK SYMBOL Clamp CN CA CN CC and CN D with CLAMPER WIRE ...
Page 26: ...4 17 REMARK SYMBOL Clamp the wires SAFETY REMARK SYMBOL Clamp the wires CN ASD CN AF 21 ...
Page 80: ...5 51 Fig 3 11 CONV PWB Fig 3 12 EMF PWB CN EMF CN LL CN RR CNEM CN CA CN D CN CCB HS8N1 ...
Page 143: ...8 18 15V 80V AFC D FOCUS Fig 3 1 HIGH VOLTAGE CIRCUIT AND PROTECTOR CIRCUIT ...
Page 260: ...10 1 ...
Page 261: ...10 2 ...
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Page 264: ...10 5 ...
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