NEC mPD789426 Series User Manual Download

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CHAPTER 3 CPU ARCHITECTURE

User’s Manual U15075EJ1V0UM00

Figure 3-8. Data Memory Addressing (

µµµµ

PD789426, 789436)

Special function registers (SFRs)

256

8 bits

Internal high-speed RAM

512

8 bits

Internal ROM

16384

8 bits

FFFFH

0000H

Direct addressing

Based addressing

FF00H

FEFFH

FF20H

FF1FH

FE20H

FE1FH

SFR addressing

Short direct
addressing

LCD display RAM

4 bits

Reserved

FD00H

FCFFH

FA00H
F9FFH

4000H

3FFFH

FA05H
FA04H

Summary of Contents for mPD789426 Series

Page 1: ...D789446 PD789435 PD789455 PD789436 PD789456 PD78F9436 PD78F9456 PD789426 789436 789446 789456 Subseries 8 Bit Single Chip Microcontrollers Printed in Japan Document No U15075EJ1V0UM00 1st edition Date...

Page 2: ...2 User s Manual U15075EJ1V0UM00 MEMO...

Page 3: ...al All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar...

Page 4: ...third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and ackno...

Page 5: ...ronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel...

Page 6: ...6 User s Manual U15075EJ1V0UM00 MEMO...

Page 7: ...ubseries User s Manual 78K 0S Series User s Manual Instructions Pin functions Internal block functions Interrupts Other internal peripheral functions CPU function Instruction set Instruction descripti...

Page 8: ...r s Manual U15075J This manual 78K 0S Series Instructions User s Manual U11047J U11047E 78K 0 78K 0S Series Flash Memory Write Application Note U14458J U14458E Documents Related to Development Tools U...

Page 9: ...X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability Quality Control System C10983J C10983...

Page 10: ...10 User s Manual U15075EJ1V0UM00 MEMO...

Page 11: ...1 List of Pin Functions 37 2 2 Description of Pin Functions 40 2 2 1 P00 to P03 Port 0 40 2 2 2 P10 P11 Port 1 40 2 2 3 P20 to P26 Port 2 40 2 2 4 P30 to P33 Port 3 41 2 2 5 P50 to P53 Port 5 41 2 2...

Page 12: ...3 3 4 4 Register addressing 74 3 4 5 Register indirect addressing 75 3 4 6 Based addressing 76 3 4 7 Stack addressing 76 CHAPTER 4 PORT FUNCTIONS 77 4 1 Port Functions 77 4 2 Port Configuration 80 4 2...

Page 13: ...127 6 4 5 Buzzer output operation 128 6 5 Notes on Using 16 Bit Timer 129 CHAPTER 7 8 BIT TIMER 131 7 1 8 Bit Timer Functions 131 7 2 8 Bit Timer Configuration 132 7 3 Registers Controlling 8 Bit Time...

Page 14: ...sters 200 11 4 10 Bit A D Converter Operation 202 11 4 1 Basic operation of 10 bit A D converter 202 11 4 2 Input voltage and conversion result 203 11 4 3 Operation mode of 10 bit A D converter 205 11...

Page 15: ...Standby Function Operation 281 15 2 1 HALT mode 281 15 2 2 STOP mode 284 CHAPTER 16 RESET FUNCTION 287 CHAPTER 17 PD78F9436 78F9456 291 17 1 Flash Memory Programming 292 17 1 1 Selecting communicatio...

Page 16: ...r s Manual U15075EJ1V0UM00 APPENDIX B EMBEDDED SOFTWARE 315 APPENDIX C REGISTER INDEX 317 C 1 Register Index Alphabetic Order of Register Name 317 C 2 Register Index Alphabetic Order of Register Symbo...

Page 17: ...Be Saved to Stack Memory 63 3 17 Data to Be Restored from Stack Memory 63 3 18 General Purpose Register Configuration 64 4 1 Port Types PD789426 789436 Subseries 77 4 2 Port Types PD789446 789456 Sub...

Page 18: ...trol Register 90 for Capture Operation 126 6 10 Capture Operation Timing Both Edges of CPT90 Pin Are Specified 126 6 11 16 Bit Timer Counter 90 Readout Timing 127 6 12 Settings of Buzzer Output Contro...

Page 19: ...Counter 170 7 29 Timing of Operation as External Event Counter 8 Bit Resolution 170 8 1 Block Diagram of Watch Timer 171 8 2 Format of Watch Timer Mode Control Register 173 8 3 Watch Timer Interval Ti...

Page 20: ...nchronous Serial Interface Reception Completion Interrupt Timing 234 12 10 Receive Error Timing 235 12 11 3 Wire Serial I O Mode Timing 240 13 1 Block Diagram of LCD Controller Driver 248 13 2 Format...

Page 21: ...nt Timing When Interrupt Request Flag Is Generated in Final Clock Under Execution 275 14 15 Example of Multiple Interrupts 276 15 1 Format of Oscillation Stabilization Time Select Register 280 15 2 Re...

Page 22: ...des 131 7 2 8 Bit Timer Configuration 132 7 3 Interval Time of Timer 50 144 7 4 Interval Time of Timer 60 144 7 5 Square Wave Output Range of Timer 50 During fX 5 0 MHz Operation 151 7 6 Square Wave O...

Page 23: ...river 247 13 3 Frame Frequencies Hz 251 13 4 COM Signals 254 13 5 LCD Drive Voltage 254 13 6 Select and Deselect Voltages COM0 to COM2 256 13 7 Select and Deselect Voltages COM0 to COM3 259 14 1 Inter...

Page 24: ...24 User s Manual U15075EJ1V0UM00 MEMO...

Page 25: ...s 32 768 kHz operation with subsystem clock I O ports 40 PD789426 789436 Subseries 30 PD789446 789456 Subseries Timer 5 channels 16 bit timer 1 channel 8 bit timer 2 channels Watch timer 1 channel Wa...

Page 26: ...tic TQFP 12 12 mm Mask ROM PD789436GK 9ET 64 pin plastic TQFP 12 12 mm Mask ROM PD789445GK 9ET 64 pin plastic TQFP 12 12 mm Mask ROM PD789446GK 9ET 64 pin plastic TQFP 12 12 mm Mask ROM PD789455GK 9ET...

Page 27: ...38 37 36 35 34 33 P50 P51 P52 P53 IC VPP XT1 XT2 VDD VSS X1 X2 RESET P00 KR0 P01 KR1 P02 KR2 P03 KR3 32 CAPH CAPL V LC0 V LC1 V LC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 P90 P91 P62 ANI2 P63 ANI3 P64 ANI...

Page 28: ...4 33 P50 P51 P52 P53 IC VPP XT1 XT2 VDD VSS X1 X2 RESET P00 KR0 P01 KR1 P02 KR2 P03 KR3 32 CAPH CAPL V LC0 V LC1 V LC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 S5 S6 P62 ANI2 P63 ANI3 P64 ANI4 P65 ANI5 AVDD...

Page 29: ...I20 Serial input CPT90 Capture trigger input SO20 Serial output IC Internally connected TMI60 Timer input INTP0 to INTP3 External interrupt input TO90 TO50 TO60 KR0 to KR3 Key return TO61 Timer output...

Page 30: ...erter 44 pin 30 pin 30 pin 30 pin 30 pin PD789124A PD789134A PD789177 PD789167 30 pin 30 pin PD789104A PD789114A PD789167 with enhanced A D converter PD789104A with enhanced timer PD789124A with enhan...

Page 31: ...h 1 ch 4 ch 1 ch UART 1 ch 20 1 8 V Inverter control PD789842 8 K to 16 K 3 ch Note 1 ch 1 ch 8 ch 1 ch UART 1 ch 30 4 0 V VFD drive PD789871 4 K to 8 K 3 ch 1 ch 1 ch 1 ch 33 2 7 V PD789488 32 K 8 ch...

Page 32: ...it timer event counter 60 Cascaded 16 bit timer event counter TO60 P32 CPT90 P30 VLC0 to VLC2 CAPH CAPL LCD controller driver P50 to P53 Port 5 System control RESET X1 X2 XT1 XT2 Interrupt control INT...

Page 33: ...P31 16 bit timer 90 Watch timer Watchdog timer TO90 P26 S0 to S4 COM0 to COM3 RAM RAM space for LCD data 8 bit timer event counter 60 Cascaded 16 bit timer event counter TO60 P32 CPT90 P30 VLC0 to VL...

Page 34: ...st I O ports Total 40 CMOS I O 30 CMOS input 6 N ch open drain 4 Total 30 CMOS I O 20 CMOS input 6 N ch open drain 4 Timers 16 bit timer 1 channel 8 bit timer 2 channels Watch timer 1 channel Watchdog...

Page 35: ...2 Operation mode External event counter 1 channel Timer outputs 1 1 2 Square wave outputs 1 2 Capture 1 input Function Interrupt sources 1 1 1 1 1 Notes 1 The watch timer can perform both watch timer...

Page 36: ...36 User s Manual U15075EJ1V0UM00 MEMO...

Page 37: ...ort Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B2 PUB2 Input TO90 P30 INTP0 CPT90...

Page 38: ...1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B8 PUB8 Input P90 to P97 Note I O Port 9 8 bit I O port Input output c...

Page 39: ...r TM90 output Input P26 CPT90 Input Capture edge input Input P30 INTP0 TO50 Output 8 bit timer TM50 output Input P31 INTP1 TMI40 TO60 Output Input P32 INTP2 TO61 Output 8 bit timer TM60 output Input P...

Page 40: ...specified by pull up resistor option register 0 PU0 in port units 2 2 3 P20 to P26 Port 2 These pins constitute a 7 bit I O port In addition these pins enable buzzer output timer output serial interf...

Page 41: ...gister B3 PUB3 in 1 bit units 2 Control mode In this mode P30 to P33 function as timer I O and external interrupt input a TMI60 This is the external clock input pin to timer 60 b TO50 TO60 TO61 These...

Page 42: ...ister 9 PM9 When used as an input port use of an on chip pull up resistor can be specified by pull up resistor option register B9 PUB9 in port units Note Only the PD789426 and PD789436 Subseries 2 2 1...

Page 43: ...the normal operation mode 2 2 20 IC mask ROM version only The IC Internally Connected pin is used to set the PD789426 789436 789446 and 789456 Subseries in the test mode before shipment In the normal...

Page 44: ...Leave open P30 INPT0 CPT90 P31 INPT1 TO50 TMI60 P32 INPT2 TO60 P33 INPT3 TO61 8 A Input Independently connect to VSS via a resistor Output Leave open P50 to P53 Mask ROM version 13 W P50 to P53 Flash...

Page 45: ...Output disable Input enable VDD P ch VDD P ch IN OUT N ch VSS VSS Output data Output disable IN OUT VDD N ch Middle voltage input buffer Input enable Pull up resistor mask option Type 8 A Type 17 Pull...

Page 46: ...46 User s Manual U15075EJ1V0UM00 MEMO...

Page 47: ...s Figure 3 1 Memory Map PD789425 789435 Special function registers 256 8 bits Internal high speed RAM 512 8 bits LCD display RAM 5 4 bits Reserved Reserved Internal ROM 12288 8 bits FFFFH FF00H FEFFH...

Page 48: ...bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT ta...

Page 49: ...ts Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table...

Page 50: ...bits Internal high speed RAM 512 8 bits Internal ROM 12288 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 2FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT ta...

Page 51: ...bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT ta...

Page 52: ...ts Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table...

Page 53: ...ory space 1 Vector table area The 34 byte area of addresses 0000H to 0021H is reserved as a vector table area This area stores program start addresses to be used when branching by the RESET input or a...

Page 54: ...M is also used as a stack 2 LCD display RAM LCD display RAM is incorporated The LCD display RAM can also be used as ordinary RAM Each subseries incorporates LCD display RAM with the following capacity...

Page 55: ...spond to the particular function an area such as the special function registers are available Figures 3 7 through 3 12 show the data memory addressing modes Figure 3 7 Data Memory Addressing PD789425...

Page 56: ...egisters SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SF...

Page 57: ...sters SFRs 256 8 bits Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR a...

Page 58: ...egisters SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 12288 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SF...

Page 59: ...egisters SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SF...

Page 60: ...sters SFRs 256 8 bits Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR a...

Page 61: ...mber of bytes of the instruction to be fetched When a branch instruction is executed immediate data or register contents are set RESET input sets the reset vector table values at addresses 0000H and 0...

Page 62: ...arious interrupt sources IE is reset 0 upon DI instruction execution or interrupt acknowledgment and is set 1 upon EI instruction execution b Zero flag Z When the operation result is zero this flag is...

Page 63: ...estores data as shown in Figures 3 16 and 3 17 Caution Since RESET input makes the SP contents undefined be sure to initialize the SP before instruction execution Figure 3 16 Data to Be Saved to Stack...

Page 64: ...s in pairs can be used as a 16 bit register AX BC DE and HL General purpose registers can be described in terms of function names X A C B E D L H AX BC DE or HL or absolute names R0 to R7 and RP0 to R...

Page 65: ...operand sfr This manipulation can also be specified with an address 16 bit manipulation Describes a symbol reserved by the assembler for the 16 bit manipulation instruction operand When addressing an...

Page 66: ...1BH TCP90 Note 2 R Note 3 Undefined FF20H Port mode register 0 PM0 FF21H Port mode register 1 PM1 FF22H Port mode register 2 PM2 FF23H Port mode register 3 PM3 FF25H Port mode register 5 PM5 R W FFH N...

Page 67: ...ator output control register 60 TCA60 W FF70H Asynchronous serial interface mode register 20 ASIM20 R W FF71H Asynchronous serial interface status register 20 ASIS20 R FF72H Serial operation mode regi...

Page 68: ...addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program...

Page 69: ...transferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR addr16 instruction is executed CALL addr16 and BR addr16 instructions can be branched to any...

Page 70: ...ted The instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory...

Page 71: ...nstruction execution 3 4 1 Direct addressing Function The memory indicated with immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit...

Page 72: ...imer event counter are mapped in this area and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to...

Page 73: ...word This addressing is applied to the 256 byte space FF00H to FFFFH However the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing Operand format Identifier Description...

Page 74: ...rand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC...

Page 75: ...The register pair to be accessed is specified by the register pair specification code in an instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Desc...

Page 76: ...s Operand format Identifier Description HL byte Description example MOV A HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3 4 7 Stack addressing Function The stack are...

Page 77: ...ous methods of control Numerous other functions are provided that can be used in addition to the digital I O port functions For more information on these additional functions see CHAPTER 2 PIN FUNCTIO...

Page 78: ...ER 4 PORT FUNCTIONS 78 User s Manual U15075EJ1V0UM00 Figure 4 2 Port Types PD789446 789456 Subseries P30 P33 P60 P00 P03 P10 P11 Port 1 Port 2 Port 3 P20 P26 P65 Port 0 P70 P72 Port 7 Port 6 P50 P53 P...

Page 79: ...Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B2 PUB2 Input TO90 P30 INTP0 CPT90 P3...

Page 80: ...e specified by means of pull up resistor option register B9 PUB9 Input Note PD789426 789436 Subseries only 4 2 Port Configuration Ports have the following hardware configuration Table 4 2 Configuratio...

Page 81: ...e connected in 4 bit units by using pull up resistor option register 0 PU0 Port 0 is set in the input mode when the RESET signal is input Figure 4 3 shows a block diagram of port 0 Figure 4 3 Block Di...

Page 82: ...pins on chip pull up resistors can be connected in 2 bit units by using pull up resistor option register 0 PU0 This port is set in the input mode when the RESET signal is input Figure 4 4 shows a blo...

Page 83: ...interface I O buzzer output and timer output This port is set in the input mode when the RESET signal is input Figures 4 5 to 4 10 show block diagrams of port 2 Caution When using the pins of port 2...

Page 84: ...lock Diagram of P21 and P26 Internal bus VDD P ch P21 BZO90 P26 TO90 WRPUB2 RD WRPORT WRPM PUB21 PUB26 Output latch P21 P26 PM21 PM26 Alternate function Selector PUB2 Pull up resistor option register...

Page 85: ...0 85 Figure 4 7 Block Diagram of P22 Internal bus VDD P ch P22 SS20 WRPUB2 RD WRPORT WRPM PUB22 Alternate function Output latch P22 PM22 Selector PUB2 Pull up resistor option register B2 PM Port mode...

Page 86: ...8 Block Diagram of P23 Internal bus VDD P ch P23 ASCK20 SCK20 WRPUB2 RD WRPORT WRPM PUB23 Alternate function Output latch P23 PM23 Alternate function Selector PUB2 Pull up resistor option register B2...

Page 87: ...re 4 9 Block Diagram of P24 PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal Internal bus VDD P24 SO20 TxD20 WRPUB2 RD WRPORT WRPM PUB24 Alte...

Page 88: ...Figure 4 10 Block Diagram of P25 P25 SI20 RxD20 WRPUB2 RD WRPORT WRPM PUB25 Alternate function Output latch P25 PM25 VDD P ch Internal bus Selector PUB2 Pull up resistor option register B2 PM Port mo...

Page 89: ...bit units by using pull up resistor option register B3 PUB3 This port is also used as an external interrupt input capture input and timer I O This port is set in the input mode when the RESET signal i...

Page 90: ...B3 Pull up resistor option register B3 PM Port mode register RD Port 3 read signal WR Port 3 write signal P31 INTP1 TO50 TMI60 P32 INTP2 TO60 P33 INTP3 TO61 WRPUB3 RD WRPORT WRPM PUB31 to PUB33 PM31 t...

Page 91: ...ip pull up resistor can be specified by a mask option This port is set in the input mode when the RESET signal is input Figure 4 13 shows a block diagram of port 5 Figure 4 13 Block Diagram of P50 to...

Page 92: ...V0UM00 4 2 6 Port 6 This is an 8 bit input only port This port is also used as the analog input of an A D converter Figure 4 14 shows a block diagram of Port 6 Figure 4 14 Block Diagram of Port 6 VREF...

Page 93: ...pull up resistors can be connected in 1 bit units by using pull up resistor option register B7 PUB7 This port is set in the input mode when the RESET signal is input Figure 4 15 shows a block diagram...

Page 94: ...ut port pins on chip pull up resistors can be connected in 1 bit units by using pull up resistor option register B8 PUB8 This port is set in the input mode when the RESET signal is input Figure 4 16 s...

Page 95: ...port pins on chip pull up resistors can be connected in 1 bit units by using pull up resistor option register B9 PUB9 This port is set in the input mode when the RESET signal is input Figure 4 17 show...

Page 96: ...input output in 1 bit units The port mode registers are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the registers to FFH When port pins are used as alterna...

Page 97: ...7 Symbol Address After reset 6 5 4 3 2 1 0 R W FF20H FF21H FF25H FFH FFH FFH R W R W R W 1 1 1 1 1 PM72 PM71 PM70 PM7 FF27H FFH R W 1 1 1 1 1 1 PM81 PM80 PM8Note FF28H FFH R W PM97 PM96 PM95 PM94 PM93...

Page 98: ...ort output latch 2 Pull up resistor option register 0 PU0 Pull up resistor option register 0 PU0 sets whether on chip pull up registers are used on ports 0 and 1 or not On the port specified to use an...

Page 99: ...Address After reset R W FF32H 00H R W 7 6 5 4 3 2 1 0 PUB2n 0 1 On chip pull up resistor not used On chip pull up resistor used Symbol 4 Pull up resistor option register B3 PUB3 Pull up resistor optio...

Page 100: ...W 7 6 5 4 3 2 1 0 PUB7n 0 1 On chip pull up resistor not used On chip pull up resistor used Symbol 6 Pull up resistor option register B8 PUB8 Note Pull up resistor option register B8 PUB8 sets whethe...

Page 101: ...be used for the bits set in the output mode regardless of the setting of PUB9 This also applies to when the pins are used for alternate function PUB9 is set with a 1 bit or 8 bit memory manipulation...

Page 102: ...the pin that is set in the input mode and not subject to manipulation become undefined 4 4 2 Reading from I O port 1 In output mode The status of an output latch can be read by using a transfer instr...

Page 103: ...uting the STOP instruction or setting the processor clock control register PCC Subsystem clock oscillator This circuit oscillates at 32 768 kHz Oscillation can be stopped by the suboscillation mode re...

Page 104: ...bit timer 60 Watch timer LCD controller driver Clock to peripheral hardware CPU clock fCPU Standby controller Wait controller Selector STOP MCC PCC1 CLS CSS0 Internal bus Suboscillation mode register...

Page 105: ...ter reset R W FFFBH 02H R W 7 6 5 4 3 2 1 0 MCC 0 1 Operation enabled Operation disabled CPU clock fCPU selectionNote CSS0 0 0 1 1 PCC1 0 1 0 1 fX 0 2 s fX 22 0 8 s fXT 2 61 s Note The CPU clock is se...

Page 106: ...memory manipulation instruction RESET input sets SCKM to 00H Figure 5 3 Format of Suboscillation Mode Register Feedback resistor selection 0 0 0 0 0 0 FRC SCC SCKM Symbol Address After reset R W FFF0H...

Page 107: ...o 00H Figure 5 4 Format of Subclock Control Register CPU clock operation status 0 0 CLS CSS0 0 0 0 0 CSS Address After reset R W FFF2H 00H R W 7 6 5 4 3 2 1 0 CLS 0 1 Operation based on the output of...

Page 108: ...nected across the X1 and X2 pins An external clock can also be input to the circuit In this case input the clock signal to the X1 pin and input the inverted signal to the X2 pin Figure 5 5 shows the e...

Page 109: ...n using the main system or subsystem clock oscillator wire as follows in the area enclosed by the broken lines in Figures 5 5 and 5 6 to avoid an adverse effect from wiring capacitance Keep the wiring...

Page 110: ...ine VSS X1 X2 VSS X1 X2 PORTn n 0 to 3 5 c Wiring near high fluctuating current d Current flowing through ground line of oscillator potential at points A B and C fluctuates VSS X1 X2 High current VSS...

Page 111: ...d this do not lay the X1 and XT2 wires in parallel 5 4 3 Divider circuit The divider circuit divides the output of the main system clock oscillator fX to generate various clocks 5 4 4 When no subsyste...

Page 112: ...used with the main system clock selected In a system where no subsystem clock is used setting bit 1 FRC of the SCKM so that the on chip feedback resistor cannot be used reduces current consumption in...

Page 113: ...after the setting of PCC has been changed and the old clock is used for the duration of several instructions after that see Table 5 2 Table 5 2 Maximum Time Required for Switching CPU Clock Set Value...

Page 114: ...0 MHz operation 2 After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed has elapsed bit 1 PCC1 of the processor clock control register PCC and bi...

Page 115: ...Timer interrupt An interrupt is generated when a count value and compare value matches 2 Timer output Timer output can be controlled when a count value and compare value matches 3 Buzzer output Buzze...

Page 116: ...wing hardware Table 6 1 16 Bit Timer Configuration Item Configuration Timer counters 16 bits 1 TM90 Registers Compare register 16 bits 1 CR90 Capture register 16 bits 1 TCP90 Timer outputs 1 TO90 Cont...

Page 117: ...TM90 16 bit compare register 90 CR90 f X 2 2 f X 2 6 f X 2 7 f XT CTP90 INTP0 TI81 P30 TOC90 TCL901TCL900 TOE90 F F TOD90 P26 Output latch P21 Output latch PM26 PM21 TO90 P26 INTTM90 BZO90 P21 Match...

Page 118: ...M90 TM90 is used to count the number of pulses The contents of TM90 are read with an 8 bit or 16 bit memory manipulation instruction RESET input sets TM90 to 0000H Cautions 1 The count becomes undefin...

Page 119: ...ters 16 bit timer mode control register 90 TMC90 Buzzer output control register 90 BZC90 Port mode register 2 PM2 1 16 bit timer mode control register 90 TMC90 16 bit timer mode control register 90 TM...

Page 120: ...0 1 Timer output data inversion control Inversion disabled Inversion enabled TCL901 0 0 1 1 16 bit timer counter 90 count clock selection TCL900 0 1 0 1 TOE90 0 1 16 bit timer counter 90 output contro...

Page 121: ...4 88 kHz fcl 29 2 44 kHz fcl 210 1 22 kHz fcl 211 610 Hz fcl 212 305 Hz fcl 213 153 Hz fcl 24 4 88 kHz fcl 25 2 44 kHz fcl 28 305 Hz fcl 29 153 Hz fcl 210 76 Hz fcl 211 38 Hz fcl 212 19 Hz fcl 213 10...

Page 122: ...6 to 0 when pin P21 BZO90 is used for buzzer output reset the output latch of P26 and PM26 to 0 PM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM2 to FFH Figure 6 4...

Page 123: ...unt value of 16 bit timer counter 90 TM90 matches the value set in CR90 counting of TM90 continues and an interrupt request signal INTTM90 is generated Table 6 2 shows interval time and Figure 6 6 sho...

Page 124: ...0 124 Figure 6 6 Timing of Timer Interrupt Operation Count clock TM90 count value CR90 INTTM90 TO90 TOF90 0000H 0001H N FFFFH 0000H 0001H N FFFFH N N N N N Interrupt acknowledgement Interrupt acknowle...

Page 125: ...C90 Setting of count clock see Table 6 2 Inverse enable of timer output data TO90 output enable Caution If both the CPT901 flag and CPT900 flag are set to 0 the capture operation is prohibited When th...

Page 126: ...etected and latches and retains the count value of 16 bit timer register 90 The TCP90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection Table 6...

Page 127: ...M90 to 0000H and TM90 starts freerunning Figure 6 11 shows the timing of 16 bit timer counter 90 readout Cautions 1 The count value after releasing stop becomes undefined because the count operation i...

Page 128: ...quency see Table 6 4 Enables buzzer output Table 6 4 Buzzer Frequency of 16 Bit Timer Buzzer Frequency BCS902 BCS901 BCS900 fcl fX 2 2 fcl fX 2 6 fcl fX 2 7 fcl fXT 0 0 0 fcl 2 4 78 1 kHz fcl 2 4 4 88...

Page 129: ...clock is stopped 2 The read function of TM90 uses the CPU clock for control refer to Figure 6 1 and reads an undefined value when the CPU clock is slower than the count clock values are not guaranteed...

Page 130: ...Main system clock Oscillation stopped BZOE90 1 Buzzer output enabled At this time when the setting of P21 the buzzer output alternate function pin is PM21 0 P21 0 a square wave of the buzzer frequency...

Page 131: ...timer counter mode discrete mode The following functions can be used in this mode Interval timer with 8 bit resolution External event counter with 8 bit resolution timer 40 only Square wave output wit...

Page 132: ...as the timer output pin using software 7 2 8 Bit Timer Configuration The 8 bit timer includes the following hardware Table 7 2 8 Bit Timer Configuration Item Configuration Timer counters 8 bits 2 TM50...

Page 133: ...7 Timer 60 interrupt request signal from Figure 7 2 B Carrier clock in carrier generator mode or timer 60 output signal in a mode other than carrier generator mode from Figure 7 2 C Cascade connection...

Page 134: ...gister 60 TCA60 TO61 INTP3 P33 Prescaler Selector Count operation start signal to timer 50 in cascade connection mode To Figure 7 1 D TM50 match signal in cascade connection mode TM60 timer counter ma...

Page 135: ...e the CR50 with the TOE50 in a cleared status 2 If the valid edge of the count clock is selected for both edges in the PWM output mode TEG50 1 do not set 00H 01H and FFH to the CR50 If the rising edge...

Page 136: ...lue overflows ii TM60 After reset When TCE60 bit 7 of 8 bit timer mode control register 60 TMC60 is cleared to 0 When a match occurs between TM60 and CR60 When the TM60 count value overflows b Cascade...

Page 137: ...mode i TM50 After reset When the TCE50 flag is cleared to 0 When a match occurs between TM50 and CR50 When the TM50 count value overflows ii TM60 Reset When the TCE60 flag is cleared to 0 When a matc...

Page 138: ...TMC50 8 bit timer mode control register 60 TMC60 Carrier generator output control register 60 TCA60 Port mode register 3 PM3 1 8 bit timer mode control register 50 TMC50 8 bit timer mode control regis...

Page 139: ...or timer 60 output signal in a mode other than carrier generator mode Other than above Setting prohibited TMD501 TMD500 TMD601 TMD600 Selection of operation mode for timer 50 and timer 60 Note 2 0 0...

Page 140: ...the operation mode and the count clock 3 Start count operation Remarks 1 fX Main system clock oscillation frequency ceramic crystal oscillation 2 fCC Main system clock oscillation frequency RC oscilla...

Page 141: ...601 TMD600 Selection of operation mode for timer 50 and timer 60 Note 2 0 0 0 0 Discrete mode 8 bit timer counter mode 0 1 0 1 Cascade connection mode 16 bit timer counter mode 0 0 1 1 Carrier generat...

Page 142: ...required value to NRZ60 by program beforehand NRZ60 No return zero data 0 Outputs low level signal carrier clock is stopped 1 Outputs carrier pulse Caution TCA60 cannot be set with a 1 bit memory man...

Page 143: ...ate 8 bit timer n0 as an interval timer settings must be made in the following sequence 1 Disable operation of 8 bit timer counter n0 TMn0 TCEn0 0 2 Disable timer output of TOn0 TOEn0 0 3 Set a count...

Page 144: ...of timer 60 output Input cycle of timer 60 output 8 Input cycle of timer 60 Remarks 1 fX Main system clock oscillation frequency 2 fXT Subsystem clock oscillation frequency Table 7 4 Interval Time of...

Page 145: ...H N 00H 00H 01H 00H 01H Clear Clear Clear Count start Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement Interval time Interval time Interval time Remarks 1 Interval time N...

Page 146: ...01H 00H 01H 00H 01H 00H 01H FFH FFH FFH Clear Clear Clear Count start Remark n 5 6 nm 50 60 61 Figure 7 11 Timing of Interval Timer Operation with 8 Bit Resolution When CRn0 Changes from N to M N M C...

Page 147: ...7 12 Timing of Interval Timer Operation with 8 Bit Resolution When CRn0 Changes from N to M N M Count clock CRn0 TCEn0 INTTMn0 TOnm TMn0 00H 00H 00H N 1 N M N M N M 00H FFH M H Clear Clear Clear TMn0...

Page 148: ...t Resolution When Timer 60 Match Signal Is Selected for Timer 50 Count Clock Timer 60 count clock CR60 TCE60 INTTM60 TO60 TM60 N 00H M 00H 00H 01H M N M 00H M 00H 00H 01H Y 1 Y 00H Y 00H Y Input clock...

Page 149: ...TOE60 0 3 Set P31 to input mode PM31 1 4 Select the external input clock for timer 60 see Table 7 5 5 Set the operation mode of timer 60 to 8 bit timer counter mode see Figures 7 4 and 7 5 6 Set a cou...

Page 150: ...er s Manual U15075EJ1V0UM00 Figure 7 14 Timing of Operation of External Event Counter with 8 Bit Resolution TMI60 pin input TM60 count value CR60 TCE60 INTTM60 00H 01H 02H 03H 04H 05H N 1 N 00H 01H 02...

Page 151: ...cleared to 00H and continues counting At the same time an interrupt request signal INTTMn0 is generated The square wave output is cleared to 0 by setting TCEn0 to 0 Tables 7 5 and 7 6 show the square...

Page 152: ...ut cycle 2 8 fTMI 2 input cycle 1 0 0 fTMI 2 2 input cycle fTMI 2 2 input cycle 2 8 fTMI 2 2 input cycle 1 0 1 fTMI 2 3 input cycle fTMI 2 3 input cycle 2 8 fTMI 2 3 input cycle Remark fX Main system...

Page 153: ...nce 1 Disable operation of 8 bit timer counter 50 TM50 and 8 bit timer counter 60 TM60 TCE50 0 TCE60 0 2 Disable timer output of TO60 TOE60 0 3 Set the count clock for timer 60 see Tables 7 5 and 7 6...

Page 154: ...0 1 fX 0 2 s 2 16 fX 13 1 ms 1 fX 0 2 s 0 0 1 2 fX 0 4 s 2 17 fX 26 2 ms 2 fX 0 4 s 0 1 0 fTMI input cycle fTMI input cycle 2 16 fTMI input cycle 0 1 1 fTMI 2 input cycle fTMI 2 input cycle 2 16 fTMI...

Page 155: ...se TM50 00H X X 1 01H CR50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H t Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated...

Page 156: ...nd 8 bit timer 60 to 16 bit timer counter mode see Figures 7 4 and 7 5 6 Set a count value in CR50 and CR60 7 Enable the operation of TM50 and TM60 TCE60 1 Note Note Start and clear of the timer in th...

Page 157: ...TM50 00H X 01H CR50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H X 1 Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated beca...

Page 158: ...ively the TO60 pin output will be inverted Through application of this mechanism square waves of any frequency can be output As soon as a match occurs TM50 and TM60 are cleared to 00H and counting con...

Page 159: ...X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated because TM50 does not match...

Page 160: ...e the operation of TM50 and TM60 TCE50 1 TCE60 1 The operation of the carrier generator is as follows 1 When the count value of TM60 matches the value set in CR60 an interrupt request signal INTTM60 i...

Page 161: ...hen CR60 N CRH60 M M N Count clock TM60 count value CR60 TCE60 INTTM60 M 00H N 00H 01H N CRH60 M N 00H Carrier clock N 00H 00H N M 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TM50 CR50 TCE50 INTTM50 C...

Page 162: ...Phases of Carrier Clock and NRZ60 Are Asynchronous Count clock TM60 count value CR60 TCE60 INTTM60 N 00H N CRH60 M Carrier clock N 00H 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TM50 CR50 TCE50 INTTM...

Page 163: ...hen CR60 CRH60 N Count clock TM60 count value CR60 TCE60 INTTM60 N 00H 00H 00H N CRH60 N N Carrier clock 00H 00H N N 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TM50 CR50 TCE50 INTTM50 Count pulse 0 1...

Page 164: ...peration mode of timer 50 to the PWM free running mode see Figure 7 4 5 Set the count clock for timer 50 6 Set P31 to the output mode PM31 0 and the P31 output latch to 0 and enable timer output of TO...

Page 165: ...flow Overflow Count start Caution When the rising edge is selected do not set the CR50 to 00H If the CR50 is set to 00H PWM output may not be performed normally Figure 7 23 Operation Timing When Overw...

Page 166: ...TO50 N TM50 N 00H 00H 00H 01H FFH FFH 01H 01H 02H 01H Overflow Overflow Overflow Count start CR50 overwrite Overflow occurs but no change takes place because TO50 is high level Figure 7 24 Operation T...

Page 167: ...00H Overflow Overflow Overflow Count start Caution When both edges are selected do not set CR50 to 00H 01H and FFH If the CR50 is set to these values PWM output may not be performed normally Figure 7...

Page 168: ...of TO60 TOE60 1 7 Enable the operation of TM60 TCE60 1 The operation in the PWM output mode is as follows 1 When the count value of TM60 matches the value set in CR60 an interrupt request signal INTTM...

Page 169: ...1H 01H M 00H Clear Clear Clear Clear Count start Note The initial value of TO60 is low level when output is enabled TOE60 1 Figure 7 27 PWM Output Mode Timing When CR60 and CRH60 Are Overwritten Count...

Page 170: ...d asynchronously to the count pulse Figure 7 28 Start Timing of 8 Bit Timer Counter Count pulse TMn0 count value 00H 01H 02H 03H 04H Timer start Remark n 5 6 2 Setting of 8 bit compare register n0 8 b...

Page 171: ...The watch and interval timers can be used at the same time Figure 8 1 is a block diagram of the watch timer Figure 8 1 Block Diagram of Watch Timer fX 27 fXT fW fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 Cl...

Page 172: ...ecified intervals Table 8 1 Interval Generated Using the Interval Timer Interval At fX 5 0 MHz At fX 4 19 MHz At fXT 32 768 kHz 2 4 1 fW 409 6 s 489 s 488 s 2 5 1 fW 819 2 s 978 s 977 s 2 6 1 fW 1 64...

Page 173: ...imer count clock selection WTM7 Prescaler interval selection WTM6 0 0 0 0 1 1 24 fW 488 s 25 fW 977 s 26 fW 1 95 ms 27 fW 3 91 ms 28 fW 7 81 ms 29 fW 15 6 ms WTM5 0 0 1 1 0 0 WTM4 0 1 0 1 0 1 Control...

Page 174: ...up to 29 1 fW seconds may occur in the overflow INTWT after the zero second start of the watch timer because the 9 bit prescaler is not cleared to 0 8 4 2 Operation as interval timer The interval time...

Page 175: ...bit counter operation is enabled by setting bit 0 WTM0 of the watch mode timer mode control register WTM to 1 the interval until the first interrupt request INTWT is generated after the register is se...

Page 176: ...User s Manual U15075EJ1V0UM00 176 MEMO...

Page 177: ...way When a runaway is detected a non maskable interrupt or the RESET signal can be generated Table 9 1 Watchdog Timer Runaway Detection Time Runaway Detection Time At fX 5 0 MHz 2 11 1 fX 410 s 2 13 1...

Page 178: ...Watchdog timer clock select register WDCS Watchdog timer mode register WDTM Figure 9 1 Block Diagram of Watchdog Timer Internal bus Internal bus Prescaler Selector Controller fX 26 fX 28 fX 210 3 7 bi...

Page 179: ...manipulation instruction RESET input sets WDCS to 00H Figure 9 2 Format of Watchdog Timer Clock Select Register WDCS2 0 0 1 1 WDCS1 0 1 0 1 fX 24 fX 26 fX 28 fX 210 312 5 kHz 78 1 kHz 19 5 kHz 4 88 kH...

Page 180: ...e 2 Starts reset operation upon overflow occurrence 0 0 RUN 0 0 WDTM4 WDTM3 0 0 0 WDTM 7 6 5 4 Symbol Address After reset R W FFF9H 00H R W 3 2 1 0 Notes 1 Once RUN has been set 1 it cannot be cleared...

Page 181: ...and the runaway detection time is exceeded a system reset signal or a non maskable interrupt is generated depending on the value of bit 3 WDTM3 of WDTM The watchdog timer continues operation in HALT m...

Page 182: ...upt mask flag WDTMK is valid and a maskable interrupt INTWDT can be generated The priority of INTWDT is set as the highest of all the maskable interrupts The interval timer continues operation in HALT...

Page 183: ...og inputs ANI0 to ANI5 is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTAD0 being issued each time A D conversion is complete 10 2 8 Bit A D Converter...

Page 184: ...a voltage tap comparison voltage received from the series resistor string starting from the most significant bit MSB Upon receiving all the bits down to the least significant bit LSB that is upon the...

Page 185: ...version Caution Do not supply pins ANI0 to ANI5 with voltages that fall outside the rated range If a voltage greater than AVDD or less than AVSS even if within the absolute maximum rating is applied t...

Page 186: ...te 1 FR02 0 0 0 1 1 1 144 fX 120 fX 96 fX 72 fX 60 fX 48 fX FR01 0 0 1 0 0 1 28 8 s 24 s 19 2 s 14 4 s Setting prohibitedNote 2 Setting prohibitedNote 2 FR00 0 1 0 0 1 0 Other than above Conversion di...

Page 187: ...is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADS0 to 00H Figure 10 3 Format of Analog Input Channel Specification Register 0 0 0 0 0 0 ADS02 ADS01 ADS00 ADS0 Symbol A...

Page 188: ...AVDD the MSB of SAR is left set If it is lower than half of AVDD the MSB is reset 6 Bit 6 of SAR is set automatically and comparison shifts to the next stage The next tap voltage of the series resist...

Page 189: ...rsion is canceled In this case A D conversion is restarted from the beginning if ADCS0 is set 1 RESET input makes A D conversion result register 0 ADCR0 undefined 10 4 2 Input voltage and conversion r...

Page 190: ...User s Manual U15075EJ1V0UM00 190 Figure 10 5 Relationship Between Analog Input Voltage and A D Conversion Result 255 254 253 3 2 1 0 A D conversion result ADCR0 1 512 1 256 3 512 2 256 5 512 3 256 5...

Page 191: ...fied in analog input channel specification register 0 ADS0 Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCR0 At the same time an interrupt requ...

Page 192: ...to a conversion channel the conversion output of the channel becomes undefined which may affect the conversion output of the other channels 3 Conflict 1 Conflict between writing to A D conversion resu...

Page 193: ...operation has been stopped stop the A D conversion operation before the next conversion operation is completed Figures 10 8 and 10 9 show the timing at which the conversion result is read Figure 10 8...

Page 194: ...ion do not execute input instructions for the ports otherwise the conversion resolution may be reduced If a digital pulse is applied to a pin adjacent to the analog input pins during A D conversion co...

Page 195: ...to the analog circuit It is also used to supply power to the ANI0 to ANI5 input circuit If your application is designed to be changed to backup power the AVDD pin must be supplied with the same volta...

Page 196: ...User s Manual U15075EJ1V0UM00 196 MEMO...

Page 197: ...og inputs ANI0 to ANI5 is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTAD0 being issued each time A D conversion is complete 11 2 10 Bit A D Converte...

Page 198: ...own to the least significant bit LSB that is upon the completion of A D conversion the SAR sends its contents to A D conversion result register 0 ADCR0 2 A D conversion result register 0 ADCR0 ADCR0 h...

Page 199: ...e the 6 channel analog input pins for the A D converter They are used to receive the analog signals for A D conversion Caution Do not supply pins ANI0 to ANI5 with voltages that fall outside the rated...

Page 200: ...Note 1 FR02 0 0 0 1 1 1 144 fX 120 fX 96 fX 72 fX 60 fX 48 fX FR01 0 0 1 0 0 1 28 8 s 24 s 19 2 s 14 4 s Setting prohibitedNote 2 Setting prohibitedNote 2 FR00 0 1 0 0 1 0 Other than above Conversion...

Page 201: ...is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ADS0 to 00H Figure 11 3 Format of Analog Input Channel Specification Register 0 0 0 0 0 0 ADS02 ADS01 ADS00 ADS0 Symbol...

Page 202: ...f AVDD the MSB of SAR is left set If it is lower than half of AVDD the MSB is reset 6 Bit 8 of SAR is set automatically and comparison shifts to the next stage The next tap voltage of the series resis...

Page 203: ...canceled In this case A D conversion is restarted from the beginning if ADCS0 is set 1 RESET input makes A D conversion result register 0 ADCR0 undefined 11 4 2 Input voltage and conversion result The...

Page 204: ...anual U15075EJ1V0UM00 204 Figure 11 5 Relationship Between Analog Input Voltage and A D Conversion Result 1023 1022 1021 3 2 1 0 A D conversion result ADCR0 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2...

Page 205: ...in specified in A D input selection register 0 ADS0 Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCR0 At the same time an interrupt request sig...

Page 206: ...nto a conversion channel the conversion output of the channel becomes undefined which may affect the conversion output of the other channels 3 Conflict 1 Conflict between writing to A D conversion res...

Page 207: ...operation has been stopped stop the A D conversion operation before the next conversion operation is completed Figures 11 8 and 11 9 show the timing at which the conversion result is read Figure 11 8...

Page 208: ...sion do not execute input instructions for the ports otherwise the conversion resolution may be reduced If a digital pulse is applied to a pin adjacent to the analog input pins during A D conversion c...

Page 209: ...r to the analog circuit It is also used to supply power to the ANI0 to ANI5 input circuit If your application is designed to be changed to backup power the AVDD pin must be supplied with the same volt...

Page 210: ...User s Manual U15075EJ1V0UM00 210 MEMO...

Page 211: ...ines SI20 and SO20 As it supports simultaneous transmission and reception 3 wire serial I O mode requires less processing time for data transmission than asynchronous serial interface mode Because in...

Page 212: ...ft clock SI20 P25 RxD20 SO20 P24 TxD20 4 Parity operation Stop bit addition Reception data counter Parity operation Stop bit addition Transmission data counter SL20 CL20 PS200 PS201 Reception enabled...

Page 213: ...eption detected TXE20 RXE20 CSIE20 Selector Selector Selector 1 2 1 2 Transmission clock counter Reception clock counter 4 f X 2 f X 2 3 f X 2 4 f X 2 5 f X 2 6 f X 2 7 f X 2 8 f X 2 2 SCK20 ASCK20 P2...

Page 214: ...Reception buffer register 20 RXB20 RXB20 holds a reception data A new reception data is transferred from reception shift register 20 RXS20 every 1 byte data reception When the data length is seven bit...

Page 215: ...E20 0 0 DAP20 DIR20 CSCK20 CKP20 CSIM20 Symbol Address After reset R W FF72H 00H R W 7 6 5 4 3 2 1 0 Operation disabled Operation enabled DIR20 0 1 First bit specification MSB LSB CSCK20 0 1 3 wire se...

Page 216: ...reset R W FF70H 00H R W 7 6 5 4 3 2 1 0 Transmit operation stop Transmit operation enable RXE20 0 1 Receive operation control Receive operation stop Receive operation enable PS201 0 0 1 1 Parity bit...

Page 217: ...ock SCK20 output 0 1 External clock SCK20 input 0 0 1 1 1 Note 2 Note 2 0 1 0 1 LSB Internal clock SI20 Note 2 SO20 CMOS output SCK20 output Other than above Setting prohibited 3 Asynchronous serial i...

Page 218: ...2 1 0 No parity error has occurred A parity error has occurred when the parity of transmit data does not match FE20 0 1 Flaming error flag No framing error has occurred A framing error has occurred wh...

Page 219: ...rohibited 2 5 MHz 1 25 MHz 625 kHz 313 kHz 156 kHz 78 1 kHz 39 1 kHz 19 5 kHz Other than above TPS201 0 0 1 1 0 0 1 1 0 TPS200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 Note An external clock can be used on...

Page 220: ...of a clock generated from the system clock is estimated by using the following expression Baud rate Hz fX Main system clock oscillation frequency n Values in Figure 12 6 determined by the values of TP...

Page 221: ...aud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression Baud rate Hz fASCK Frequency of clock input to the ASCK20 pin Table 12 4 Relationshi...

Page 222: ...D20 and P25 SI20 RxD20 pins can be used as normal I O ports 1 Register setting Operation stop mode is set by serial operation mode register 20 CSIM20 and asynchronous serial interface mode register 20...

Page 223: ...ation instruction RESET input sets ASIM20 to 00H TXE20 0 1 Transmit operation control Transmit operation stopped Transmit operation enabled Receive operation stopped Receive operation enabled RXE20 0...

Page 224: ...bles communications at the desired baud rate In addition the baud rate can also be defined by dividing the clock input to the ASCK20 pin The UART dedicated baud rate generator also can output the 31 2...

Page 225: ...specification MSB LSB CSCK20 0 1 3 wire serial I O mode clock selection External clock input to the SCK20 pin Output of the dedicated baud rate generator SSE20 0 1 Not used Used DAP20 0 1 3 wire seria...

Page 226: ...0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Odd parity Even parity Receive operation control PS201 Pa...

Page 227: ...verrun error has occured An overrun error has occuredNote 2 when the next receive operation is completed before data is read from reception buffer register 20 FE20 0 1 0 1 Framing error flag Overrun e...

Page 228: ...PS203 TPS202 TPS201 TPS200 0 0 0 0 BRGC20 7 6 5 4 Symbol Address After reset R W FF73H 00H R W 3 2 1 0 Note Can only be used in the UART mode Cautions 1 When writing to BRGC20 during a communication o...

Page 229: ...a clock generated from the system clock is estimated by using the following expression Baud rate Hz fX Main system clock oscillation frequency n Values in the above table determined by the settings of...

Page 230: ...e baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression Baud rate Hz fASCK Frequency of clock input to ASCK20 pin Table 12 6 Relationship...

Page 231: ...mit Receive Data D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Start bit One data frame Start bits 1 bit Character bits 7 bits 8 bits Parity bits Even parity odd parity 0 parity no parity Stop bits 1 bi...

Page 232: ...parity bit is counted and if the number is odd a parity error occurs ii Odd parity At transmission Conversely to the even parity the parity bit is determined so that the number of bits with a value o...

Page 233: ...Transmission Completion Interrupt Timing a Stop bit length 1 STOP Parity D7 D6 D2 D1 D0 START TxD20 output INTST20 b Stop bit length 2 STOP Parity D7 D6 D2 D1 D0 START TxD20 output INTST20 Caution Do...

Page 234: ...cted after the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to reception buffer register 20 RXB20 and a...

Page 235: ...et Table 12 7 Receive Error Causes Receive Errors Cause Parity error Transmission time parity and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next...

Page 236: ...bit 6 RXE20 of asynchronous serial interface mode register 20 ASIM20 is cleared during reception reception buffer register 20 RXB20 and the receive completion interrupt INTSR20 are as follows Parity R...

Page 237: ...tion RESET input sets CSIM20 to 00H CSIE20 0 1 3 wire serial I O mode operation control CSIE20 SSE20 0 0 DAP20 DIR20 CSCK20 CKP20 CSIM20 Symbol Address After reset R W FF72H 00H R W 7 6 5 4 3 2 1 0 Op...

Page 238: ...ceive operation enabled RXE20 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error occurs Odd parity Even parity Receive ope...

Page 239: ...and communications cannot be performed normally Be sure not to write to BRGC20 during a communication operation 2 Be sure not to select n 1 during operation at fX 5 0 MHz because the resulting baud ra...

Page 240: ...Then transmit data is held in the SO20 latch and output from the SO20 pin Also receive data input to the SI20 pin is latched in the reception buffer register RXB20 SIO20 on the rise of SCK20 At the en...

Page 241: ...O0 SCK20 SI20 Note SO20 SIO20 write INTCSI20 Note The value of the last bit previously output is output iii Slave operation when DAP20 0 CKP20 0 SSE20 1 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0...

Page 242: ...O0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SCK20 SO20 SI20 SIO20 write INTCSI20 v Slave operation when DAP20 0 CKP20 1 SSE20 0 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 S...

Page 243: ...te SS20 INTCSI20 DO0 SIO20 write master Note 1 Notes 1 The data of SI20 is loaded at the first rising edge of SCK20 Make sure that the master outputs the first bit before the first rising of SCK20 2 S...

Page 244: ...K20 Make sure that the master outputs the first bit before the first falling of SCK20 ix Slave operation when DAP20 1 CKP20 0 SSE20 1 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO...

Page 245: ...DO6 DO5 DO4 DO3 DO2 DO1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 SCK20 SO20 SI20 SIO20 write INTCSI20 DI0 DO0 Note The value of the last bit previously output is output xi Slave operation when DAP20 1 CKP20 1 SSE2...

Page 246: ...until SS20 rises When SS20 is high SO20 is in a high impedance state 3 Transfer start Serial transfer is started by setting transfer data to the transmission shift register TXS20 SIO20 when the follo...

Page 247: ...ent Outputs and Maximum Number of Pixels Bias Method Time Slots Common Signals Used Maximum Number of Segments Maximum Number of Pixels 3 COM0 to COM2 15 5 segments 3 commons PD789426 789436 Subseries...

Page 248: ...LCDM02 LCDM01 LCDM00 LCD display mode register 0 LCDM0 LCD drive voltage controller V LC2 V LC1 V LC0 Segment driver Common driver COM0 COM1 COM2 COM3 3 3 2 1 0 3 2 1 0 6 5 7 4 FA00H Display data memo...

Page 249: ...LCD clock control register 0 LCDC0 LCD voltage amplification control register 0 LCDVA0 1 LCD display mode register 0 LCDM0 LCDM0 specifies whether to enable display operation It also specifies the op...

Page 250: ...mode 1 3 1 3 Note When the LCD display panel is not used the VAON0 and LIPS0 must be set to 0 to reduce power consumption Cautions 1 Bits 1 to 3 and 5 must be set to 0 2 When operating VAON0 follow t...

Page 251: ...26 78 1 kHz fX 27 39 1 kHz Note Specify an internal clock fLCD frequency of at least 32 kHz Cautions 1 Bits 4 to 7 must be set to 0 2 Before changing the LCDC0 setting be sure to stop voltage amplifi...

Page 252: ...DVA0 Symbol Address After reset R W FFB3H 00H R W 7 6 5 4 3 2 1 0 GAIN 0 1 1 5 times specification of the LCD panel used is 4 5 V 1 0 times specification of the LCD panel used is 3 V 0 0 0 0 0 0 Refer...

Page 253: ...tential 7 Start output corresponding to each data memory by setting LCDON0 bit 7 of LCDM0 LCDON0 1 13 5 LCD Display Data Memory The LCD display data memory is mapped at addresses FA00H to FA0EH Data i...

Page 254: ...ively If the contents of each bit are 1 it is converted to the select voltage and if 0 it is converted to the deselect voltage The conversion results are output to the segment pins Check with the info...

Page 255: ...t signals Figure 13 6 Common Signal Waveforms COMn Three time slot mode TF 3 T VLC0 VSS VLCD VLC1 VLC2 TF 4 T COMn Four time slot mode VLC0 VLCD VLC1 VLC2 VSS T One LCD clock period TF Frame frequency...

Page 256: ...ssary to apply the select or deselect voltage to the S6 to S8 pins according to Table 13 6 at the timing of the common signals COM0 to COM2 Table 13 6 Select and Deselect Voltages COM0 to COM2 Segment...

Page 257: ...1 1 0 0 1 0 Bit 0 Bit 1 Bit 2 Bit 3 Timing strobe Data memory address LCD panel FA00H 1 2 3 4 5 6 7 8 9 A B C D E S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 COM 3 COM 2 COM 1 CO...

Page 258: ...Figure 13 10 Three Time Slot LCD Drive Waveform Examples VLC0 VLC2 COM0 VLCD 0 COM0 S6 VLCD VLC1 1 3VLCD 1 3VLCD VSS0 VLC0 VLC2 COM1 VLC1 VSS0 VLC0 VLC2 COM2 VLC1 VSS0 VLC0 VLC2 S6 VLC1 VSS0 VLCD 0 C...

Page 259: ...ltage to the S2 and S3 pins according to Table 13 7 at the timing of the common signals COM0 to COM3 Table 13 7 Select and Deselect Voltages COM0 to COM3 Segment Common S2 S3 COM0 Select Select COM1 D...

Page 260: ...ur Time Slot LCD Panel 0 0 0 1 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 Bit 0 Bit 1 Bit 2 Bit 3 Timing strobe Data memory address LCD pan...

Page 261: ...UM00 261 Figure 13 13 Four Time Slot LCD Drive Waveform Examples TF VLC0 VLC2 COM0 VLCD 0 COM0 S2 VLCD VLC1 1 3VLCD 1 3VLCD VSS VLC0 VLC2 COM1 VLC1 VSS VLC0 VLC2 COM2 VLC1 VSS VLC0 VLC2 COM3 VLC1 VSS...

Page 262: ...262 User s Manual U15075EJ1V0UM00 MEMO...

Page 263: ...ted One interrupt source from the watchdog timer is incorporated as a non maskable interrupt 2 Maskable interrupt This interrupt undergoes mask control If two or more interrupts with the same priority...

Page 264: ...of serial interface 20 UART transmission 0012H 7 INTWTI Interval timer interrupt 0014H 8 INTTM90 Generation of match signal of 16 bit timer 90 0016H 9 INTTM50 Generation of match signal of 8 bit timer...

Page 265: ...ble interrupt MK IF IE Internal bus Interrupt request Vector table address generator Standby release signal C External maskable interrupt MK IF IE Internal bus INTM0 INTM1 KRM00 Interrupt request Edge...

Page 266: ...ey return mode register 00 KRM00 Table 14 2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests Table 14 2 Flags Corresponding to Interrupt Requ...

Page 267: ...IF IF1 FFE1H 00H R W Interrupt request flag No interrupt request signal is generated Interrupt request signal is generated Interrupt request state XXIFX 6 5 4 3 2 1 7 0 STIF20 0 SRIF20 PIF3 PIF2 PIF1...

Page 268: ...rvicing control Interrupt servicing enabled Interrupt servicing disabled 6 5 4 3 2 1 7 0 XXMK STMK20 1 SRMK20 PMK3 PMK2 PMK1 PMK0 WDTMK MK0 R W FFE4H FFH R W Symbol Address After reset 6 5 4 3 2 1 7 0...

Page 269: ...1 1 0 1 0 1 Symbol Address After reset INTP0 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges INTP1 valid edge selection Falling edge Rising edge Setting...

Page 270: ...sable interrupts After that clear 0 PIF3 then set PMK3 to 0 to enable interrupts 5 Program status word PSW The program status word is a register used to hold the instruction execution result and the c...

Page 271: ...Symbol Cautions 1 Bits 1 to 7 must be set to 0 2 Before setting KRM00 always set bit 6 of MK1 KRMK00 1 to disable interrupts After setting KRM00 clear KRMK00 after clearing bit 6 of IF1 KRIF00 0 to e...

Page 272: ...stack in that order the IE flag is reset to 0 the contents of the vector table are loaded to the PC and then program execution branches Figure 14 9 shows the flow from non maskable interrupt request g...

Page 273: ...enerated Interrupt servicing starts WDTM3 0 non maskable interrupt is selected WDTM Watchdog timer mode register WDT Watchdog timer Figure 14 10 Timing of Non Maskable Interrupt Request Acknowledgment...

Page 274: ...1 clock fCPU CPU clock When two or more maskable interrupt requests are generated at the same time they are acknowledged starting from the one assigned the highest priority by the priority specificati...

Page 275: ...in Final Clock Under Execution Clock CPU NOP MOV A r Saving PSW and PC and jump to interrupt servicing Interrupt servicing program Interrupt 8 clocks If the interrupt request flag XXIF is generated in...

Page 276: ...quest is acknowledged the EI instruction is issued and the interrupt request is enabled Example 2 Multiple interrupts are not performed because interrupts are disabled INTyy EI Main servicing RETI INT...

Page 277: ...rrupt is generated when a certain type of instruction is being executed the interrupt request will not be acknowledged until the instruction is completed Such instructions interrupt request pending in...

Page 278: ...278 User s Manual U15075EJ1V0UM00 MEMO...

Page 279: ...ps the entire system The power consumption of the CPU can be substantially reduced in this mode The data memory can be retained at the low voltage VDD 1 8 V Therefore this mode is useful for retaining...

Page 280: ...ime Select Register OSTS2 0 0 1 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS R W FFFAH 04H R W 7 6 5 4 3 2 1 0 OSTS1 0 1 0 212 fX 215 fX 217 fX 819 s 6 55 ms 26 2 ms OSTS0 0 0 0 Setting prohibited Symbol Address...

Page 281: ...16 bit timer Operation enabled Operation stopped TM50 Operation enabled Note1 8 bit timer TM60 Operation enabled Operation enabled Note2 Watch timer Operation enabled Operation enabled Note3 Operatio...

Page 282: ...s executed Figure 15 2 Releasing HALT Mode by Interrupt HALT instruction Standby release signal Wait Wait HALT mode Operation mode Operation mode Clock Oscillation Remarks 1 The broken line indicates...

Page 283: ...ion RESET signal Wait 215 fX 6 55 ms Reset period HALT mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation Remark fX Main system cl...

Page 284: ...ystem Clock Is Running Item While the subsystem clock is running While the subsystem clock is not running Main system clock Oscillation stopped CPU Operation stopped Port output latch Remains in the s...

Page 285: ...red interrupt processing is performed after the oscillation stabilization time has elapsed If the interrupt is disabled the instruction at the next address is executed Figure 15 4 Releasing STOP Mode...

Page 286: ...ut STOP instruction RESET signal Wait STOP mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation Reset period Remark fX Main system c...

Page 287: ...r during oscillation stabilization time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution is started after the oscillation stabilization tim...

Page 288: ...erflow in Watchdog Timer X1 Overflow in watchdog timer Internal reset signal Port pin Hi Z During normal operation Reset period oscillation continues Normal operation reset processing Oscillation stab...

Page 289: ...gister CR90 FFFFH Control register TMC90 00H 16 bit timer Capture register TCP90 Undefined Timer counter TM50 TM60 00H Compare register CR50 CR60 CRH60 Undefined 8 bit timer Mode control register TMC5...

Page 290: ...tatus After Reset Display mode register LCDM0 00H Clock control register LCDC0 00H LCD controller driver Voltage amplification control register LCDVA0 00H Request flag register IF0 IF1 00H Mask flag r...

Page 291: ...Versions Flash Memory Version Mask ROM Version Part Number Item PD78F9436 PD78F9456 PD789425 789435 PD789426 789436 PD789445 789455 PD789446 789456 ROM 12 KB 16 KB 12 KB 16 KB 12 KB 16 KB High speed R...

Page 292: ...tion mode The flash memory is written by using Flashpro III and by means of serial communication Select a communication mode from those listed in Table 17 2 To select a communication mode the format s...

Page 293: ...ck Checks erased state of entire memory Data write Write to flash memory based on write start address and number of data written number of bytes Batch verify Compares all contents of memory with input...

Page 294: ...6 78F9456 294 User s Manual U15075EJ1V0UM00 Figure 17 3 Flashpro III Connection Example in UART Mode VPPnNote VDD RESET SI SO GND VPP VDD AVDD RESET CLK X1 RxD20 TxD20 VSS AVSS Flashpro III PD78F9436...

Page 295: ...s Note 1 COMM PORT SIO ch0 On Target Board CPU CLK In Flashpro On Target Board 4 1943 MHz SIO CLK 1 0 MHz In Flashpro 4 0 MHz 3 wire serial I O SIO CLK 1 0 MHz 0 COMM PORT UART ch0 CPU CLK On Target B...

Page 296: ...296 User s Manual U15075EJ1V0UM00 MEMO...

Page 297: ...3 Whether a pull up resistor is to be incorporated can be specified in 1 bit units For P50 to P53 port 5 a mask option is used to specify whether a pull up resistor is to be incorporated The mask opti...

Page 298: ...User s Manual U15075EJ1V0UM00 298 MEMO...

Page 299: ...ecification Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register id...

Page 300: ...flag AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag NMIS Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents i...

Page 301: ...A 2 4 sfr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte x x x A PSW 2 4 A PSW PSW A 2 4 PSW A x x x A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL by...

Page 302: ...HL byte 2 6 A CY A HL byte x x x ADDC A byte 2 4 A CY A byte CY x x x saddr byte 3 6 saddr CY saddr byte CY x x x A r 2 4 A CY A r CY x x x A saddr 2 4 A CY A saddr CY x x x A addr16 3 8 A CY A addr16...

Page 303: ...dr saddr byte x A r 2 4 A A r x A saddr 2 4 A A saddr x A addr16 3 8 A A addr16 x A HL 1 6 A A HL x A HL byte 2 6 A A HL byte x OR A byte 2 4 A A byte x saddr byte 3 6 saddr saddr byte x A r 2 4 A A r...

Page 304: ...x DEC r 2 4 r r 1 x x saddr 2 4 saddr saddr 1 x x INCW rp 1 4 rp rp 1 DECW rp 1 4 rp rp 1 ROR A 1 1 2 CY A7 A0 Am 1 Am 1 x ROL A 1 1 2 CY A0 A7 Am 1 Am 1 x RORC A 1 1 2 CY A0 A7 CY Am 1 Am 1 x ROLC A...

Page 305: ...addr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 BT saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 j...

Page 306: ...te addr16 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote XCHNote ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH M...

Page 307: ...ote saddrp SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW SP MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd...

Page 308: ...0UM00 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand 1st Operand AX addr16 addr5 addr16 Basic Instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound Instructions...

Page 309: ...ubseries Figure A 1 shows development tools Support to PC98 NX Series Unless specified otherwise the products supported by IBM PC AT compatibles can be used in PC98 NX Series When using the PC98 NX Se...

Page 310: ...compiler package System simulator Device file C compiler source file Integrated debugger Embedded software OS Host machine PC or EWS Interface adapter In circuit emulator Emulation board Emulation pr...

Page 311: ...mbler package CC78K0S C compiler package Part number S CC78K0S File containing the information inherent to the device Used in combination with optional RA78K0S CC78K0S and SM78K0S DF789456 Note Device...

Page 312: ...rammer Dedicated flash programmer for microcomputers incorporating flash memory FA 64GK Flash memory writing adapter Adapter for writing to flash memory and connected to Flashpro III FA 64GK for 64 pi...

Page 313: ...ter necessary when using IBM PC AT compatible as host machine of IE 78K0S NS ISA bus supported IE 70000 PCI IF Interface adapter Adapter necessary when using personal computer incorporating PCI bus as...

Page 314: ...S ID78K0S NS Host Machine OS Supply Media AA13 PC 9800 series Japanese Windows Note 3 5 2HD FD AB13 Japanese Windows Note BB13 IBM PC AT compatibles English Windows Note 3 5 2HC FD Note Also operates...

Page 315: ...execution sequences are controlled to switch the task to be executed next Caution when used under PC environment The MX78K0S is a DOS based application Use this software in the DOS prompt when running...

Page 316: ...User s Manual U15075EJ1V0UM00 316 MEMO...

Page 317: ...register 60 TCA60 142 E 8 bit compare register 50 CR50 135 8 bit compare register 60 CR60 135 8 bit compare register H60 CRH60 135 8 bit timer counter 50 TM50 136 8 bit timer counter 60 TM60 136 8 bit...

Page 318: ...resistor option register B2 PUB2 99 Pull up resistor option register B3 PUB3 99 Pull up resistor option register B7 PUB7 100 Pull up resistor option register B8 PUB8 100 Pull up resistor option regis...

Page 319: ...8 bit compare register 60 135 CR90 16 bit compare register 90 118 CRH60 8 bit compare register H60 135 CSIM20 Serial operation mode register 20 215 222 225 237 CSS Subclock control register 107 I IF0...

Page 320: ...egister B3 99 PUB7 Pull up resistor option register B7 100 PUB8 Pull up resistor option register B8 100 PUB9 Pull up resistor option register B9 101 R RXB20 Receive buffer register 20 214 S SCKM Subos...

Page 321: ...02 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 2...

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