CHAPTER 7 8-BIT TIMER
User’s Manual U15075EJ1V0UM00
133
TEG50
TCL500
TCL501
8-bit timer mode
control register 50
(TMC50)
Decoder
Selector
8-bit compare
register 50 (CR50)
8-bit timer counter 50
(TM50)
From Figure 7-2 (E)
Timer 60 match signal
(in cascade connection mode)
From Figure 7-2 (D)
Count operation start signal
(in cascade connection mode)
INTTM50
f
X
/2
3
f
X
/2
7
Timer 60 interrupt request signal
(from Figure 7-2 (B))
Carrier clock
(in carrier generator mode)
or timer 60 output signal
(in a mode other than carrier generator mode)
(from Figure 7-2 (C))
Cascade connection
mode
Match
Internal bus
OVF
Bit 7 of TM60
(from Figure 7-2 (A))
TOE50
P31
output latch
PM31
To Figure 7-2 (F)
Timer 50 match signal
(in cascade connection mode)
TO50/TMI60/INTP1/P31
TCE50
TCL502
f
X
f
XT
TMD500
TMD501
S
Q
IN
R
Q
CK
Clear
PWM mode
To Figure 7-2 (G)
Timer 50 match signal
(in carrier generator mode)
Selector
Selector
Figure 7-1. Block Diagram of Timer 50
Summary of Contents for mPD789426 Series
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