CHAPTER 5 CLOCK GENERATOR
User’s Manual U15075EJ1V0UM00
107
(3)
Subclock control register (CSS)
CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the
CPU clock operation status.
CSS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSS to 00H.
Figure 5-4. Format of Subclock Control Register
CPU clock operation status
0
0
CLS
CSS0
0
0
0
0
CSS
Address
After reset
R/W
FFF2H
00H
R/W
7
6
5
4
3
2
1
0
CLS
0
1
Operation based on the output of the (divided) main system clock
Operation based on the subsystem clock
Selection of the main system or subsystem clock oscillator
CSS0
0
1
(Divided) output from the main system clock oscillator
Output from the subsystem clock oscillator
Symbol
Note
Note
Bit 5 is read only.
Caution
Bits 0 to 3, 6, and 7 must be set to 0.
Summary of Contents for mPD789426 Series
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