NEC mPD789425, User Manual

Page: 114 / 321

CHAPTER 5 CLOCK GENERATOR
114
User’s Manual U15075EJ1V0UM00
5.6.2 Switching between system clock and CPU clock
The following figure illustrates how the CPU clock and system clock switch.
Figure 5-8. Switching Between System Clock and CPU Clock
System clock
CPU clock
Interrupt request signal
RESET
V
DD
f
X
f
X
f
XT
f
X
Low-speed
operation High-speed
operation
Subsystem clock
operation
High-speed operation
Wait (6.55 ms: at 5.0 MHz operation)
Internal reset operation
<1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released
when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the
oscillation stabilization time (2
15
/f
X
) is automatically secured.
After that, the CPU starts instruction execution at the slow speed of the main system clock (1.6
µ
s: at
5.0 MHz operation).
<2> After the time required for the V
DD
voltage to rise to the level at which the CPU can operate at high speed
has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock
control register (CSS) are rewritten so that high-speed operation can be selected.
<3> A drop of the V
DD
voltage is detected with an interrupt request signal. The clock is switched to the
subsystem clock (at this moment, the subsystem clock must be in the oscillation stabilization status).
<4> A recover of the V
DD
voltage is detected with an interrupt request signal. Bit 7 (MCC) of PCC is set to 0, and
then the main system clock starts oscillating. After the time required for the oscillation to stabilize has
elapsed, PCC1 and CSS0 are rewritten so that high-speed operation can be selected again.
Caution When the main system clock is stopped and the device is operating on the subsystem
clock, wait until the oscillation stabilization time has been secured by the program before
switching back to the main system clock.