NEC mPD789425, User Manual

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CHAPTER 5 CLOCK GENERATOR
112
User’s Manual U15075EJ1V0UM00
5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as the
standby mode.
•
Main system clock f
X
•
Subsystem clock f
XT
•
CPU clock f
CPU
•
Clock to peripheral hardware
The operation and function of the clock generator is determined by the processor clock control register (PCC),
suboscillation mode register (SCKM), and subclock control register (CSS), as follows.
(a) The low-speed mode 2f
CPU
(1.6
µ
s: at 5.0 MHz operation) of the main system clock is selected when
the RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of
the main system clock is stopped.
(b) Three types of CPU clocks f
CPU
(0.2
µ
s and 0.8
µ
s: main system clock (at 5.0 MHz operation), 61
µ
s:
subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM, and CSS settings.
(c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system
where no subsystem clock is used, setting bit 1 (FRC) of the SCKM so that the on-chip feedback
resistor cannot be used reduces current consumption in STOP mode. In a system where a subsystem
clock is used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation.
(d) CSS bit 4 (CSS0) can be used to select the subsystem clock so that low current consumption
operation is used (122
µ
s: at 32.768 kHz operation).
(e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating
using bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot.
(f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system
clock, but the subsystem clock pulse is only supplied to the 16-bit timer, 8-bit timer, watch timer, and
LCD controller/driver. The 16-bit timer, 8-bit timer, watch timer, and LCD controller/driver can therefore
keep running even during standby. The other hardware stops when the main system clock stops
because it runs based on the main system clock (except for external input clock operations).