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CHAPTER 9 WATCHDOG TIMER

User’s Manual U15075EJ1V0UM00

182

9.4.2 Operation as interval timer

When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1,

respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals

specified by a preset count value.

Select a count clock (or interval) by setting bits 0 to 2 (WDCS0 to WDCS2) of the watchdog timer clock select

to 1.

In interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be

generated. The priority of INTWDT is set as the highest of all the maskable interrupts.

The interval timer continues operation in HALT mode, but stops in STOP mode. Therefore, first set RUN to 1 to

clear the interval timer before executing the STOP instruction.

Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when watchdog timer mode is selected), interval

timer mode is not set unless the RESET signal is input.

2. The interval time may be up to 0.8% shorter than the set time when WDTM has just been

set.

Table 9-5. Interval Time of Interval Timer

WDCS2

WDCS1

WDCS0

Interval

At f

= 5.0 MHz

1/f

410

1/f

1.64 ms

1/f

6.55 ms

1/f

26.2 ms

: Main system clock oscillation frequency

Summary of Contents for mPD789425

Page 1: ... µ µ µPD789435 µ µ µ µPD789455 µ µ µ µPD789436 µ µ µ µPD789456 µ µ µ µPD78F9436 µ µ µ µPD78F9456 µ µ µ µPD789426 789436 789446 789456 Subseries 8 Bit Single Chip Microcontrollers Printed in Japan Document No U15075EJ1V0UM00 1st edition Date Published November 2000 N CP K 1999 2000 ...

Page 2: ...2 User s Manual U15075EJ1V0UM00 MEMO ...

Page 3: ...ial All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connec...

Page 4: ...r third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor pr...

Page 5: ...tronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 01 30 6...

Page 6: ...6 User s Manual U15075EJ1V0UM00 MEMO ...

Page 7: ...9456 Subseries User s Manual 78K 0S Series User s Manual Instructions Pin functions Internal block functions Interrupts Other internal peripheral functions CPU function Instruction set Instruction description How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To understand the overall functions o...

Page 8: ...User s Manual U15075J This manual 78K 0S Series Instructions User s Manual U11047J U11047E 78K 0 78K 0S Series Flash Memory Write Application Note U14458J U14458E Documents Related to Development Tools User s Manuals Document No Document Name Japanese English Operation U11622J U11622E Assembly Language U11599J U11599E RA78K0S Assembler Package Structured Assembly Language U11623J U11623E Operation...

Page 9: ...9X Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892J C11892E Guide to Microcomputer Related Products by Third Parties U11416J Caution The related documents liste...

Page 10: ...10 User s Manual U15075EJ1V0UM00 MEMO ...

Page 11: ...7 2 1 List of Pin Functions 37 2 2 Description of Pin Functions 40 2 2 1 P00 to P03 Port 0 40 2 2 2 P10 P11 Port 1 40 2 2 3 P20 to P26 Port 2 40 2 2 4 P30 to P33 Port 3 41 2 2 5 P50 to P53 Port 5 41 2 2 6 P60 to P65 Port 6 41 2 2 7 P70 to P72 Port 7 42 2 2 8 P80 P81 Port 8 42 2 2 9 P90 to P97 Port 9 42 2 2 10 S0 to S14 42 2 2 11 COM0 to COM3 42 2 2 12 VLC0 to VLC2 42 2 2 13 CAPH CAPL 42 2 2 14 RES...

Page 12: ...3 3 4 4 Register addressing 74 3 4 5 Register indirect addressing 75 3 4 6 Based addressing 76 3 4 7 Stack addressing 76 CHAPTER 4 PORT FUNCTIONS 77 4 1 Port Functions 77 4 2 Port Configuration 80 4 2 1 Port 0 81 4 2 2 Port 1 82 4 2 3 Port 2 83 4 2 4 Port 3 89 4 2 5 Port 5 91 4 2 6 Port 6 92 4 2 7 Port 7 93 4 2 8 Port 8 µPD789426 789436 Subseries only 94 4 2 9 Port 9 µPD789426 789436 Subseries onl...

Page 13: ... 127 6 4 5 Buzzer output operation 128 6 5 Notes on Using 16 Bit Timer 129 CHAPTER 7 8 BIT TIMER 131 7 1 8 Bit Timer Functions 131 7 2 8 Bit Timer Configuration 132 7 3 Registers Controlling 8 Bit Timer 138 7 4 8 Bit Timer Operation 143 7 4 1 Operation as 8 bit timer counter 143 7 4 2 Operation as 16 bit timer counter 153 7 4 3 Operation as carrier generator 160 7 4 4 PWM free running mode operati...

Page 14: ...rol Registers 200 11 4 10 Bit A D Converter Operation 202 11 4 1 Basic operation of 10 bit A D converter 202 11 4 2 Input voltage and conversion result 203 11 4 3 Operation mode of 10 bit A D converter 205 11 5 Cautions Related to 10 Bit A D Converter 206 CHAPTER 12 SERIAL INTERFACE 20 211 12 1 Serial Interface 20 Functions 211 12 2 Serial Interface 20 Configuration 211 12 3 Serial Interface 20 Co...

Page 15: ...andby Function Operation 281 15 2 1 HALT mode 281 15 2 2 STOP mode 284 CHAPTER 16 RESET FUNCTION 287 CHAPTER 17 µ µ µ µPD78F9436 78F9456 291 17 1 Flash Memory Programming 292 17 1 1 Selecting communication mode 292 17 1 2 Function of flash memory programming 293 17 1 3 Flashpro III connection example 293 17 1 4 Example of settings for Flashpro III PG FP3 295 CHAPTER 18 MASK OPTIONS 297 CHAPTER 19 ...

Page 16: ...er s Manual U15075EJ1V0UM00 APPENDIX B EMBEDDED SOFTWARE 315 APPENDIX C REGISTER INDEX 317 C 1 Register Index Alphabetic Order of Register Name 317 C 2 Register Index Alphabetic Order of Register Symbol 319 ...

Page 17: ...ata to Be Saved to Stack Memory 63 3 17 Data to Be Restored from Stack Memory 63 3 18 General Purpose Register Configuration 64 4 1 Port Types µPD789426 789436 Subseries 77 4 2 Port Types µPD789446 789456 Subseries 78 4 3 Block Diagram of P00 to P03 81 4 4 Block Diagram of P10 and P11 82 4 5 Block Diagram of P20 83 4 6 Block Diagram of P21 and P26 84 4 7 Block Diagram of P22 85 4 8 Block Diagram o...

Page 18: ...ntrol Register 90 for Capture Operation 126 6 10 Capture Operation Timing Both Edges of CPT90 Pin Are Specified 126 6 11 16 Bit Timer Counter 90 Readout Timing 127 6 12 Settings of Buzzer Output Control Register 90 for Buzzer Output Operation 128 7 1 Block Diagram of Timer 50 133 7 2 Block Diagram of Timer 60 134 7 3 Block Diagram of Output Controller Timer 60 135 7 4 Format of 8 Bit Timer Mode Co...

Page 19: ... Counter 170 7 29 Timing of Operation as External Event Counter 8 Bit Resolution 170 8 1 Block Diagram of Watch Timer 171 8 2 Format of Watch Timer Mode Control Register 173 8 3 Watch Timer Interval Timer Operation Timing 175 9 1 Block Diagram of Watchdog Timer 178 9 2 Format of Watchdog Timer Clock Select Register 179 9 3 Format of Watchdog Timer Mode Register 180 10 1 Block Diagram of 8 Bit A D ...

Page 20: ...ynchronous Serial Interface Reception Completion Interrupt Timing 234 12 10 Receive Error Timing 235 12 11 3 Wire Serial I O Mode Timing 240 13 1 Block Diagram of LCD Controller Driver 248 13 2 Format of LCD Display Mode Register 0 250 13 3 Format of LCD Clock Control Register 0 251 13 4 Format of LCD Voltage Amplification Control Register 0 252 13 5 Relationship Between LCD Display Data Memory Co...

Page 21: ...ent Timing When Interrupt Request Flag Is Generated in Final Clock Under Execution 275 14 15 Example of Multiple Interrupts 276 15 1 Format of Oscillation Stabilization Time Select Register 280 15 2 Releasing HALT Mode by Interrupt 282 15 3 Releasing HALT Mode by RESET Input 283 15 4 Releasing STOP Mode by Interrupt 285 15 5 Releasing STOP Mode by RESET Input 286 16 1 Block Diagram of Reset Functi...

Page 22: ...odes 131 7 2 8 Bit Timer Configuration 132 7 3 Interval Time of Timer 50 144 7 4 Interval Time of Timer 60 144 7 5 Square Wave Output Range of Timer 50 During fX 5 0 MHz Operation 151 7 6 Square Wave Output Range of Timer 60 During fX 5 0 MHz Operation 152 7 7 Interval Time with 16 Bit Resolution During fX 5 0 MHz Operation 154 7 8 Square Wave Output Range with 16 Bit Resolution During fX 5 0 MHz ...

Page 23: ...Driver 247 13 3 Frame Frequencies Hz 251 13 4 COM Signals 254 13 5 LCD Drive Voltage 254 13 6 Select and Deselect Voltages COM0 to COM2 256 13 7 Select and Deselect Voltages COM0 to COM3 259 14 1 Interrupt Source List 264 14 2 Flags Corresponding to Interrupt Request Signal Name 266 14 3 Time from Generation of Maskable Interrupt Request to Servicing 274 15 1 HALT Mode Operating Status 281 15 2 Op...

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Page 25: ...2 µs 32 768 kHz operation with subsystem clock I O ports 40 µPD789426 789436 Subseries 30 µPD789446 789456 Subseries Timer 5 channels 16 bit timer 1 channel 8 bit timer 2 channels Watch timer 1 channel Watchdog timer 1 channel A D converter 8 bit resolution 6 channels µPD789426 789446 Subseries 10 bit resolution 6 channels µPD789436 789456 Subseries Serial interface 1 channel LCD controller driver...

Page 26: ...ic TQFP 12 12 mm Mask ROM µPD789436GK 9ET 64 pin plastic TQFP 12 12 mm Mask ROM µPD789445GK 9ET 64 pin plastic TQFP 12 12 mm Mask ROM µPD789446GK 9ET 64 pin plastic TQFP 12 12 mm Mask ROM µPD789455GK 9ET 64 pin plastic TQFP 12 12 mm Mask ROM µPD789456GK 9ET 64 pin plastic TQFP 12 12 mm Mask ROM µPD78F9436GK 9ET 64 pin plastic TQFP 12 12 mm Flash memory µPD78F9456GK 9ET 64 pin plastic TQFP 12 12 mm...

Page 27: ...40 39 38 37 36 35 34 33 P50 P51 P52 P53 IC VPP XT1 XT2 VDD VSS X1 X2 RESET P00 KR0 P01 KR1 P02 KR2 P03 KR3 32 CAPH CAPL V LC0 V LC1 V LC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 P90 P91 P62 ANI2 P63 ANI3 P64 ANI4 P65 ANI5 AVDD P72 P71 P70 P81 P80 P97 P96 P95 P94 P93 P92 P20 P21 BZO90 P22 SS20 P23 SCK20 ASCK20 P24 SO20 TxD20 P25 SI20 RxD20 P26 TO90 P30 INTP0 CPT90 P31 INTP1 TO50 TMI60 P32 INTP2 TO60 P33...

Page 28: ...6 35 34 33 P50 P51 P52 P53 IC VPP XT1 XT2 VDD VSS X1 X2 RESET P00 KR0 P01 KR1 P02 KR2 P03 KR3 32 CAPH CAPL V LC0 V LC1 V LC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 S5 S6 P62 ANI2 P63 ANI3 P64 ANI4 P65 ANI5 AVDD P72 P71 P70 S14 S13 S12 S11 S10 S9 S8 S7 P20 P21 BZO90 P22 SS20 P23 SCK20 ASCK20 P24 SO20 TxD20 P25 SI20 RxD20 P26 TO90 P30 INTP0 CPT90 P31 INTP1 TO50 TMI60 P32 INTP2 TO60 P33 INTP3 TO61 P10 P1...

Page 29: ...I20 Serial input CPT90 Capture trigger input SO20 Serial output IC Internally connected TMI60 Timer input INTP0 to INTP3 External interrupt input TO90 TO50 TO60 KR0 to KR3 Key return TO61 Timer output P00 to P03 Port 0 TxD20 Transmit data P10 P11 Port 1 VDD Power supply P20 to P26 Port 2 VLC0 to VLC2 LCD power supply P30 to P33 Port 3 VPP Programming power supply P50 to P53 Port 5 VSS Ground P60 t...

Page 30: ...PD789134A PD789177 PD789167 30 pin 30 pin PD789104A PD789114A PD789167 with enhanced A D converter PD789104A with enhanced timer PD789124A with enhanced A D converter RC oscillation version of the PD789104A PD789104A with enhanced A D converter PD789026 with added A D converter and multiplier PD789104A with added EEPROMTM PD789146 with enhanced A D converter PD789177Y PD789167Y Y Subseries product...

Page 31: ... ch 4 ch 1 ch UART 1 ch 20 1 8 V Inverter control µPD789842 8 K to 16 K 3 ch Note 1 ch 1 ch 8 ch 1 ch UART 1 ch 30 4 0 V VFD drive µPD789871 4 K to 8 K 3 ch 1 ch 1 ch 1 ch 33 2 7 V µPD789488 32 K 8 ch 2 ch UART 1 ch 45 µPD789417A 7 ch µPD789407A 12 K to 24 K 3 ch 7 ch 43 µPD789456 6 ch µPD789446 6 ch 30 µPD789436 6 ch µPD789426 12 K to 16 K 6 ch 1 ch UART 1 ch 40 µPD789316 RC oscillation version L...

Page 32: ... 8 bit timer event counter 60 Cascaded 16 bit timer event counter TO60 P32 CPT90 P30 VLC0 to VLC2 CAPH CAPL LCD controller driver P50 to P53 Port 5 System control RESET X1 X2 XT1 XT2 Interrupt control INTP0 P30 INTP1 P31 INTP2 P32 INTP3 P33 KR0 P00 to KR3 P03 TO61 P33 BZO90 P21 Serial Iinterface 20 SCK20 ASCK20 P23 SI20 RxD20 P25 SO20 TxD20 P24 SS20 P22 A D converter ANI0 P60 to ANI5 P65 AVSS AVDD...

Page 33: ... TO50 P31 16 bit timer 90 Watch timer Watchdog timer TO90 P26 S0 to S4 COM0 to COM3 RAM RAM space for LCD data 8 bit timer event counter 60 Cascaded 16 bit timer event counter TO60 P32 CPT90 P30 VLC0 to VLC2 CAPH CAPL LCD controller driver P50 to P53 Port 5 System control RESET X1 X2 XT1 XT2 Interrupt control INTP0 P30 INTP1 P31 INTP2 P32 INTP3 P33 KR0 P00 to KR3 P03 TO61 P33 BZO90 P21 Serial Iint...

Page 34: ...d test I O ports Total 40 CMOS I O 30 CMOS input 6 N ch open drain 4 Total 30 CMOS I O 20 CMOS input 6 N ch open drain 4 Timers 16 bit timer 1 channel 8 bit timer 2 channels Watch timer 1 channel Watchdog timer 1 channel A D converter 8 bit resolution 6 channels µPD789426 789446 Subseries 10 bit resolution 6 channels µPD789436 789456 Subseries Serial interfaces Switchable between 3 wire serial I O...

Page 35: ...e 2 Operation mode External event counter 1 channel Timer outputs 1 1 2 Square wave outputs 1 2 Capture 1 input Function Interrupt sources 1 1 1 1 1 Notes 1 The watch timer can perform both watch timer and interval timer functions at the same time 2 The watchdog timer has the watchdog timer and interval timer functions However use the watchdog timer by selecting either the watchdog timer function ...

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Page 37: ...port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B2 PUB2 Input TO90 P30 INTP0 CPT90 P31 INTP1 TO50 TMI60 P32 INTP2 TO60 P33 I O Port 3 4 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pul...

Page 38: ... 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B8 PUB8 Input P90 to P97 Note I O Port 9 8 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B9 PUB9 Input Note µPD789426 789436 Subseries only ...

Page 39: ...r TM90 output Input P26 CPT90 Input Capture edge input Input P30 INTP0 TO50 Output 8 bit timer TM50 output Input P31 INTP1 TMI40 TO60 Output Input P32 INTP2 TO61 Output 8 bit timer TM60 output Input P33 INTP33 TMI60 Input External count clock input to timer 40 Input P31 INTP1 TO50 ANI0 to ANI5 Input A D converter analog input Input P60 to P65 S0 to S4 Output Output S5 to S14 Note Output LCD contro...

Page 40: ...e specified by pull up resistor option register 0 PU0 in port units 2 2 3 P20 to P26 Port 2 These pins constitute a 7 bit I O port In addition these pins enable buzzer output timer output serial interface data I O and serial clock I O Port 2 can be specified in the following operation modes in 1 bit units 1 Port mode In this mode P20 to P26 function as a 7 bit I O port Port 2 can be set in the inp...

Page 41: ...egister B3 PUB3 in 1 bit units 2 Control mode In this mode P30 to P33 function as timer I O and external interrupt input a TMI60 This is the external clock input pin to timer 60 b TO50 TO60 TO61 These are the timer output pins of timer 50 and timer 60 c CPT90 This is the capture edge input pin of 16 bit timer 90 d INTP0 to INTP3 These are external interrupt input pins for which valid edges rising ...

Page 42: ...gister 9 PM9 When used as an input port use of an on chip pull up resistor can be specified by pull up resistor option register B9 PUB9 in port units Note Only the µPD789426 and µPD789436 Subseries 2 2 10 S0 to S14 Note These pins are segment signal output pins for the LCD controller driver Note S0 to S4 in the case of the µPD789426 and 789436 Subseries 2 2 11 COM0 to COM3 These pins are common si...

Page 43: ...S in the normal operation mode 2 2 20 IC mask ROM version only The IC Internally Connected pin is used to set the µPD789426 789436 789446 and 789456 Subseries in the test mode before shipment In the normal operation mode directly connect this pin to the VSS pin with as short a wiring length as possible If a potential difference is generated between the IC pin and VSS pin due to a long wiring lengt...

Page 44: ...Leave open P30 INPT0 CPT90 P31 INPT1 TO50 TMI60 P32 INPT2 TO60 P33 INPT3 TO61 8 A Input Independently connect to VSS via a resistor Output Leave open P50 to P53 Mask ROM version 13 W P50 to P53 Flash memory version 13 V I O Input Independently connect to VDD via a resistor Output Leave open P60 ANI0 to P65 ANI5 9 C Input Connect directly to VDD or VSS P70 to P72 P80 P81 Note 1 P90 to P97 Note 1 5 ...

Page 45: ... Output disable Input enable VDD P ch VDD P ch IN OUT N ch VSS VSS Output data Output disable IN OUT VDD N ch Middle voltage input buffer Input enable Pull up resistor mask option Type 8 A Type 17 Pull up enable Data Output disable VDD P ch VDD P ch IN OUT N ch VSS P ch P ch VLC0 VLC1 N ch P ch N ch VLC2 SEG data P ch OUT N ch N ch Type 9 C Type 18 IN Comparator VREF Threshold voltage AVSS P ch N ...

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Page 47: ...Figure 3 1 Memory Map µ µ µ µPD789425 789435 Special function registers 256 8 bits Internal high speed RAM 512 8 bits LCD display RAM 5 4 bits Reserved Reserved Internal ROM 12288 8 bits FFFFH FF00H FEFFH FD00H FCFFH FA00H F9FFH 0000H Program memory space Data memory space 2FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table area 0022H 0021H Vector table area FA05H FA04H 3000H...

Page 48: ...256 8 bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table area 0022H 0021H Vector table area LCD display RAM 5 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH FA05H FA04H 4000H 3FFFH ...

Page 49: ... 8 bits Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table area 0022H 0021H Vector table area LCD display RAM 5 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH FA05H FA04H 4000H 3FFFH ...

Page 50: ...56 8 bits Internal high speed RAM 512 8 bits Internal ROM 12288 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 2FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table area 0022H 0021H Vector table area LCD display RAM 15 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH FA0FH FA0EH 3000H 2FFFH ...

Page 51: ...56 8 bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table area 0022H 0021H Vector table area LCD display RAM 15 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH FA0FH FA0EH 4000H 3FFFH ...

Page 52: ...8 bits Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH FF00H FEFFH 0000H Program memory space Data memory space 3FFFH 0000H Program area 0080H 007FH Program area 0040H 003FH CALLT table area 0022H 0021H Vector table area LCD display RAM 15 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH FA0FH FA0EH 4000H 3FFFH ...

Page 53: ...memory space 1 Vector table area The 34 byte area of addresses 0000H to 0021H is reserved as a vector table area This area stores program start addresses to be used when branching by the RESET input or an interrupt request generation Of a 16 bit program address the lower 8 bits are stored in an even address and the higher 8 bits are stored in an odd address Table 3 2 Vector Table Vector Table Addr...

Page 54: ...M is also used as a stack 2 LCD display RAM LCD display RAM is incorporated The LCD display RAM can also be used as ordinary RAM Each subseries incorporates LCD display RAM with the following capacity Table 3 3 LCD Display RAM Capacity Subseries Name Area Capacity µPD789426 789436 Subseries FA00H to FA04H 5 4 bits µPD789446 789456 Subseries FA00H to FA0EH 15 4 bits 3 1 3 Special function register ...

Page 55: ...ond to the particular function an area such as the special function registers are available Figures 3 7 through 3 12 show the data memory addressing modes Figure 3 7 Data Memory Addressing µ µ µ µPD789425 789435 Special function registers SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 12288 8 bits FFFFH 0000H Direct adressing Register indirect addressing Based addressing FF00H FEF...

Page 56: ...ion registers SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR addressing Short direct addressing LCD display RAM 5 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH 4000H 3FFFH FA05H FA04H ...

Page 57: ... registers SFRs 256 8 bits Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR addressing Short direct addressing LCD display RAM 5 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH 4000H 3FFFH FA05H FA04H ...

Page 58: ...ion registers SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 12288 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR addressing Short direct addressing LCD display RAM 15 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH 3000H 2FFFH FA0FH FA0EH ...

Page 59: ...ion registers SFRs 256 8 bits Internal high speed RAM 512 8 bits Internal ROM 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR addressing Short direct addressing LCD display RAM 15 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH 4000H 3FFFH FA0FH FA0EH ...

Page 60: ... registers SFRs 256 8 bits Internal high speed RAM 512 8 bits Flash memory 16384 8 bits FFFFH 0000H Direct addressing Register indirect addressing Based addressing FF00H FEFFH FF20H FF1FH FE20H FE1FH SFR addressing Short direct addressing LCD display RAM 15 4 bits Reserved Reserved FD00H FCFFH FA00H F9FFH 4000H 3FFFH FA0FH FA0EH ...

Page 61: ...number of bytes of the instruction to be fetched When a branch instruction is executed immediate data or register contents are set RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter Figure 3 13 Program Counter Configuration 0 15 PC14 PC15 PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 2 Program status word PSW The program status word ...

Page 62: ...various interrupt sources IE is reset 0 upon DI instruction execution or interrupt acknowledgment and is set 1 upon EI instruction execution b Zero flag Z When the operation result is zero this flag is set 1 It is reset 0 in all other cases c Auxiliary carry flag AC If the operation result has a carry from bit 3 or a borrow at bit 3 this flag is set 1 It is reset 0 in all other cases d Carry flag ...

Page 63: ...restores data as shown in Figures 3 16 and 3 17 Caution Since RESET input makes the SP contents undefined be sure to initialize the SP before instruction execution Figure 3 16 Data to Be Saved to Stack Memory Interrupt PSW PC15 to PC8 PC15 to PC8 PC7 to PC0 Lower register pairs SP SP _ 2 SP _ 2 CALL CALLT instructions PUSH rp instruction SP _ 1 SP SP SP _ 2 SP _ 2 SP _ 1 SP PC7 to PC0 SP _ 3 SP _ ...

Page 64: ...rs in pairs can be used as a 16 bit register AX BC DE and HL General purpose registers can be described in terms of function names X A C B E D L H AX BC DE or HL or absolute names R0 to R7 and RP0 to RP3 Figure 3 18 General Purpose Register Configuration a Absolute names R0 15 0 7 0 16 bit processing 8 bit processing RP3 RP2 RP1 RP0 R1 R2 R3 R4 R5 R6 R7 b Function names X 15 0 7 0 16 bit processin...

Page 65: ...n operand sfr This manipulation can also be specified with an address 16 bit manipulation Describes a symbol reserved by the assembler for the 16 bit manipulation instruction operand When addressing an address describe an even address Table 3 4 lists the special function registers The meanings of the symbols in this table are as follows Symbol Indicates the addresses of the implemented special fun...

Page 66: ...P90 Note 2 R Note 3 Undefined FF20H Port mode register 0 PM0 FF21H Port mode register 1 PM1 FF22H Port mode register 2 PM2 FF23H Port mode register 3 PM3 FF25H Port mode register 5 PM5 R W FFH Notes 1 µPD789426 and 789436 Subseries only 2 Name of SFR dedicated for 16 bit access 3 Only in short direct addressing 16 bit access is possible 4 These are 16 bit access dedicated registers however 8 bit a...

Page 67: ...ator output control register 60 TCA60 W FF70H Asynchronous serial interface mode register 20 ASIM20 R W FF71H Asynchronous serial interface status register 20 ASIS20 R FF72H Serial operation mode register 20 CSIM20 FF73H Baud rate generator control register 20 BRGC20 FF80H A D converter mode register 0 ADM0 FF84H Analog input channel specification register 0 ADS0 FFB0H LCD display mode register 0 ...

Page 68: ...ddressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit This means that information is relatively branched to a location between...

Page 69: ... transferred to the program counter PC and branched This function is carried out when the CALL addr16 or BR addr16 instruction is executed CALL addr16 and BR addr16 instructions can be branched to any location in the memory space Illustration In case of CALL addr16 and BR addr16 instructions 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr ...

Page 70: ...uted The instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective address 1 Effective address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 0 0 1 7 6 5 1 0 ta4 0 Instruction code 3 3 4 Register addressing Function The register pair AX contents to be specified...

Page 71: ...instruction execution 3 4 1 Direct addressing Function The memory indicated with immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A FE00H When setting addr16 to FE00H Instruction code 0 0 1 0 1 0 0 1 OP code 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 00H FEH Illustration 7 0 OP code addr16 Lower add...

Page 72: ...er event counter are mapped in this area and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 See Illustration below Operand format Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data even ...

Page 73: ...n word This addressing is applied to the 256 byte space FF00H to FFFFH However the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing Operand format Identifier Description sfr Special function register name Description example MOV PM0 A When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 Illustration 15 0 SFR Effective Address 1 1 1 1 1 1 1 8 7 ...

Page 74: ...erand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C When selecting the C register for r ...

Page 75: ... The register pair to be accessed is specified by the register pair specification code in an instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE When selecting register pair DE Instruction code 0 0 1 0 1 0 1 1 Illustration 15 0 8 D 7 E 0 7 7 0 A DE Addressed memory contents are transferred Memory add...

Page 76: ...es Operand format Identifier Description HL byte Description example MOV A HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3 4 7 Stack addressing Function The stack area is indirectly addressed with the stack pointer SP contents This addressing method is automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is...

Page 77: ...s methods of control Numerous other functions are provided that can be used in addition to the digital I O port functions For more information on these additional functions see CHAPTER 2 PIN FUNCTIONS Figure 4 1 Port Types µ µ µ µPD789426 789436 Subseries P30 P33 P60 P00 P03 P10 P11 Port 1 Port 2 Port 3 Port 5 P20 P26 P65 Port 0 Port 6 P70 P72 Port 8 Port 7 P80 P81 P90 P97 Port 9 P50 P53 ...

Page 78: ...4 PORT FUNCTIONS 78 User s Manual U15075EJ1V0UM00 Figure 4 2 Port Types µ µ µ µPD789446 789456 Subseries P30 P33 P60 P00 P03 P10 P11 Port 1 Port 2 Port 3 P20 P26 P65 Port 0 P70 P72 Port 7 Port 6 P50 P53 Port 5 ...

Page 79: ...t Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull up resistor option register B2 PUB2 Input TO90 P30 INTP0 CPT90 P31 INTP1 TO50 TMI60 P32 INTP2 TO60 P33 I O Port 3 4 bit I O port Input output can be specified in 1 bit units When used as an input port an on chip pull up resistor can be specified by means of pull u...

Page 80: ... specified by means of pull up resistor option register B9 PUB9 Input Note µPD789426 789436 Subseries only 4 2 Port Configuration Ports have the following hardware configuration Table 4 2 Configuration of Port Item Configuration Control registers Port mode register PMm m 0 to 3 5 7 to 9 Pull up resistor option register PU0 PUB2 PUB3 PUB7 to PUB9 µPD789426 789436 Subseries Total 40 CMOS I O 30 CMOS...

Page 81: ...be connected in 4 bit units by using pull up resistor option register 0 PU0 Port 0 is set in the input mode when the RESET signal is input Figure 4 3 shows a block diagram of port 0 Figure 4 3 Block Diagram of P00 to P03 WRKRM00 VDD P00 KR0 to P03 KR3 WRPUO RD WRPORT WRPM PU00 PM00 to PM03 KRM000 P ch Internal bus Selector Output latch P00 to P03 Alternate function KRM00 Key return mode register 0...

Page 82: ...t pins on chip pull up resistors can be connected in 2 bit units by using pull up resistor option register 0 PU0 This port is set in the input mode when the RESET signal is input Figure 4 4 shows a block diagram of port 1 Figure 4 4 Block Diagram of P10 and P11 PU0 Pull up resistor option register 0 PM Port mode register RD Port 1 read signal WR Port 1 write signal WRPU0 RD WRPORT WRPM PU01 PM10 P...

Page 83: ...l interface I O buzzer output and timer output This port is set in the input mode when the RESET signal is input Figures 4 5 to 4 10 show block diagrams of port 2 Caution When using the pins of port 2 as the serial interface the I O or output latch must be set according to the function to be used For how to set the latches see Figure 12 2 Settings of Serial Interface 20 Operating Mode Figure 4 5 B...

Page 84: ...Block Diagram of P21 and P26 Internal bus VDD P ch P21 BZO90 P26 TO90 WRPUB2 RD WRPORT WRPM PUB21 PUB26 Output latch P21 P26 PM21 PM26 Alternate function Selector PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 85: ...00 85 Figure 4 7 Block Diagram of P22 Internal bus VDD P ch P22 SS20 WRPUB2 RD WRPORT WRPM PUB22 Alternate function Output latch P22 PM22 Selector PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 86: ... 8 Block Diagram of P23 Internal bus VDD P ch P23 ASCK20 SCK20 WRPUB2 RD WRPORT WRPM PUB23 Alternate function Output latch P23 PM23 Alternate function Selector PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 87: ...ure 4 9 Block Diagram of P24 PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal Internal bus VDD P24 SO20 TxD20 WRPUB2 RD WRPORT WRPM PUB24 Alternate function Output latch P24 PM24 Selector P ch SS20 output ...

Page 88: ...0 Figure 4 10 Block Diagram of P25 P25 SI20 RxD20 WRPUB2 RD WRPORT WRPM PUB25 Alternate function Output latch P25 PM25 VDD P ch Internal bus Selector PUB2 Pull up resistor option register B2 PM Port mode register RD Port 2 read signal WR Port 2 write signal ...

Page 89: ... bit units by using pull up resistor option register B3 PUB3 This port is also used as an external interrupt input capture input and timer I O This port is set in the input mode when the RESET signal is input Figures 4 11 and 4 12 show block diagrams of port 3 Figure 4 11 Block Diagram of P30 P30 INTP0 CPT90 WRPUB3 RD WRPORT WRPM PUB30 PM30 VDD P ch Internal bus Alternate function Selector Output ...

Page 90: ...UB3 Pull up resistor option register B3 PM Port mode register RD Port 3 read signal WR Port 3 write signal P31 INTP1 TO50 TMI60 P32 INTP2 TO60 P33 INTP3 TO61 WRPUB3 RD WRPORT WRPM PUB31 to PUB33 PM31 to PM33 VDD P ch Internal bus Alternate function Selector Output latch P31 to P33 Alternate function ...

Page 91: ...hip pull up resistor can be specified by a mask option This port is set in the input mode when the RESET signal is input Figure 4 13 shows a block diagram of port 5 Figure 4 13 Block Diagram of P50 to P53 Internal bus Selector RD PM50 to PM53 P50 to P53 N ch WRPORT Output latch P50 to P53 WRPM VDD Mask option resistor Mask ROM version only For flash memory version a pull up resistor is not incorpo...

Page 92: ...1V0UM00 4 2 6 Port 6 This is an 8 bit input only port This port is also used as the analog input of an A D converter Figure 4 14 shows a block diagram of Port 6 Figure 4 14 Block Diagram of Port 6 VREF RD A D converter P60 ANI0 to P65 ANI5 Internal bus ...

Page 93: ...p pull up resistors can be connected in 1 bit units by using pull up resistor option register B7 PUB7 This port is set in the input mode when the RESET signal is input Figure 4 15 shows a block diagram of Port 7 Figure 4 15 Block Diagram of P70 to P72 WRPUB7 RD WRPORT WRPM PUB70 to PUB72 Output latch P70 to P72 PM70 to PM72 VDD P ch P70 to P72 Internal bus Selector PUB7 Pull up resistor option reg...

Page 94: ... input port pins on chip pull up resistors can be connected in 1 bit units by using pull up resistor option register B8 PUB8 This port is set in the input mode when the RESET signal is input Figure 4 16 shows a block diagram of port 8 Figure 4 16 Block Diagram of P80 and P81 PUB8 Pull up resistor option register B8 PM Port mode register RD Port 8 read signal WR Port 8 write signal WRPUB8 RD WRPORT...

Page 95: ...nput port pins on chip pull up resistors can be connected in 1 bit units by using pull up resistor option register B9 PUB9 This port is set in the input mode when the RESET signal is input Figure 4 17 shows a block diagram of port 9 Figure 4 17 Block Diagram of P90 to P97 WRPUB9 RD WRPORT WRPM PUB90 to PUB97 Output latch P90 to P97 PM90 to PM97 VDD P ch P90 to P97 Internal bus Selector PUB9 Pull u...

Page 96: ... input output in 1 bit units The port mode registers are independently set with a 1 bit or 8 bit memory manipulation instruction RESET input sets the registers to FFH When port pins are used as alternate function pins set the port mode register and output latch according to Table 4 3 Caution As port 3 has an alternate function as external interrupt input when the port function output mode is speci...

Page 97: ... 7 Symbol Address After reset 6 5 4 3 2 1 0 R W FF20H FF21H FF25H FFH FFH FFH R W R W R W 1 1 1 1 1 PM72 PM71 PM70 PM7 FF27H FFH R W 1 1 1 1 1 1 PM81 PM80 PM8Note FF28H FFH R W PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90 PM9Note FF29H FFH R W 1 1 PM26 1 PM25 1 PM24 1 PM23 PM33 PM22 PM32 PM21 PM31 PM20 PM30 PM2 PM3 FF22H FF23H FFH FFH R W R W Pmn pin input output mode selection m 0 to 3 5 7 to 9 n 0 to...

Page 98: ...Port output latch 2 Pull up resistor option register 0 PU0 Pull up resistor option register 0 PU0 sets whether on chip pull up registers are used on ports 0 and 1 or not On the port specified to use an on chip pull up resistor by PU0 the pull up resistor can be internally used only for the bits set in the input mode No on chip pull up resistors can be used for the bits set in the output mode regar...

Page 99: ... Address After reset R W FF32H 00H R W 7 6 5 4 3 2 1 0 PUB2n 0 1 On chip pull up resistor not used On chip pull up resistor used Symbol 4 Pull up resistor option register B3 PUB3 Pull up resistor option register B3 PUB3 sets whether on chip pull up resistors on P30 to P33 are used or not On the port specified to use an on chip pull up resistor by PUB3 the pull up resistor can be internally used on...

Page 100: ...R W 7 6 5 4 3 2 1 0 PUB7n 0 1 On chip pull up resistor not used On chip pull up resistor used Symbol 6 Pull up resistor option register B8 PUB8 Note Pull up resistor option register B8 PUB8 sets whether on chip pull up resistors on P80 and P81 are used or not On the port specified to use an on chip pull up resistor by PUB8 the pull up resistor can be internally used only for bits set in the input ...

Page 101: ... be used for the bits set in the output mode regardless of the setting of PUB9 This also applies to when the pins are used for alternate function PUB9 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PUB9 to 00H Note Incorporated only in the µPD789426 and 789436 Subseries Figure 4 24 Format of Pull Up Resistor Option Register B9 P9n on chip pull up resistor selection n...

Page 102: ...f the pin that is set in the input mode and not subject to manipulation become undefined 4 4 2 Reading from I O port 1 In output mode The status of an output latch can be read by using a transfer instruction The contents of the output latch are not changed 2 In input mode The status of a pin can be read by using a transfer instruction The contents of the output latch are not changed 4 4 3 Arithmet...

Page 103: ...cuting the STOP instruction or setting the processor clock control register PCC Subsystem clock oscillator This circuit oscillates at 32 768 kHz Oscillation can be stopped by the suboscillation mode register SCKM 5 2 Clock Generator Configuration The clock generator includes the following hardware Table 5 1 Configuration of Clock Generator Item Configuration Control registers Processor clock contr...

Page 104: ...8 bit timer 60 Watch timer LCD controller driver Clock to peripheral hardware CPU clock fCPU Standby controller Wait controller Selector STOP MCC PCC1 CLS CSS0 Internal bus Suboscillation mode register SCKM FRC SCC Internal bus Subclock control register CSS Processor clock control register PCC Subsystem clock oscillator X1 X2 XT1 XT2 Main system clock oscillator ...

Page 105: ...eset R W FFFBH 02H R W 7 6 5 4 3 2 1 0 MCC 0 1 Operation enabled Operation disabled CPU clock fCPU selectionNote CSS0 0 0 1 1 PCC1 0 1 0 1 fX 0 2 s fX 22 0 8 s fXT 2 61 s µ µ µ Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control register PCC and the CSS0 flag in the subclock control register CSS Refer to 5 3 3 Subclock control register CSS Caut...

Page 106: ... memory manipulation instruction RESET input sets SCKM to 00H Figure 5 3 Format of Suboscillation Mode Register Feedback resistor selection 0 0 0 0 0 0 FRC SCC SCKM Symbol Address After reset R W FFF0H 00H R W 7 6 5 4 3 2 1 0 FRC 0 1 On chip feedback resistor used On chip feedback resistor not used Control of subsystem clock oscillator operation SCC 0 1 Operation enabled Operation disabled Caution...

Page 107: ...to 00H Figure 5 4 Format of Subclock Control Register CPU clock operation status 0 0 CLS CSS0 0 0 0 0 CSS Address After reset R W FFF2H 00H R W 7 6 5 4 3 2 1 0 CLS 0 1 Operation based on the output of the divided main system clock Operation based on the subsystem clock Selection of the main system or subsystem clock oscillator CSS0 0 1 Divided output from the main system clock oscillator Output fr...

Page 108: ...nnected across the X1 and X2 pins An external clock can also be input to the circuit In this case input the clock signal to the X1 pin and input the inverted signal to the X2 pin Figure 5 5 shows the external circuit of the main system clock oscillator Figure 5 5 External Circuit of Main System Clock Oscillator a Crystal or ceramic oscillation b External clock Crystal or ceramic resonator VSS X2 X...

Page 109: ...en using the main system or subsystem clock oscillator wire as follows in the area enclosed by the broken lines in Figures 5 5 and 5 6 to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point...

Page 110: ...line VSS X1 X2 VSS X1 X2 PORTn n 0 to 3 5 c Wiring near high fluctuating current d Current flowing through ground line of oscillator potential at points A B and C fluctuates VSS X1 X2 High current VSS X1 A B C Pmn VDD High current X2 Remark When using the subsystem clock read X1 and X2 as XT1 and XT2 respectively and connect a resistor to XT2 in series ...

Page 111: ...id this do not lay the X1 and XT2 wires in parallel 5 4 3 Divider circuit The divider circuit divides the output of the main system clock oscillator fX to generate various clocks 5 4 4 When no subsystem clock is used If a subsystem clock is not necessary for example for low power consumption operation or clock operation handle the XT1 and XT2 pins as follows XT1 Connect to VSS XT2 Leave open In th...

Page 112: ...e used with the main system clock selected In a system where no subsystem clock is used setting bit 1 FRC of the SCKM so that the on chip feedback resistor cannot be used reduces current consumption in STOP mode In a system where a subsystem clock is used setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation d CSS bit 4 CSS0 can be used to select the subsystem clock so that low...

Page 113: ... after the setting of PCC has been changed and the old clock is used for the duration of several instructions after that see Table 5 2 Table 5 2 Maximum Time Required for Switching CPU Clock Set Value Before Switching Set Value After Switching CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 0 0 0 1 1 x 0 0 4 clocks 2fX fXT clocks 306 clocks 1 2 clocks fX 2fXT clocks 76 clocks 1 x 2 clocks 2 clocks Remarks...

Page 114: ... 5 0 MHz operation 2 After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed has elapsed bit 1 PCC1 of the processor clock control register PCC and bit 4 CSS0 of the subclock control register CSS are rewritten so that high speed operation can be selected 3 A drop of the VDD voltage is detected with an interrupt request signal The clock is switche...

Page 115: ...1 Timer interrupt An interrupt is generated when a count value and compare value matches 2 Timer output Timer output can be controlled when a count value and compare value matches 3 Buzzer output Buzzer output can be controlled by software 4 Count value capture A count value of 16 bit timer counter 90 TM90 is latched into a capture register synchronizing with the capture trigger and retained ...

Page 116: ...owing hardware Table 6 1 16 Bit Timer Configuration Item Configuration Timer counters 16 bits 1 TM90 Registers Compare register 16 bits 1 CR90 Capture register 16 bits 1 TCP90 Timer outputs 1 TO90 Control registers 16 bit timer mode control register 90 TMC90 Buzzer output control register 90 BZC90 Port mode register 2 PM2 ...

Page 117: ...0 TM90 16 bit compare register 90 CR90 f X 2 2 f X 2 6 f X 2 7 f XT CTP90 INTP0 TI81 P30 TOC90 TCL901TCL900 TOE90 F F TOD90 P26 Output latch P21 Output latch PM26 PM21 TO90 P26 INTTM90 BZO90 P21 Match OVF Buzzer output control register BZC90 3 BCS902 BCS901 BCS900 BZOE90 Edge detector Synchronization circuit f X Write controller Write controller f X 2 CPU clock Selector Selector Selector Figure 6 ...

Page 118: ...TM90 TM90 is used to count the number of pulses The contents of TM90 are read with an 8 bit or 16 bit memory manipulation instruction RESET input sets TM90 to 0000H Cautions 1 The count becomes undefined when STOP mode is deselected because the count operation is performed before oscillation stabilizes 2 TM90 is designed to be manipulated with a 16 bit memory manipulation instruction However it ca...

Page 119: ...sters 16 bit timer mode control register 90 TMC90 Buzzer output control register 90 BZC90 Port mode register 2 PM2 1 16 bit timer mode control register 90 TMC90 16 bit timer mode control register 90 TMC90 controls the setting of a count clock capture edge etc TMC90 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC90 to 00H ...

Page 120: ... 0 1 Timer output data inversion control Inversion disabled Inversion enabled TCL901 0 0 1 1 16 bit timer counter 90 count clock selection TCL900 0 1 0 1 TOE90 0 1 16 bit timer counter 90 output control Output disabled port mode Output enabled TOD90 0 1 Timer output data Timer output data is 0 Timer output data is 1 fX 22 1 25 MHz fX 26 78 1 kHz fX 27 39 1 kHz fXT 32 768 kHz Note Bit 7 is read onl...

Page 121: ... 4 88 kHz fcl 29 2 44 kHz fcl 210 1 22 kHz fcl 211 610 Hz fcl 212 305 Hz fcl 213 153 Hz fcl 24 4 88 kHz fcl 25 2 44 kHz fcl 28 305 Hz fcl 29 153 Hz fcl 210 76 Hz fcl 211 38 Hz fcl 212 19 Hz fcl 213 10 Hz fcl 24 2 44 kHz fcl 25 1 22 kHz fcl 28 153 Hz fcl 29 76 Hz fcl 210 38 Hz fcl 211 19 Hz fcl 212 10 Hz fcl 213 5 Hz fcl 24 2 05 kHz fcl 25 1 02 kHz fcl 28 128 Hz fcl 29 64 Hz fcl 210 32 Hz fcl 211 1...

Page 122: ...26 to 0 when pin P21 BZO90 is used for buzzer output reset the output latch of P26 and PM26 to 0 PM2 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM2 to FFH Figure 6 4 Format of Port Mode Register 2 PM2n P2n pin I O mode n 1 6 Output mode output buffer ON Input mode output buffer OFF 0 1 1 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM2 Symbol Address After reset R W FF22H ...

Page 123: ...nt value of 16 bit timer counter 90 TM90 matches the value set in CR90 counting of TM90 continues and an interrupt request signal INTTM90 is generated Table 6 2 shows interval time and Figure 6 6 shows timing of timer interrupt operation Caution When rewriting the value in CR90 during a count operation be sure to execute the following processing 1 Set interrupt disabled set TMMK90 bit 4 of interru...

Page 124: ...00 124 Figure 6 6 Timing of Timer Interrupt Operation Count clock TM90 count value CR90 INTTM90 TO90 TOF90 0000H 0001H N FFFFH 0000H 0001H N FFFFH N N N N N Interrupt acknowledgement Interrupt acknowledgement Overflow flag set t Remark N 0000H to FFFFH ...

Page 125: ...MC90 Setting of count clock see Table 6 2 Inverse enable of timer output data TO90 output enable Caution If both the CPT901 flag and CPT900 flag are set to 0 the capture operation is prohibited When the count value of 16 bit timer counter 90 TM90 matches the value set in CR90 the output status of the TO90 P26 pin is inverted This enables timer output At that time TM90 counting continues and an int...

Page 126: ...detected and latches and retains the count value of 16 bit timer register 90 The TCP90 fetches the count value within 2 clocks and retains the count value until the next capture edge detection Table 6 3 and Figure 6 10 show the settings of the capture edge and the capture operation timing respectively Table 6 3 Settings of Capture Edge CPT901 CPT900 Capture Edge Selection 0 0 Capture operation pro...

Page 127: ...TM90 to 0000H and TM90 starts freerunning Figure 6 11 shows the timing of 16 bit timer counter 90 readout Cautions 1 The count value after releasing stop becomes undefined because the count operation is executed during the oscillation stabilization time 2 Though TM90 is designed for a 16 bit transfer instruction an 8 bit transfer instruction can also be used When using an 8 bit transfer instructio...

Page 128: ...equency see Table 6 4 Enables buzzer output Table 6 4 Buzzer Frequency of 16 Bit Timer Buzzer Frequency BCS902 BCS901 BCS900 fcl fX 2 2 fcl fX 2 6 fcl fX 2 7 fcl fXT 0 0 0 fcl 2 4 78 1 kHz fcl 2 4 4 88 kHz fcl 2 4 2 44 kHz fcl 2 4 2 05 kHz 0 0 1 fcl 2 5 39 1 kHz fcl 2 5 2 44 kHz fcl 2 5 1 22 kHz fcl 2 5 1 02 kHz 0 1 0 fcl 2 8 4 88 kHz fcl 2 8 305 Hz fcl 2 8 153 Hz fcl 2 8 128 Hz 0 1 1 fcl 2 9 2 44...

Page 129: ... clock is stopped 2 The read function of TM90 uses the CPU clock for control refer to Figure 6 1 and reads an undefined value when the CPU clock is slower than the count clock values are not guaranteed When reading TM90 set the count clock to the same speed as the CPU clock when the CPU clock is the main system clock high speed mode is set or select a clock slower than the CPU clock 3 When the sub...

Page 130: ... Main system clock Oscillation stopped BZOE90 1 Buzzer output enabled At this time when the setting of P21 the buzzer output alternate function pin is PM21 0 P21 0 a square wave of the buzzer frequency is output from P21 To avoid outputting the buzzer frequency make either of the following settings Set P21 to input mode PM21 1 If P21 cannot be set to input mode set the port latch value of P21 to 1...

Page 131: ...t timer counter mode discrete mode The following functions can be used in this mode Interval timer with 8 bit resolution External event counter with 8 bit resolution timer 40 only Square wave output with 8 bit resolution 2 16 bit timer counter mode cascade connection mode Operation as a 16 bit timer event counter is enabled during cascade connection mode The following functions can be used in this...

Page 132: ... as the timer output pin using software 7 2 8 Bit Timer Configuration The 8 bit timer includes the following hardware Table 7 2 8 Bit Timer Configuration Item Configuration Timer counters 8 bits 2 TM50 TM60 Registers Compare registers 8 bits 3 CR50 CR60 CRH60 Timer outputs 3 TO50 TO60 TO61 Control registers 8 bit timer mode control register 50 TMC50 8 bit timer mode control register 60 TMC60 Carri...

Page 133: ... 7 Timer 60 interrupt request signal from Figure 7 2 B Carrier clock in carrier generator mode or timer 60 output signal in a mode other than carrier generator mode from Figure 7 2 C Cascade connection mode Match Internal bus OVF Bit 7 of TM60 from Figure 7 2 A TOE50 P31 output latch PM31 To Figure 7 2 F Timer 50 match signal in cascade connection mode TO50 TMI60 INTP1 P31 TCE50 TCL502 f X f XT TM...

Page 134: ...egister 60 TCA60 TO61 INTP3 P33 Prescaler Selector Count operation start signal to timer 50 in cascade connection mode To Figure 7 1 D TM50 match signal in cascade connection mode TM60 timer counter match signal in cascade connection mode From Figure 7 1 F To Figure 7 1 E count clock input signal to TM50 To Figure 7 1 A Bit 7 of TM60 in cascade connection mode To Figure 7 1 C Carrier clock during ...

Page 135: ...te the CR50 with the TOE50 in a cleared status 2 If the valid edge of the count clock is selected for both edges in the PWM output mode TEG50 1 do not set 00H 01H and FFH to the CR50 If the rising edge is selected TEG50 0 do not set 00H to CR50 2 8 bit compare register 60 CR60 This 8 bit register is used to continually compare the value set to CR60 with the count value in 8 bit timer counter 60 TM...

Page 136: ...alue overflows ii TM60 After reset When TCE60 bit 7 of 8 bit timer mode control register 60 TMC60 is cleared to 0 When a match occurs between TM60 and CR60 When the TM60 count value overflows b Cascade connection mode TM50 and TM60 are simultaneously cleared to 00H After reset When the TCE60 flag is cleared to 0 When matches occur simultaneously between TM50 and CR50 and between TM60 and CR60 When...

Page 137: ...t mode i TM50 After reset When the TCE50 flag is cleared to 0 When a match occurs between TM50 and CR50 When the TM50 count value overflows ii TM60 Reset When the TCE60 flag is cleared to 0 When a match occurs between TM60 and CRH60 When the TM60 count value overflows ...

Page 138: ... TMC50 8 bit timer mode control register 60 TMC60 Carrier generator output control register 60 TCA60 Port mode register 3 PM3 1 8 bit timer mode control register 50 TMC50 8 bit timer mode control register 50 TMC50 is used to control the timer 50 count clock setting and the operation mode setting TMC50 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC50 to 00H ...

Page 139: ...e or timer 60 output signal in a mode other than carrier generator mode Other than above Setting prohibited TMD501 TMD500 TMD601 TMD600 Selection of operation mode for timer 50 and timer 60 Note 2 0 0 0 0 Discrete mode 8 bit timer counter mode 0 1 0 1 Cascade connection mode 16 bit timer counter mode 0 0 1 1 Carrier generator mode 1 0 1 0 Timer 50 PWM free running mode Timer 60 PWM pulse generator...

Page 140: ... the operation mode and the count clock 3 Start count operation Remarks 1 fX Main system clock oscillation frequency ceramic crystal oscillation 2 fCC Main system clock oscillation frequency RC oscillation 2 8 bit timer mode control register 60 TMC60 8 bit timer mode control register 60 TMC60 is used to control the timer 60 count clock setting and the operation mode setting TMC60 is set with a 1 b...

Page 141: ...D601 TMD600 Selection of operation mode for timer 50 and timer 60 Note 2 0 0 0 0 Discrete mode 8 bit timer counter mode 0 1 0 1 Cascade connection mode 16 bit timer counter mode 0 0 1 1 Carrier generator mode 1 0 1 0 Timer 50 PWM free running mode Timer 60 PWM pulse generator mode Other than above Setting prohibited TOE61 TOE60 Control of timer output 0 0 Output disabled 0 1 Output enabled only fo...

Page 142: ...e required value to NRZ60 by program beforehand NRZ60 No return zero data 0 Outputs low level signal carrier clock is stopped 1 Outputs carrier pulse Caution TCA60 cannot be set with a 1 bit memory manipulation instruction Be sure to use an 8 bit memory manipulation instruction to set TCA60 4 Port mode register 3 PM3 This register is used to set the I O mode of port 3 in 1 bit units When using the...

Page 143: ...rate 8 bit timer n0 as an interval timer settings must be made in the following sequence 1 Disable operation of 8 bit timer counter n0 TMn0 TCEn0 0 2 Disable timer output of TOn0 TOEn0 0 3 Set a count value in CRn0 4 Set the operation mode of timer n0 to 8 bit timer counter mode see Figures 7 4 and 7 5 5 Set the count clock for timer n0 see Tables 7 3 to 7 6 6 Enable the operation of TMn0 TCEn0 1 ...

Page 144: ...le of timer 60 output Input cycle of timer 60 output 8 Input cycle of timer 60 Remarks 1 fX Main system clock oscillation frequency 2 fXT Subsystem clock oscillation frequency Table 7 4 Interval Time of Timer 60 TCL602 TCL601 TCL600 Minimum Interval Time Maximum Interval Time Resolution 0 0 0 1 fX 0 2 µs 2 8 fX 51 2 µs 1 fX 0 2 µs 0 0 1 2 fX 0 4 µs 2 9 fX 1 02 µs 2 fX 0 4 µs 0 1 0 fTMI input cycle...

Page 145: ...1H N 00H 00H 01H 00H 01H Clear Clear Clear Count start Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement Interval time Interval time Interval time Remarks 1 Interval time N 1 t N 00H to FFH 2 n 5 6 nm 50 60 61 Figure 7 9 Timing of Interval Timer Operation with 8 Bit Resolution When CRn0 Is Set to 00H Count clock CRn0 TCEn0 INTTMn0 TOnm 00H TMn0 00H Count start Remark n ...

Page 146: ...H 01H 00H 01H 00H 01H 00H 01H FFH FFH FFH Clear Clear Clear Count start Remark n 5 6 nm 50 60 61 Figure 7 11 Timing of Interval Timer Operation with 8 Bit Resolution When CRn0 Changes from N to M N M Count clock CRn0 TCEn0 INTTMn0 TOnm TMn0 N 00H 00H N 00H 01H 00H 01H M N M N M Clear Clear Clear Count start Interrupt acknowledgement Interrupt acknowledgement CRn0 overwritten Remark n 5 6 nm 50 60 ...

Page 147: ... 7 12 Timing of Interval Timer Operation with 8 Bit Resolution When CRn0 Changes from N to M N M Count clock CRn0 TCEn0 INTTMn0 TOnm TMn0 00H 00H 00H N 1 N M N M N M 00H FFH M H Clear Clear Clear TMn0 overflows because M N CRn0 overwritten Remark n 5 6 nm 50 60 61 ...

Page 148: ...it Resolution When Timer 60 Match Signal Is Selected for Timer 50 Count Clock Timer 60 count clock CR60 TCE60 INTTM60 TO60 TM60 N 00H M 00H 00H 01H M N M 00H M 00H 00H 01H Y 1 Y 00H Y 00H Y Input clock to timer 50 timer 60 match signal TO50 INTTM50 TCE50 CR50 TM50 Clear Clear Clear Clear Count start Count start ...

Page 149: ... TOE60 0 3 Set P31 to input mode PM31 1 4 Select the external input clock for timer 60 see Table 7 5 5 Set the operation mode of timer 60 to 8 bit timer counter mode see Figures 7 4 and 7 5 6 Set a count value in CR60 7 Enable the operation of TM60 TCE60 1 Each time the valid edge is input the value of TM60 is incremented When the count value of TM60 matches the value set in CR60 TM60 is cleared t...

Page 150: ...ser s Manual U15075EJ1V0UM00 Figure 7 14 Timing of Operation of External Event Counter with 8 Bit Resolution TMI60 pin input TM60 count value CR60 TCE60 INTTM60 00H 01H 02H 03H 04H 05H N 1 N 00H 01H 02H 03H N Remark N 00H to FFH ...

Page 151: ...ared to 00H and continues counting At the same time an interrupt request signal INTTMn0 is generated The square wave output is cleared to 0 by setting TCEn0 to 0 Tables 7 5 and 7 6 show the square wave output range and Figure 7 15 shows the timing of square wave output Note In the case of timer 60 either TO60 or TO61 can be selected as the timer output pin If TO61 is selected set TOE61 1 Caution B...

Page 152: ... input cycle 2 8 fTMI 2 input cycle 1 0 0 fTMI 2 2 input cycle fTMI 2 2 input cycle 2 8 fTMI 2 2 input cycle 1 0 1 fTMI 2 3 input cycle fTMI 2 3 input cycle 2 8 fTMI 2 3 input cycle Remark fX Main system clock oscillation frequency Figure 7 15 Timing of Square Wave Output with 8 Bit Resolution Count clock CRn0 TCEn0 INTTMn0 TOnmNote N TMn0 N 00H 01H N 00H 01H N 00H 01H 00H 01H Clear Clear Clear Co...

Page 153: ...ence 1 Disable operation of 8 bit timer counter 50 TM50 and 8 bit timer counter 60 TM60 TCE50 0 TCE60 0 2 Disable timer output of TO60 TOE60 0 3 Set the count clock for timer 60 see Tables 7 5 and 7 6 4 Set the operation mode of timer 50 and 8 bit timer 60 to 16 bit timer counter mode see Figures 7 4 and 7 5 5 Set a count value in CR50 and CR60 6 Enable the operation of TM50 and TM60 TCE60 1 Note ...

Page 154: ... 1 fX 0 2 µs 2 16 fX 13 1 ms 1 fX 0 2 µs 0 0 1 2 fX 0 4 µs 2 17 fX 26 2 ms 2 fX 0 4 µs 0 1 0 fTMI input cycle fTMI input cycle 2 16 fTMI input cycle 0 1 1 fTMI 2 input cycle fTMI 2 input cycle 2 16 fTMI 2 input cycle 1 0 0 fTMI 2 2 input cycle fTMI 2 2 input cycle 2 16 fTMI 2 2 input cycle 1 0 1 fTMI 2 3 input cycle fTMI 2 3 input cycle 2 16 fTMI 2 3 input cycle Remark fX Main system clock oscilla...

Page 155: ...lse TM50 00H X X 1 01H CR50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H t Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated because TM50 does not match Interrupt acknowledgement Interrupt acknowledgement Remark Interval time 256X N 1 t X 00H to FFH N 00H to FFH Figure 7 16 Timing of Interval Timer Operation with 16 Bit Re...

Page 156: ...and 8 bit timer 60 to 16 bit timer counter mode see Figures 7 4 and 7 5 6 Set a count value in CR50 and CR60 7 Enable the operation of TM50 and TM60 TCE60 1 Note Note Start and clear of the timer in the 16 bit timer counter mode are controlled by TCE60 the value of TCE50 is invalid Each time the valid edge is input the values of TM50 and TM60 are incremented When the count values of TM50 and TM60 ...

Page 157: ...e TM50 00H X 01H CR50 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H X 1 Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated because TM50 does not match Interrupt acknowledgement Interrupt acknowledgement Remark X 00H to FFH N 00H to FFH Figure 7 17 Timing of External Event Counter Operation with 16 Bit Resolution ...

Page 158: ...vely the TO60 pin output will be inverted Through application of this mechanism square waves of any frequency can be output As soon as a match occurs TM50 and TM60 are cleared to 00H and counting continues At the same time an interrupt request signal INTTM60 is generated INTTM50 is not generated The square wave output is cleared to 0 by setting TCE60 to 0 Table 7 8 shows the square wave output ran...

Page 159: ...0 X X X 7FH 80H FFH 00H N 00H N N N X X 1 00H Not cleared because TM50 does not match Cleared because TM50 and TM60 match simultaneously Count start Interrupt not generated because TM50 does not match Interrupt acknowledgement Interrupt acknowledgement Figure 7 18 Timing of Square Wave Output with 16 Bit Resolution Note The initial value of TO60 or TO61 is low level when output is enabled Remark X...

Page 160: ...le the operation of TM50 and TM60 TCE50 1 TCE60 1 The operation of the carrier generator is as follows 1 When the count value of TM60 matches the value set in CR60 an interrupt request signal INTTM60 is generated and output of timer 60 is inverted which makes the compare register switch from CR60 to CRH60 2 After that when the count value of TM60 matches the value set in CRH60 an interrupt request...

Page 161: ...When CR60 N CRH60 M M N Count clock TM60 count value CR60 TCE60 INTTM60 M 00H N 00H 01H N CRH60 M N 00H Carrier clock N 00H 00H N M 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TM50 CR50 TCE50 INTTM50 Count pulse 0 1 0 1 0 0 1 0 1 0 NRZB60 NRZ60 TO60 or TO61 Carrier clock Clear Clear Clear Clear Count start ...

Page 162: ... Phases of Carrier Clock and NRZ60 Are Asynchronous Count clock TM60 count value CR60 TCE60 INTTM60 N 00H N CRH60 M Carrier clock N 00H 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TM50 CR50 TCE50 INTTM50 Count pulse 0 1 0 1 0 0 1 0 1 0 NRZB60 NRZ60 TO60 or TO61 Carrier clock M 00H M M 00H M 00H Clear Clear Clear Clear Count start ...

Page 163: ...When CR60 CRH60 N Count clock TM60 count value CR60 TCE60 INTTM60 N 00H 00H 00H N CRH60 N N Carrier clock 00H 00H N N 00H 01H L 00H 01H L 00H 01H L 00H L 00H 01H TM50 CR50 TCE50 INTTM50 Count pulse 0 1 0 1 0 0 1 0 1 0 NRZB60 NRZ60 TO60 or TO61 Carrier clock N N 00H Clear Clear Clear Clear Clear Count start ...

Page 164: ...operation mode of timer 50 to the PWM free running mode see Figure 7 4 5 Set the count clock for timer 50 6 Set P31 to the output mode PM31 0 and the P31 output latch to 0 and enable timer output of TO50 TOE50 1 7 Enable the operation of TM50 TCE50 1 The operation in the PWM free running mode is as follows 1 When the count value of TM50 matches the value set in CR50 an interrupt request signal INT...

Page 165: ...rflow Overflow Count start Caution When the rising edge is selected do not set the CR50 to 00H If the CR50 is set to 00H PWM output may not be performed normally Figure 7 23 Operation Timing When Overwriting CR50 When Rising Edge Is Selected 1 2 1 When setting CR50 TM50 after overflow Count clock CR50 TCE50 INTTM50 TO50 N TM50 N 00H 00H 00H 01H FFH M FFH 01H M Overflow Overflow Overflow Count star...

Page 166: ... TO50 N TM50 N 00H 00H 00H 01H FFH FFH 01H 01H 02H 01H Overflow Overflow Overflow Count start CR50 overwrite Overflow occurs but no change takes place because TO50 is high level Figure 7 24 Operation Timing in PWM Free Running Mode When Both Edges Are Selected 1 2 1 CR50 Even number Count clock CR50 TCE50 INTTM50 TO50 2N TM50 2N 00H 00H 01H FFH FFH 2N 02H FEH 01H 02H FEH Overflow Overflow Overflow...

Page 167: ... 00H Overflow Overflow Overflow Count start Caution When both edges are selected do not set CR50 to 00H 01H and FFH If the CR50 is set to these values PWM output may not be performed normally Figure 7 25 Operation Timing in PWM Free Running Mode When Both Edges Are Selected When CR50 Is Overwritten Count clock CR50 TCE50 INTTM50 TO50 2N 1 TM50 2N 00H 00H 00H 01H FFH FFH 01H 2N 1 01H 02H FEH 2N Ove...

Page 168: ... of TO60 TOE60 1 7 Enable the operation of TM60 TCE60 1 The operation in the PWM output mode is as follows 1 When the count value of TM60 matches the value set in CR60 an interrupt request signal INTTM60 is generated and output of timer 60 is inverted which makes the compare register switch from CR60 to CRH60 2 A match between TM60 and CR60 clears the TM60 value to 00H and then counting starts aga...

Page 169: ...01H 01H M 00H Clear Clear Clear Clear Count start Note The initial value of TO60 is low level when output is enabled TOE60 1 Figure 7 27 PWM Output Mode Timing When CR60 and CRH60 Are Overwritten Count clock TM60 count value CR60 TCE60 INTTM60 00H N 00H 01H N CRH60 M N TO60 or TO61Note M X Y 00H 00H X 00H X Y M Clear Clear Clear Clear Count start Note The initial value of TO60 is low level when ou...

Page 170: ...ed asynchronously to the count pulse Figure 7 28 Start Timing of 8 Bit Timer Counter Count pulse TMn0 count value 00H 01H 02H 03H 04H Timer start Remark n 5 6 2 Setting of 8 bit compare register n0 8 bit compare register n0 CRn0 can be set to 00H Therefore one pulse can be counted when the 8 bit timer operates as an event counter Figure 7 29 Timing of Operation as External Event Counter 8 Bit Reso...

Page 171: ...r The watch and interval timers can be used at the same time Figure 8 1 is a block diagram of the watch timer Figure 8 1 Block Diagram of Watch Timer fX 27 fXT fW fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 Clear 9 bit prescaler Selector Clear 5 bit counter INTWT INTWTI WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register WTM Internal bus Selector ...

Page 172: ...ified intervals Table 8 1 Interval Generated Using the Interval Timer Interval At fX 5 0 MHz At fX 4 19 MHz At fXT 32 768 kHz 2 4 1 fW 409 6 µs 489 µs 488 µs 2 5 1 fW 819 2 µs 978 µs 977 µs 2 6 1 fW 1 64 ms 1 96 ms 1 95 ms 2 7 1 fW 3 28 ms 3 91 ms 3 91 ms 2 8 1 fW 6 55 ms 7 82 ms 7 81 ms 2 9 1 fW 13 1 ms 15 6 ms 15 6 ms Remarks 1 fW Watch timer clock frequency fX 27 or fXT 2 fX Main system clock o...

Page 173: ...mer count clock selection WTM7 Prescaler interval selection WTM6 0 0 0 0 1 1 24 fW 488 s 25 fW 977 s 26 fW 1 95 ms 27 fW 3 91 ms 28 fW 7 81 ms 29 fW 15 6 ms WTM5 0 0 1 1 0 0 WTM4 0 1 0 1 0 1 Control of 5 bit counter operation WTM1 0 1 Cleared after stop Started Watch timer operation WTM0 0 1 Operation disabled both prescaler and timer cleared Operation enabled Other than above fX 27 fXT 39 1 kHz 3...

Page 174: ... to 29 1 fW seconds may occur in the overflow INTWT after the zero second start of the watch timer because the 9 bit prescaler is not cleared to 0 8 4 2 Operation as interval timer The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count value The interval can be selected by bits 4 to 6 WTM4 to WTM6 of the watch timer mode control register ...

Page 175: ... bit counter operation is enabled by setting bit 0 WTM0 of the watch mode timer mode control register WTM to 1 the interval until the first interrupt request INTWT is generated after the register is set does not exactly match the specification made with WTM3 bit 3 of WTM This is because there is a delay of one 9 bit pre scaler output cycle until the 5 bit counter starts counting Subsequently howev...

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Page 177: ...way When a runaway is detected a non maskable interrupt or the RESET signal can be generated Table 9 1 Watchdog Timer Runaway Detection Time Runaway Detection Time At fX 5 0 MHz 2 11 1 fX 410 µs 2 13 1 fX 1 64 ms 2 15 1 fX 6 55 ms 2 17 1 fX 26 2 ms fX Main system clock oscillation frequency 2 Interval timer The interval timer generates an interrupt at an arbitrary preset interval Table 9 2 Interva...

Page 178: ... Watchdog timer clock select register WDCS Watchdog timer mode register WDTM Figure 9 1 Block Diagram of Watchdog Timer Internal bus Internal bus Prescaler Selector Controller fX 26 fX 28 fX 210 3 7 bit counter TMIF4 TMMK4 TCL22 TCL21 TCL20 Watchdog timer clock select register WDCS Watchdog timer mode register WDTM Clear WDTM4 RUN WDTM3 INTWDT Maskable interrupt request RESET INTWDT Non maskable i...

Page 179: ...manipulation instruction RESET input sets WDCS to 00H Figure 9 2 Format of Watchdog Timer Clock Select Register WDCS2 0 0 1 1 WDCS1 0 1 0 1 fX 24 fX 26 fX 28 fX 210 312 5 kHz 78 1 kHz 19 5 kHz 4 88 kHz WDCS0 0 0 0 0 Setting prohibited Other than above Watchdog timer count clock selection 211 fX 213 fX 215 fX 217 fX 410 s 1 64 ms 6 55 ms 26 2 ms Interval µ 0 0 0 0 0 WDCS2 WDCS1 WDCS0 WDCS 7 6 5 4 S...

Page 180: ...de 2 Starts reset operation upon overflow occurrence 0 0 RUN 0 0 WDTM4 WDTM3 0 0 0 WDTM 7 6 5 4 Symbol Address After reset R W FFF9H 00H R W 3 2 1 0 Notes 1 Once RUN has been set 1 it cannot be cleared 0 by software Therefore when counting is started it cannot be stopped by any means other than RESET input 2 Once WDTM3 and WDTM4 have been set 1 they cannot be cleared 0 by software 3 The watchdog t...

Page 181: ...and the runaway detection time is exceeded a system reset signal or a non maskable interrupt is generated depending on the value of bit 3 WDTM3 of WDTM The watchdog timer continues operation in HALT mode but stops in STOP mode Therefore first set RUN to 1 to clear the watchdog timer before executing the STOP instruction Cautions 1 The actual runaway detection time may be up to 0 8 shorter than the...

Page 182: ...rupt mask flag WDTMK is valid and a maskable interrupt INTWDT can be generated The priority of INTWDT is set as the highest of all the maskable interrupts The interval timer continues operation in HALT mode but stops in STOP mode Therefore first set RUN to 1 to clear the interval timer before executing the STOP instruction Cautions 1 Once bit 4 WDTM4 of WDTM is set to 1 when watchdog timer mode is...

Page 183: ...analog inputs ANI0 to ANI5 is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTAD0 being issued each time A D conversion is complete 10 2 8 Bit A D Converter Configuration The 8 bit A D converter includes the following hardware Table 10 1 Configuration of 8 Bit A D Converter Item Configuration Analog inputs 6 channels ANI0 to ANI5 Registers Successive...

Page 184: ... at a voltage tap comparison voltage received from the series resistor string starting from the most significant bit MSB Upon receiving all the bits down to the least significant bit LSB that is upon the completion of A D conversion the SAR sends its contents to A D conversion result register 0 ADCR0 2 A D conversion result register 0 ADCR0 ADCR0 holds the result of A D conversion Each time A D co...

Page 185: ... conversion Caution Do not supply pins ANI0 to ANI5 with voltages that fall outside the rated range If a voltage greater than AVDD or less than AVSS even if within the absolute maximum rating is applied to any of these pins the conversion value for the corresponding channel will be undefined Furthermore the conversion values for the other channels may also be affected 7 AVSS pin The AVSS pin is a ...

Page 186: ...te 1 FR02 0 0 0 1 1 1 144 fX 120 fX 96 fX 72 fX 60 fX 48 fX FR01 0 0 1 0 0 1 28 8 s 24 s 19 2 s 14 4 s Setting prohibitedNote 2 Setting prohibitedNote 2 µ µ µ FR00 0 1 0 0 1 0 Other than above Conversion disabled Conversion enabled Setting prohibited µ ADCS0 0 FR02 FR01 FR00 0 0 0 ADM0 7 6 5 4 Symbol Address After reset R W FF80H 00H R W 3 2 1 0 Notes 1 The specifications of FR02 FR01 and FR00 mus...

Page 187: ... ADS0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets ADS0 to 00H Figure 10 3 Format of Analog Input Channel Specification Register 0 0 0 0 0 0 ADS02 ADS01 ADS00 ADS0 Symbol Address After reset R W FF84H 00H R W 7 6 5 4 3 2 1 0 Analog input channel specification Other than above ADS02 0 0 0 0 1 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 Setting prohibited ADS01 0 0 1 1 0 0 ADS00...

Page 188: ...lf of AVDD the MSB of SAR is left set If it is lower than half of AVDD the MSB is reset 6 Bit 6 of SAR is set automatically and comparison shifts to the next stage The next tap voltage of the series resistor string is selected according to bit 7 which reflects the previous comparison result as follows Bit 7 1 Three quarters of AVDD Bit 7 0 One quarter of AVDD The tap voltage is compared with the a...

Page 189: ...conversion is canceled In this case A D conversion is restarted from the beginning if ADCS0 is set 1 RESET input makes A D conversion result register 0 ADCR0 undefined 10 4 2 Input voltage and conversion result The relationships between the analog input voltage at the analog input pins ANI0 to ANI5 and the A D conversion result A D conversion result register 0 ADCR0 are represented by ADCR0 INT 25...

Page 190: ...ERIES User s Manual U15075EJ1V0UM00 190 Figure 10 5 Relationship Between Analog Input Voltage and A D Conversion Result 255 254 253 3 2 1 0 A D conversion result ADCR0 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 Input voltage AVDD ...

Page 191: ...specified in analog input channel specification register 0 ADS0 Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCR0 At the same time an interrupt request signal INTAD0 is generated Once A D conversion is activated and completed another session of A D conversion is started A D conversion is repeated until new data is written to ADM0 If data whe...

Page 192: ...ut into a conversion channel the conversion output of the channel becomes undefined which may affect the conversion output of the other channels 3 Conflict 1 Conflict between writing to A D conversion result register 0 ADCR0 at the end of conversion and reading from ADCR0 using instruction Reading from ADCR0 takes precedence After reading the new conversion result is written to ADCR0 2 Conflict be...

Page 193: ...sion operation has been stopped stop the A D conversion operation before the next conversion operation is completed Figures 10 8 and 10 9 show the timing at which the conversion result is read Figure 10 8 Conversion Result Read Timing If Conversion Result Is Undefined End of A D conversion End of A D conversion Normal conversion result Undefined value Normal conversion result is read A D conversio...

Page 194: ...version do not execute input instructions for the ports otherwise the conversion resolution may be reduced If a digital pulse is applied to a pin adjacent to the analog input pins during A D conversion coupling noise may occur that prevents an A D conversion result from being obtained as expected Avoid applying a digital pulse to pins adjacent to the analog input pins during A D conversion 8 Inter...

Page 195: ...ower to the analog circuit It is also used to supply power to the ANI0 to ANI5 input circuit If your application is designed to be changed to backup power the AVDD pin must be supplied with the same voltage level as the VDD pin as shown in Figure 10 12 Figure 10 12 AVDD Pin Handling Main power source Backup capacitor VDD AVDD VSS AVSS 10 AVDD pin input impedance A series resistor string of several...

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Page 197: ...analog inputs ANI0 to ANI5 is selected for A D conversion A D conversion is performed repeatedly with an interrupt request INTAD0 being issued each time A D conversion is complete 11 2 10 Bit A D Converter Configuration The 10 bit A D converter includes the following hardware Table 11 1 Configuration of 10 Bit A D Converter Item Configuration Analog inputs 6 channels ANI0 to ANI5 Registers Success...

Page 198: ...t LSB that is upon the completion of A D conversion the SAR sends its contents to A D conversion result register 0 ADCR0 2 A D conversion result register 0 ADCR0 ADCR0 holds the result of A D conversion Each time A D conversion ends the conversion result in the successive approximation register is loaded into ADCR0 which is a 10 bit register ADCR0 can be read with a 16 bit memory manipulation inst...

Page 199: ...5 are the 6 channel analog input pins for the A D converter They are used to receive the analog signals for A D conversion Caution Do not supply pins ANI0 to ANI5 with voltages that fall outside the rated range If a voltage greater than AVDD or less than AVSS even if within the absolute maximum rating is applied to any of these pins the conversion value for the corresponding channel will be undefi...

Page 200: ...ote 1 FR02 0 0 0 1 1 1 144 fX 120 fX 96 fX 72 fX 60 fX 48 fX FR01 0 0 1 0 0 1 28 8 s 24 s 19 2 s 14 4 s Setting prohibitedNote 2 Setting prohibitedNote 2 µ µ µ FR00 0 1 0 0 1 0 Other than above Conversion disabled Conversion enabled Setting prohibited µ ADCS0 0 FR02 FR01 FR00 0 0 0 ADM0 7 6 5 4 Symbol Address After reset R W FF80H 00H R W 3 2 1 0 Notes 1 The specifications of FR02 FR01 and FR00 mu...

Page 201: ...ADS0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears ADS0 to 00H Figure 11 3 Format of Analog Input Channel Specification Register 0 0 0 0 0 0 ADS02 ADS01 ADS00 ADS0 Symbol Address After reset R W FF84H 00H R W 7 6 5 4 3 2 1 0 Analog input channel specification Other than above ADS02 0 0 0 0 1 1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 Setting prohibited ADS01 0 0 1 1 0 0 ADS0...

Page 202: ...alf of AVDD the MSB of SAR is left set If it is lower than half of AVDD the MSB is reset 6 Bit 8 of SAR is set automatically and comparison shifts to the next stage The next tap voltage of the series resistor string is selected according to bit 9 which reflects the previous comparison result as follows Bit 9 1 Three quarters of AVDD Bit 9 0 One quarter of AVDD The tap voltage is compared with the ...

Page 203: ... is canceled In this case A D conversion is restarted from the beginning if ADCS0 is set 1 RESET input makes A D conversion result register 0 ADCR0 undefined 11 4 2 Input voltage and conversion result The relationships between the analog input voltage at the analog input pins ANI0 to ANI5 and the A D conversion result A D conversion result register 0 ADCR0 are represented by ADCR0 INT 1 024 0 5 or...

Page 204: ...r s Manual U15075EJ1V0UM00 204 Figure 11 5 Relationship Between Analog Input Voltage and A D Conversion Result 1023 1022 1021 3 2 1 0 A D conversion result ADCR0 1 2048 1 1024 3 2048 2 1024 5 2048 3 1024 2043 2048 1022 1024 2045 2048 1023 1024 2047 2048 1 Input voltage AVDD ...

Page 205: ...ut pin specified in A D input selection register 0 ADS0 Upon completion of A D conversion the conversion result is saved to A D conversion result register 0 ADCR0 At the same time an interrupt request signal INTAD0 is generated Once A D conversion is activated and completed another session of A D conversion is started A D conversion is repeated until new data is written to ADM0 If data where ADCS0...

Page 206: ...put into a conversion channel the conversion output of the channel becomes undefined which may affect the conversion output of the other channels 3 Conflict 1 Conflict between writing to A D conversion result register 0 ADCR0 at the end of conversion and reading from ADCR0 using instruction Reading from ADCR0 takes precedence After reading the new conversion result is written to ADCR0 2 Conflict b...

Page 207: ...rsion operation has been stopped stop the A D conversion operation before the next conversion operation is completed Figures 11 8 and 11 9 show the timing at which the conversion result is read Figure 11 8 Conversion Result Read Timing If Conversion Result Is Undefined End of A D conversion End of A D conversion Normal conversion result Undefined value Normal conversion result is read A D conversi...

Page 208: ...nversion do not execute input instructions for the ports otherwise the conversion resolution may be reduced If a digital pulse is applied to a pin adjacent to the analog input pins during A D conversion coupling noise may occur that prevents an A D conversion result from being obtained as expected Avoid applying a digital pulse to pins adjacent to the analog input pins during A D conversion 8 Inte...

Page 209: ...power to the analog circuit It is also used to supply power to the ANI0 to ANI5 input circuit If your application is designed to be changed to backup power the AVDD pin must be supplied with the same voltage level as the VDD pin as shown in Figure 11 12 Figure 11 12 AVDD Pin Handling Main power supply Backup capacitor VDD AVDD VSS AVSS 10 AVDD pin input impedance A series resistor string of severa...

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Page 211: ...lines SI20 and SO20 As it supports simultaneous transmission and reception 3 wire serial I O mode requires less processing time for data transmission than asynchronous serial interface mode Because in 3 wire serial I O mode it is possible to select whether 8 bit data transmission begins with the MSB or LSB serial interface 20 can be connected to any device regardless of whether that device is desi...

Page 212: ...ift clock SI20 P25 RxD20 SO20 P24 TxD20 4 Parity operation Stop bit addition Reception data counter Parity operation Stop bit addition Transmission data counter SL20 CL20 PS200 PS201 Reception enabled Reception clock Detection clock Start bit detection CSIE20 CSCK20 SCK20 P23 ASCK20 SS20 P22 Clock phase control Reception detected Internal clock output External clock input Transmission and receptio...

Page 213: ...ception detected TXE20 RXE20 CSIE20 Selector Selector Selector 1 2 1 2 Transmission clock counter Reception clock counter 4 f X 2 f X 2 3 f X 2 4 f X 2 5 f X 2 6 f X 2 7 f X 2 8 f X 2 2 SCK20 ASCK20 P23 TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 BRGC20 Internal bus Figure 12 2 Block Diagram of Baud Rate Generator 20 ...

Page 214: ... Reception buffer register 20 RXB20 RXB20 holds a reception data A new reception data is transferred from reception shift register 20 RXS20 every 1 byte data reception When the data length is seven bits the reception data is sent to bits 0 to 6 of RXB20 in which the MSB is always fixed to 0 RXB20 can be read with an 8 bit memory manipulation instruction but cannot be written RESET input makes RXB2...

Page 215: ...SE20 0 0 DAP20 DIR20 CSCK20 CKP20 CSIM20 Symbol Address After reset R W FF72H 00H R W 7 6 5 4 3 2 1 0 Operation disabled Operation enabled DIR20 0 1 First bit specification MSB LSB CSCK20 0 1 3 wire serial I O mode clock selection External clock input to the SCK20 pin Output of the dedicated baud rate generator SSE20 0 1 Not used Used DAP20 0 1 3 wire serial I O mode data phase selection Outputs a...

Page 216: ...r reset R W FF70H 00H R W 7 6 5 4 3 2 1 0 Transmit operation stop Transmit operation enable RXE20 0 1 Receive operation control Receive operation stop Receive operation enable PS201 0 0 1 1 Parity bit specification PS200 0 1 0 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Odd parity Even parity CL20 0 1 Transmit data charact...

Page 217: ...lock SCK20 output 0 1 External clock SCK20 input 0 0 1 1 1 Note 2 Note 2 0 1 0 1 LSB Internal clock SI20 Note 2 SO20 CMOS output SCK20 output Other than above Setting prohibited 3 Asynchronous serial interface mode ASIM20 CSIM20 TXE20 RXE20 CSIE20 DIR20 CSCK20 PM25 P25 PM24 P24 PM23 P23 First Bit Shift Clock P25 SI20 RxD20 Pin Function P24 SO20 TxD20 Pin Function P23 SCK20 ASCK20 Pin Function 1 Ex...

Page 218: ... 2 1 0 No parity error has occurred A parity error has occurred when the parity of transmit data does not match FE20 0 1 Flaming error flag No framing error has occurred A framing error has occurred when stop bit is not detected Note 1 OVE20 0 1 Overrun error flag No overrun error has occurred An overrun error has occurred Note 2 when the next receive operation is completed before the data is read...

Page 219: ...prohibited 2 5 MHz 1 25 MHz 625 kHz 313 kHz 156 kHz 78 1 kHz 39 1 kHz 19 5 kHz Other than above TPS201 0 0 1 1 0 0 1 1 0 TPS200 0 1 0 1 0 1 0 1 0 n 1 2 3 4 5 6 7 8 Note An external clock can be used only in UART mode Cautions 1 When writing to BRGC00 during a communication operation the output of the baud rate generator is disrupted and communications cannot be performed normally Be sure not to wr...

Page 220: ... of a clock generated from the system clock is estimated by using the following expression Baud rate Hz fX Main system clock oscillation frequency n Values in Figure 12 6 determined by the values of TPS200 to TPS203 2 n 8 Table 12 3 Example of Relationships Between System Clock and Baud Rate Error Baud Rate bps n BRGC20 Set Value fX 5 0 MHz fX 4 9152 MHz 1 200 8 70H 2 400 7 60H 4 800 6 50H 9 600 5...

Page 221: ...baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression Baud rate Hz fASCK Frequency of clock input to the ASCK20 pin Table 12 4 Relationship Between ASCK20 Pin Input Frequency and Baud Rate When BRGC20 Is Set to 80H Baud Rate bps ASCK20 Pin Input Frequency kHz 75 1 2 150 2 4 300 4 8 600 9 6 1 200 19 2 2 400 38 4 4 800 76 8 9 600 153 6 1...

Page 222: ...xD20 and P25 SI20 RxD20 pins can be used as normal I O ports 1 Register setting Operation stop mode is set by serial operation mode register 20 CSIM20 and asynchronous serial interface mode register 20 ASIM20 a Serial operation mode register 20 CSIM20 CSIM20 is set with a 1 bit or 8 bit memory manipulation instruction RESET input clears CSIM20 to 00H CSIE20 0 1 Operation control in 3 wire serial I...

Page 223: ...lation instruction RESET input sets ASIM20 to 00H TXE20 0 1 Transmit operation control Transmit operation stopped Transmit operation enabled Receive operation stopped Receive operation enabled RXE20 0 1 Receive operation control TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 ASIM20 7 6 5 4 Symbol Address After reset R W FF70H 00H R W 3 2 1 0 Caution Bits 0 and 1 must be set to 0 ...

Page 224: ...ables communications at the desired baud rate In addition the baud rate can also be defined by dividing the clock input to the ASCK20 pin The UART dedicated baud rate generator also can output the 31 25 kbps baud rate that complies with the MIDI standard 1 Register setting UART mode is set by serial operation mode register 20 CSIM20 asynchronous serial interface mode register 20 ASIM20 asynchronou...

Page 225: ... specification MSB LSB CSCK20 0 1 3 wire serial I O mode clock selection External clock input to the SCK20 pin Output of the dedicated baud rate generator SSE20 0 1 Not used Used DAP20 0 1 3 wire serial I O mode data phase selection Outputs at the falling edge of SCK20 Outputs at the rising edge of SCK20 SS20 pin selection Function of SS20 P22 pin Port function 0 1 Communication status Communicati...

Page 226: ...0 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error is generated Odd parity Even parity Receive operation control PS201 Parity bit specification PS200 CL20 0 1 SL20 Character length specification 7 bits 8 bits 1 bit 2 bits Transmit data stop bit length specification TXE20 RXE20 PS201 PS200 CL20 SL20 0 0 ASIM20 7 6 5 4 S...

Page 227: ...overrun error has occured An overrun error has occuredNote 2 when the next receive operation is completed before data is read from reception buffer register 20 FE20 0 1 0 1 Framing error flag Overrun error flag OVE20 0 0 0 0 0 PE20 FE20 OVE20 ASIS20 7 6 5 4 Symbol Address After reset R W FF71H 00H R 3 2 1 0 Notes 1 Even when the stop bit length is set to 2 bits by setting bit 2 SL20 of asynchronou...

Page 228: ...TPS203 TPS202 TPS201 TPS200 0 0 0 0 BRGC20 7 6 5 4 Symbol Address After reset R W FF73H 00H R W 3 2 1 0 Note Can only be used in the UART mode Cautions 1 When writing to BRGC20 during a communication operation the output of the baud rate generator is disrupted and communications cannot be performed normally Be sure not to write to BRGC20 during a communication operation 2 Be sure not to select n 1...

Page 229: ... a clock generated from the system clock is estimated by using the following expression Baud rate Hz fX Main system clock oscillation frequency n Values in the above table determined by the settings of TPS200 to TPS203 2 n 8 Table 12 5 Example of Relationships Between System Clock and Baud Rate Error Baud Rate bps n BRGC20 Set Value fX 5 0 MHz fX 4 9152 MHz 1 200 8 70H 2 400 7 60H 4 800 6 50H 9 60...

Page 230: ...he baud rate of a clock generated from the clock input to the ASCK20 pin is estimated by using the following expression Baud rate Hz fASCK Frequency of clock input to ASCK20 pin Table 12 6 Relationship Between ASCK20 Pin Input Frequency and Baud Rate When BRGC20 Is Set to 80H Baud Rate bps ASCK20 Pin Input Frequency kHz 75 1 2 150 2 4 300 4 8 600 9 6 1 200 19 2 2 400 38 4 4 800 76 8 9 600 153 6 19...

Page 231: ...smit Receive Data D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit Start bit One data frame Start bits 1 bit Character bits 7 bits 8 bits Parity bits Even parity odd parity 0 parity no parity Stop bits 1 bit 2 bits When 7 bits are selected as the number of character bits only the lower 7 bits bits 0 to 6 are valid in transmission the most significant bit bit 7 is ignored and in reception the most signi...

Page 232: ...g parity bit is counted and if the number is odd a parity error occurs ii Odd parity At transmission Conversely to the even parity the parity bit is determined so that the number of bits with a value of 1 in the transmit data including parity bit may be odd The parity bit value should be as follows The number of bits with a value of 1 is an odd number in transmit data 0 The number of bits with a v...

Page 233: ...e Transmission Completion Interrupt Timing a Stop bit length 1 STOP Parity D7 D6 D2 D1 D0 START TxD20 output INTST20 b Stop bit length 2 STOP Parity D7 D6 D2 D1 D0 START TxD20 output INTST20 Caution Do not rewrite asynchronous serial interface mode register 20 ASIM20 during a transmit operation If the ASIM20 register is rewritten during transmission subsequent transmission may not be able to be pe...

Page 234: ...ected after the start bit reception of one frame of data ends When one frame of data has been received the receive data in the shift register is transferred to reception buffer register 20 RXB20 and a reception completion interrupt INTSR20 is generated If an error occurs the receive data in which the error occurred is still transferred to RXB20 and INTSR20 is generated If the RXE20 bit is reset 0 ...

Page 235: ...set Table 12 7 Receive Error Causes Receive Errors Cause Parity error Transmission time parity and reception data parity do not match Framing error Stop bit not detected Overrun error Reception of next data is completed before data is read from reception buffer register Figure 12 10 Receive Error Timing a Parity error occurrence STOP Parity D7 D6 D2 D1 D0 START RxD20 input INTSR20 b Framing error ...

Page 236: ... bit 6 RXE20 of asynchronous serial interface mode register 20 ASIM20 is cleared during reception reception buffer register 20 RXB20 and the receive completion interrupt INTSR20 are as follows Parity RxD20 pin RXB20 INTSR20 3 1 2 When RXE20 is set to 0 at a time indicated by 1 RXB20 holds the previous data and INTSR20 is not generated When RXE20 is set to 0 at a time indicated by 2 RXB20 renews th...

Page 237: ...ction RESET input sets CSIM20 to 00H CSIE20 0 1 3 wire serial I O mode operation control CSIE20 SSE20 0 0 DAP20 DIR20 CSCK20 CKP20 CSIM20 Symbol Address After reset R W FF72H 00H R W 7 6 5 4 3 2 1 0 Operation disabled Operation enabled DIR20 0 1 First bit specification MSB LSB CSCK20 0 1 3 wire serial I O mode clock selection External clock input to the SCK20 pin Output of the dedicated baud rate ...

Page 238: ...eceive operation enabled RXE20 0 1 0 1 0 0 0 1 0 1 1 1 No parity Always add 0 parity at transmission Parity check is not performed at reception No parity error occurs Odd parity Even parity Receive operation control PS201 Parity bit specification PS200 CL20 0 1 SL20 Transmit data character length specification 7 bits 8 bits 1 bit 2 bits Transmit data stop bit length specification TXE20 RXE20 PS201...

Page 239: ... and communications cannot be performed normally Be sure not to write to BRGC20 during a communication operation 2 Be sure not to select n 1 during operation at fX 5 0 MHz because the resulting baud rate exceeds the rated range 3 When the external input clock is selected set port mode register 2 PM2 to input mode Remarks 1 fX Main system clock oscillation frequency 2 n Values determined by the set...

Page 240: ... Then transmit data is held in the SO20 latch and output from the SO20 pin Also receive data input to the SI20 pin is latched in the reception buffer register RXB20 SIO20 on the rise of SCK20 At the end of an 8 bit transfer the operation of TXS20 SIO20 and RXS20 stops automatically and the interrupt request signal INTCSI20 is generated Figure 12 11 3 Wire Serial I O Mode Timing 1 7 i Master operat...

Page 241: ...DO0 SCK20 SI20 Note SO20 SIO20 write INTCSI20 Note The value of the last bit previously output is output iii Slave operation when DAP20 0 CKP20 0 SSE20 1 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 Note 1 DO6 DO5 DO4 DO3 DO2 DO1 DO0Note 2 SCK20 SI20 SO20 Hi Z Hi Z SS20 SIO20 write INTCSI20 Notes 1 The value of the last bit previously output is output 2 DO0 is output until SS20 rises When S...

Page 242: ...DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SCK20 SO20 SI20 SIO20 write INTCSI20 v Slave operation when DAP20 0 CKP20 1 SSE20 0 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SCK20 SI20 SO20 SIO20 write INTCSI20 SIO20 write master Note Note The data of SI20 is loaded at the first rising edge of SCK20 Make sure that the master outputs the first bit before the first rising o...

Page 243: ...ite SS20 INTCSI20 DO0 SIO20 write master Note 1 Notes 1 The data of SI20 is loaded at the first rising edge of SCK20 Make sure that the master outputs the first bit before the first rising of SCK20 2 SO20 is high until SS20 rises after completion of DO0 output When SS20 is high SO20 is in a high impedance state vii Master operation when DAP20 1 CKP20 0 SSE20 0 1 2 3 4 5 6 7 8 DO7 DO6 DO5 DO4 DO3 D...

Page 244: ...CK20 Make sure that the master outputs the first bit before the first falling of SCK20 ix Slave operation when DAP20 1 CKP20 0 SSE20 1 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 Note 2 SCK20 SI20 Hi Z Hi Z SO20 SIO20 write SS20 INTCSI20 DO0 SIO20 write master Note 1 Notes 1 The data of SI20 is loaded at the first falling edge of SCK20 Make sure that the master outp...

Page 245: ... DO6 DO5 DO4 DO3 DO2 DO1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 SCK20 SO20 SI20 SIO20 write INTCSI20 DI0 DO0 Note The value of the last bit previously output is output xi Slave operation when DAP20 1 CKP20 1 SSE20 0 1 2 3 4 5 6 7 8 DI7 DI6 DI5 DI4 DI3 DI2 DI1 SCK20 SI20 SO20 SIO20 write INTCSI20 DO7 Note DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI0 Note The value of the last bit previously output is output ...

Page 246: ...t until SS20 rises When SS20 is high SO20 is in a high impedance state 3 Transfer start Serial transfer is started by setting transfer data to the transmission shift register TXS20 SIO20 when the following two conditions are satisfied Bit 7 CSIE20 of serial operation mode register 20 CSIM20 1 Internal serial clock is stopped or SCK20 is high after 8 bit serial transfer Caution If CSIE20 is set to ...

Page 247: ...nt Outputs and Maximum Number of Pixels Bias Method Time Slots Common Signals Used Maximum Number of Segments Maximum Number of Pixels 3 COM0 to COM2 15 5 segments 3 commons µPD789426 789436 Subseries 4 COM0 to COM3 5 20 5 segments 4 commons 3 COM0 to COM2 45 15 segments 3 commons µPD789446 789456 Subseries 1 3 4 COM0 to COM3 15 60 15 segments 4 commons 13 2 LCD Controller Driver Configuration The...

Page 248: ...LCDM02 LCDM01 LCDM00 LCD display mode register 0 LCDM0 LCD drive voltage controller V LC2 V LC1 V LC0 Segment driver Common driver COM0 COM1 COM2 COM3 3 3 2 1 0 3 2 1 0 6 5 7 4 FA00H Display data memory LCDON0 Selector Segment driver 3 2 1 0 3 2 1 0 6 5 7 4 FA04H FA0EH Note LCDON0 S4 S14 Timing controller f X 2 5 f X 2 6 f X 2 7 f XT S0 Voltage amplifier GAIN LCD voltage amplification control regi...

Page 249: ...0 LCD clock control register 0 LCDC0 LCD voltage amplification control register 0 LCDVA0 1 LCD display mode register 0 LCDM0 LCDM0 specifies whether to enable display operation It also specifies the operation mode LCD drive power supply and display mode LCDM0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets LCDM0 to 00H ...

Page 250: ...s mode 1 3 1 3 Note When the LCD display panel is not used the VAON0 and LIPS0 must be set to 0 to reduce power consumption Cautions 1 Bits 1 to 3 and 5 must be set to 0 2 When operating VAON0 follow the procedure described below A To stop voltage amplification after switching display status from on to off 1 Set to display off status by setting LCDON0 0 2 Disable outputs of all the segment buffers...

Page 251: ...X 26 78 1 kHz fX 27 39 1 kHz Note Specify an internal clock fLCD frequency of at least 32 kHz Cautions 1 Bits 4 to 7 must be set to 0 2 Before changing the LCDC0 setting be sure to stop voltage amplification VAON0 0 3 Set the frame frequency to 128 Hz or lower Remarks 1 fX Main system clock oscillation frequency 2 fXT Subsystem clock oscillation frequency 3 The parenthesized values apply to operat...

Page 252: ...CDVA0 Symbol Address After reset R W FFB3H 00H R W 7 6 5 4 3 2 1 0 GAIN 0 1 1 5 times specification of the LCD panel used is 4 5 V 1 0 times specification of the LCD panel used is 3 V 0 0 0 0 0 0 Reference voltage VLC2 level selectionNote Note Select the settings according to the specifications of the LCD panel that is used Caution Before changing the LCDVA0 setting be sure to stop voltage amplifi...

Page 253: ...ntial 7 Start output corresponding to each data memory by setting LCDON0 bit 7 of LCDM0 LCDON0 1 13 5 LCD Display Data Memory The LCD display data memory is mapped at addresses FA00H to FA0EH Data in the LCD display data memory can be displayed on the LCD panel using the LCD controller driver Figure 13 5 shows the relationship between the contents of the LCD display data memory and the segment com...

Page 254: ...tively If the contents of each bit are 1 it is converted to the select voltage and if 0 it is converted to the deselect voltage The conversion results are output to the segment pins Check with the information given above what combination of the front surface electrodes corresponding to the segment signals and the rear surface electrodes corresponding to the common signals forms display patterns in...

Page 255: ...nt signals Figure 13 6 Common Signal Waveforms COMn Three time slot mode TF 3 T VLC0 VSS VLCD VLC1 VLC2 TF 4 T COMn Four time slot mode VLC0 VLCD VLC1 VLC2 VSS T One LCD clock period TF Frame frequency Figure 13 7 Voltages and Phases of Common and Segment Signals Select Deselect Common signal Segment signal VLC0 VSS VLCD VLC0 VSS VLCD T T VLC2 VLC2 VLC1 VLC1 T One LCD clock period ...

Page 256: ...cessary to apply the select or deselect voltage to the S6 to S8 pins according to Table 13 6 at the timing of the common signals COM0 to COM2 Table 13 6 Select and Deselect Voltages COM0 to COM2 Segment Common S6 S7 S8 COM0 Select Select Deselect COM1 Select Select Deselect COM2 Select Select According to Table 13 6 it is determined that the display data memory location FA06H that corresponds to S...

Page 257: ...0 1 1 0 0 1 0 Bit 0 Bit 1 Bit 2 Bit 3 Timing strobe Data memory address LCD panel FA00H 1 2 3 4 5 6 7 8 9 A B C D E S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 S 9 S 10 S 11 S 12 S 13 S 14 COM 3 COM 2 COM 1 COM 0 Open x x x x x x Can be used to store any data because there is no corresponding segment in the LCD panel Can always be used to store any data because of the three time slot mode being used ...

Page 258: ...0 Figure 13 10 Three Time Slot LCD Drive Waveform Examples VLC0 VLC2 COM0 VLCD 0 COM0 S6 VLCD VLC1 1 3VLCD 1 3VLCD VSS0 VLC0 VLC2 COM1 VLC1 VSS0 VLC0 VLC2 COM2 VLC1 VSS0 VLC0 VLC2 S6 VLC1 VSS0 VLCD 0 COM1 S6 VLCD 1 3VLCD 1 3VLCD VLCD 0 COM2 S6 VLCD 1 3VLCD 1 3VLCD TF ...

Page 259: ...voltage to the S2 and S3 pins according to Table 13 7 at the timing of the common signals COM0 to COM3 Table 13 7 Select and Deselect Voltages COM0 to COM3 Segment Common S2 S3 COM0 Select Select COM1 Deselect Select COM2 Select Select COM3 Select Select According to Table 13 7 it is determined that the display data memory location FA02H that corresponds to S2 must contain 1101 Figure 13 13 shows ...

Page 260: ...our Time Slot LCD Panel 0 0 0 1 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 Bit 0 Bit 1 Bit 2 Bit 3 Timing strobe Data memory address LCD panel FA00H 1 2 3 4 5 6 7 8 9 A B C D S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 COM 3 COM 2 COM 1 COM 0 ...

Page 261: ...0UM00 261 Figure 13 13 Four Time Slot LCD Drive Waveform Examples TF VLC0 VLC2 COM0 VLCD 0 COM0 S2 VLCD VLC1 1 3VLCD 1 3VLCD VSS VLC0 VLC2 COM1 VLC1 VSS VLC0 VLC2 COM2 VLC1 VSS VLC0 VLC2 COM3 VLC1 VSS VLCD 0 COM1 S2 VLCD 1 3VLCD 1 3VLCD VLC0 VLC2 S2 VLC1 VSS ...

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Page 263: ...ated One interrupt source from the watchdog timer is incorporated as a non maskable interrupt 2 Maskable interrupt This interrupt undergoes mask control If two or more interrupts with the same priority are simultaneously generated each interrupt has a predetermined priority as shown in Table 14 1 A standby release signal is generated 5 external and 9 internal interrupt sources are incorporated as ...

Page 264: ... of serial interface 20 UART transmission 0012H 7 INTWTI Interval timer interrupt 0014H 8 INTTM90 Generation of match signal of 16 bit timer 90 0016H 9 INTTM50 Generation of match signal of 8 bit timer 50 0018H 10 INTTM60 Generation of match signal of 8 bit timer 60 001AH 11 INTAD0 End of A D conversion signal 001CH 12 INTWT Watch timer interrupt Internal 001EH B Maskable 13 INTKR00 Key return sig...

Page 265: ...able interrupt MK IF IE Internal bus Interrupt request Vector table address generator Standby release signal C External maskable interrupt MK IF IE Internal bus INTM0 INTM1 KRM00 Interrupt request Edge detector Vector table address generator Standby release signal INTM0 External interrupt mode register 0 INTM1 External interrupt mode register 1 KRM00 Key return mode register 00 IF Interrupt reques...

Page 266: ...Key return mode register 00 KRM00 Table 14 2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests Table 14 2 Flags Corresponding to Interrupt Request Signal Name Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag INTWDT INTP0 INTP1 INTP2 INTP3 INTSR20 INTCSI20 INTST20 INTWTI INTTM90 INTTM50 INTTM60 INTAD0 INTWT INTKR00 WD...

Page 267: ...IIF IF1 FFE1H 00H R W Interrupt request flag No interrupt request signal is generated Interrupt request signal is generated Interrupt request state XXIFX 6 5 4 3 2 1 7 0 STIF20 0 SRIF20 PIF3 PIF2 PIF1 PIF0 WDTIF IF0 R W FFE0H 00H R W Symbol Address After reset 6 5 4 3 2 1 7 0 Cautions 1 Bit 7 of IF1 and bit 6 of IF0 must be set to 0 2 The WDTIF flag is R W enabled only when a watchdog timer is use...

Page 268: ...ervicing control Interrupt servicing enabled Interrupt servicing disabled 6 5 4 3 2 1 7 0 XXMK STMK20 1 SRMK20 PMK3 PMK2 PMK1 PMK0 WDTMK MK0 R W FFE4H FFH R W Symbol Address After reset 6 5 4 3 2 1 7 0 Cautions 1 Bits 7 of MK1 and bit 6 of MK0 must be set to 1 2 If the WDTMK flag is read when the watchdog timer is used in watchdog timer mode 1 or 2 its value becomes undefined 3 Because port 3 has ...

Page 269: ... 1 1 0 1 0 1 Symbol Address After reset INTP0 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges INTP1 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges INTP2 valid edge selection Falling edge Rising edge Setting prohibited Both rising and falling edges ES00 ES01 ES11 ES10 ES20 ES21 Cautions 1 Bits 0 and 1 mus...

Page 270: ...isable interrupts After that clear 0 PIF3 then set PMK3 to 0 to enable interrupts 5 Program status word PSW The program status word is a register used to hold the instruction execution result and the current status for interrupt requests The IE flag to set maskable interrupt enable disable is mapped Besides 8 bit unit read write this register can carry out operations with a bit manipulation instru...

Page 271: ...0 Symbol Cautions 1 Bits 1 to 7 must be set to 0 2 Before setting KRM00 always set bit 6 of MK1 KRMK00 1 to disable interrupts After setting KRM00 clear KRMK00 after clearing bit 6 of IF1 KRIF00 0 to enable interrupts 3 When P00 to P03 are in input mode on chip pull up resistors are connected to P00 to P03 by the setting of KRM000 After switching to output mode the on chip pull up resistors are cu...

Page 272: ... stack in that order the IE flag is reset to 0 the contents of the vector table are loaded to the PC and then program execution branches Figure 14 9 shows the flow from non maskable interrupt request generation to acknowledgement Figure 14 10 shows the timing of non maskable interrupt acknowledgement and Figure 14 11 shows the acknowledgement operation when a number of non maskable interrupts are ...

Page 273: ...generated Interrupt servicing starts WDTM3 0 non maskable interrupt is selected WDTM Watchdog timer mode register WDT Watchdog timer Figure 14 10 Timing of Non Maskable Interrupt Request Acknowledgment Instruction Instruction Saving PSW and PC and jump to interrupt servicing Interrupt servicing program CPU processing WDTIF Figure 14 11 Non Maskable Interrupt Request Acknowledgment Second interrupt...

Page 274: ... 1 clock fCPU CPU clock When two or more maskable interrupt requests are generated at the same time they are acknowledged starting from the one assigned the highest priority by the priority specification flag A pending interrupt is acknowledged when the status where it can be acknowledged is set Figure 14 12 shows the algorithm of interrupt request acknowledgement When a maskable interrupt request...

Page 275: ... in Final Clock Under Execution Clock CPU NOP MOV A r Saving PSW and PC and jump to interrupt servicing Interrupt servicing program Interrupt 8 clocks If the interrupt request flag XXIF is generated in the final clock of the instruction interrupt request acknowledgment processing will begin after execution of the next instruction is complete Figure 14 14 shows an example whereby an interrupt reque...

Page 276: ...equest is acknowledged the EI instruction is issued and the interrupt request is enabled Example 2 Multiple interrupts are not performed because interrupts are disabled INTyy EI Main servicing RETI INTyy servicing INTxx servicing IE 0 INTxx RETI INTyy is held pending IE 0 Because interrupt requests are disabled the EI instruction has not been issued in the interrupt INTxx servicing the interrupt r...

Page 277: ...errupt is generated when a certain type of instruction is being executed the interrupt request will not be acknowledged until the instruction is completed Such instructions interrupt request pending instructions are as follows Instructions that manipulate interrupt request flag registers 0 1 IF0 and IF1 Instructions that manipulate interrupt mask flag registers 0 1 MK0 and MK1 ...

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Page 279: ...ops the entire system The power consumption of the CPU can be substantially reduced in this mode The data memory can be retained at the low voltage VDD 1 8 V Therefore this mode is useful for retaining the contents of the data memory at an extremely low current The STOP mode can be released by an interrupt request so that this mode can be used for intermittent operation However some time is requir...

Page 280: ...ime Select Register OSTS2 0 0 1 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS R W FFFAH 04H R W 7 6 5 4 3 2 1 0 OSTS1 0 1 0 212 fX 215 fX 217 fX 819 s 6 55 ms 26 2 ms OSTS0 0 0 0 Setting prohibited Symbol Address After reset Oscillation stabilization time selection Other than above µ Caution The wait time after the STOP mode is released does not include the time from STOP mode release to clock oscillation star...

Page 281: ...e 16 bit timer Operation enabled Operation stopped TM50 Operation enabled Note1 8 bit timer TM60 Operation enabled Operation enabled Note2 Watch timer Operation enabled Operation enabled Note3 Operation enabled Operation enabled Note4 Watchdog timer Operation enabled Operation stopped Serial interface Operation enabled Operation stopped Note5 A D converter Operation stopped LCD controller driver O...

Page 282: ...is executed Figure 15 2 Releasing HALT Mode by Interrupt HALT instruction Standby release signal Wait Wait HALT mode Operation mode Operation mode Clock Oscillation Remarks 1 The broken line indicates the case where the interrupt request that has released the standby mode is acknowledged 2 The wait time is as follows When vectored interrupt processing is performed 9 to 10 clocks When vectored inte...

Page 283: ...tion RESET signal Wait 215 fX 6 55 ms Reset period HALT mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation Remark fX Main system clock oscillation frequency Table 15 2 Operation After Releasing HALT Mode Releasing Source MKxx IE Operation 0 0 Executes next address instruction 0 1 Executes interrupt servicing Maskable interrupt r...

Page 284: ...System Clock Is Running Item While the subsystem clock is running While the subsystem clock is not running Main system clock Oscillation stopped CPU Operation stopped Port output latch Remains in the state existing before the selection of STOP mode 16 bit timer Operation stopped TM50 Operation enabled Note 1 8 bit timer TM60 Operation enabled Note 2 Watch timer Operation enabled Note 3 Operation s...

Page 285: ...ored interrupt processing is performed after the oscillation stabilization time has elapsed If the interrupt is disabled the instruction at the next address is executed Figure 15 4 Releasing STOP Mode by Interrupt STOP instruction Standby release signal Wait set time by OSTS STOP mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillatio...

Page 286: ...put STOP instruction RESET signal Wait STOP mode Operation mode Oscillation stabilization wait status Clock Operation mode Oscillation stops Oscillation Oscillation Reset period Remark fX Main system clock oscillation frequency Table 15 4 Operation After Releasing STOP Mode Releasing Source MKxx IE Operation 0 0 Executes next address instruction 0 1 Executes interrupt servicing Maskable interrupt ...

Page 287: ...during oscillation stabilization time just after reset clear When a high level is input to the RESET pin the reset is cleared and program execution is started after the oscillation stabilization time has elapsed The reset applied by the watchdog timer overflow is automatically cleared after reset and program execution is started after the oscillation stabilization time has elapsed see Figures 16 2...

Page 288: ...verflow in Watchdog Timer X1 Overflow in watchdog timer Internal reset signal Port pin Hi Z During normal operation Reset period oscillation continues Normal operation reset processing Oscillation stabilization time wait Figure 16 4 Reset Timing by RESET Input in STOP Mode X1 RESET Internal reset signal Port pin Delay Delay Hi Z STOP instruction execution During normal operation Reset period oscil...

Page 289: ...gister CR90 FFFFH Control register TMC90 00H 16 bit timer Capture register TCP90 Undefined Timer counter TM50 TM60 00H Compare register CR50 CR60 CRH60 Undefined 8 bit timer Mode control register TMC50 TMC60 00H Watch timer Mode control register WTM 00H Clock select register WDCS 00H Watchdog timer Mode register WDTM 00H Serial operation mode register CSIM20 00H Asynchronous serial interface mode ...

Page 290: ...Status After Reset Display mode register LCDM0 00H Clock control register LCDC0 00H LCD controller driver Voltage amplification control register LCDVA0 00H Request flag register IF0 IF1 00H Mask flag register MK0 MK1 FFH External interrupt mode register INTM0 INTM1 00H Interrupt Key return mode register KRM00 00H ...

Page 291: ...Mask ROM Versions Flash Memory Version Mask ROM Version Part Number Item µPD78F9436 µPD78F9456 µPD789425 789435 µPD789426 789436 µPD789445 789455 µPD789446 789456 ROM 12 KB 16 KB 12 KB 16 KB 12 KB 16 KB High speed RAM 512 bytes Internal memory LCD display RAM 5 bytes 15 bytes 5 bytes 15 bytes IC pin Not provided Provided VPP pin Provided Not provided Electrical specifications Varies depending on f...

Page 292: ...unication mode The flash memory is written by using Flashpro III and by means of serial communication Select a communication mode from those listed in Table 17 2 To select a communication mode the format shown in Figure 17 1 is used Each communication mode is selected by the number of VPP pulses shown in Table 17 2 Table 17 2 Communication Mode Communication Mode Pins Used Number of VPP Pulses 3 w...

Page 293: ...check Checks erased state of entire memory Data write Write to flash memory based on write start address and number of data written number of bytes Batch verify Compares all contents of memory with input data 17 1 3 Flashpro III connection example How the Flashpro III is connected to the µPD78F9436 or 78F9456 differs depending on the communication mode 3 wire serial I O or UART Figures 17 2 and 17...

Page 294: ...F9436 78F9456 294 User s Manual U15075EJ1V0UM00 Figure 17 3 Flashpro III Connection Example in UART Mode VPPnNote VDD RESET SI SO GND VPP VDD AVDD RESET CLK X1 RxD20 TxD20 VSS AVSS Flashpro III PD78F9436 78F9456 µ Note n 1 2 ...

Page 295: ...ulses Note 1 COMM PORT SIO ch0 On Target Board CPU CLK In Flashpro On Target Board 4 1943 MHz SIO CLK 1 0 MHz In Flashpro 4 0 MHz 3 wire serial I O SIO CLK 1 0 MHz 0 COMM PORT UART ch0 CPU CLK On Target Board On Target Board 4 1943 MHz UART UART BPS 9600 bps Note 2 8 Notes 1 The number of VPP pulses supplied from Flashpro III when serial communication is initialized The pins to be used for communi...

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Page 297: ...53 Whether a pull up resistor is to be incorporated can be specified in 1 bit units For P50 to P53 port 5 a mask option is used to specify whether a pull up resistor is to be incorporated The mask option is selectable in 1 bit units Caution Flash memory versions do not have a mask option based on chip pull up resistor function ...

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Page 299: ...specification Indirect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either functional names X A C etc or absolute names names in parenthesis in the table below R0 R1 R2 etc can be used for description Table 19 1 Operand Identifiers and Description...

Page 300: ...y flag AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag NMIS Flag indicating non maskable interrupt servicing in progress Memory contents indicated by address or register contents in parenthesis XH XL Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR V Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp...

Page 301: ...r A 2 4 sfr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte x x x A PSW 2 4 A PSW PSW A 2 4 PSW A x x x A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL byte HL byte A 2 6 HL byte A XCH A X 1 4 A X A r Note 2 2 6 A r A saddr 2 6 A saddr A sfr 2 6 A sfr A DE 1 8 A DE A HL 1 8 A HL A HL byte 2 8 A HL byte Notes 1 Except r A 2 Except r A X Remark One inst...

Page 302: ... HL byte 2 6 A CY A HL byte x x x ADDC A byte 2 4 A CY A byte CY x x x saddr byte 3 6 saddr CY saddr byte CY x x x A r 2 4 A CY A r CY x x x A saddr 2 4 A CY A saddr CY x x x A addr16 3 8 A CY A addr16 CY x x x A HL 1 6 A CY A HL CY x x x A HL byte 2 6 A CY A HL byte CY x x x SUB A byte 2 4 A CY A byte x x x saddr byte 3 6 saddr CY saddr byte x x x A r 2 4 A CY A r x x x A saddr 2 4 A CY A saddr x...

Page 303: ...ddr saddr byte x A r 2 4 A A r x A saddr 2 4 A A saddr x A addr16 3 8 A A addr16 x A HL 1 6 A A HL x A HL byte 2 6 A A HL byte x OR A byte 2 4 A A byte x saddr byte 3 6 saddr saddr byte x A r 2 4 A A r x A saddr 2 4 A A saddr x A addr16 3 8 A A addr16 x A HL 1 6 A A HL x A HL byte 2 6 A A HL byte x XOR A byte 2 4 A A V byte x saddr byte 3 6 saddr saddr V byte x A r 2 4 A A V r x A saddr 2 4 A A V ...

Page 304: ...x x DEC r 2 4 r r 1 x x saddr 2 4 saddr saddr 1 x x INCW rp 1 4 rp rp 1 DECW rp 1 4 rp rp 1 ROR A 1 1 2 CY A7 A0 Am 1 Am 1 x ROL A 1 1 2 CY A0 A7 Am 1 Am 1 x RORC A 1 1 2 CY A0 A7 CY Am 1 Am 1 x ROLC A 1 1 2 CY A7 A0 CY Am 1 Am 1 x SET1 saddr bit 3 6 saddr bit 1 sfr bit 3 6 sfr bit 1 A bit 2 4 A bit 1 PSW bit 3 6 PSW bit 1 x x x HL bit 2 10 HL bit 1 CLR1 saddr bit 3 6 saddr bit 0 sfr bit 3 6 sfr b...

Page 305: ...saddr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 BT saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 PSW bit addr16 4 10 PC PC 4 jdisp8 if PSW bit 1 BF saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 0 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 3 8 PC PC 3 jdisp8...

Page 306: ...yte addr16 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOVNote XCHNote ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV MOV INC DEC B C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV DBNZ INC DEC a...

Page 307: ...Note saddrp SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW SP MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand 1st Operand addr16 None A bit BT BF SET1 CLR1 sfr bit BT BF SET1 CLR1 saddr bit BT BF SET1 CLR1 PSW bit BT BF SET1 CLR1 HL bit SET1 CLR1 CY SET1 CLR1 NOT1 ...

Page 308: ...V0UM00 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand 1st Operand AX addr16 addr5 addr16 Basic Instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound Instructions DBNZ 5 Other instructions RET RETI NOP EI DI HALT STOP ...

Page 309: ...Subseries Figure A 1 shows development tools Support to PC98 NX Series Unless specified otherwise the products supported by IBM PC AT compatibles can be used in PC98 NX Series When using the PC98 NX Series refer to the explanation of IBM PC AT compatibles Windows Unless specified otherwise Windows indicates the following operating systems Windows 3 1 Windows 95 Windows NT Ver 4 0 ...

Page 310: ...C compiler package System simulator Device file C compiler source file Integrated debugger Embedded software OS Host machine PC or EWS Interface adapter In circuit emulator Emulation board Emulation probe Conversion adapter Target system Flash programmer Flash memory writing adapter Flash memory Flash memory writing tools Power supply unit ...

Page 311: ...ler package CC78K0S C compiler package Part number µS CC78K0S File containing the information inherent to the device Used in combination with optional RA78K0S CC78K0S and SM78K0S DF789456 Note Device file Part number µS DF789456 Source file of functions for generating object library included in C compiler package Necessary for changing object library included in C compiler package according to cus...

Page 312: ...grammer Dedicated flash programmer for microcomputers incorporating flash memory FA 64GK Flash memory writing adapter Adapter for writing to flash memory and connected to Flashpro III FA 64GK for 64 pin plastic TQFP fine pitch GK 9ET type Remark The FL PR3 and FA 64GK are products made by Naito Densei Machida Mfg Co Ltd TEL 81 44 822 3813 ...

Page 313: ...pter necessary when using IBM PC AT compatible as host machine of IE 78K0S NS ISA bus supported IE 70000 PCI IF Interface adapter Adapter necessary when using personal computer incorporating PCI bus as host machine of IE 78K0S NS IE 789456 NS EM1 Emulation board Board for emulating the peripheral hardware inherent to the device Used in combination with in circuit emulator NP 64GK Emulation probe P...

Page 314: ...µS ID78K0S NS Host Machine OS Supply Media AA13 PC 9800 series Japanese Windows Note 3 5 2HD FD AB13 Japanese Windows Note BB13 IBM PC AT compatibles English Windows Note 3 5 2HC FD Note Also operates under the DOS environment Debugs program at C source level or assembler level while simulating operation of target system on host machine SM78K0S runs under Windows By using SM78K0S the logic and per...

Page 315: ... execution sequences are controlled to switch the task to be executed next Caution when used under PC environment The MX78K0S is a DOS based application Use this software in the DOS prompt when running it on Windows MX78K0S OS Part number µS MX78K0S Remark in the part number differs depending on the host machines and operating systems to be used µS MX78K0S Host Machine OS Supply Media AA13 PC 9800...

Page 316: ...User s Manual U15075EJ1V0UM00 316 MEMO ...

Page 317: ... register 60 TCA60 142 E 8 bit compare register 50 CR50 135 8 bit compare register 60 CR60 135 8 bit compare register H60 CRH60 135 8 bit timer counter 50 TM50 136 8 bit timer counter 60 TM60 136 8 bit timer mode control register 50 TMC50 138 139 8 bit timer mode control register 60 TMC60 140 141 External interrupt mode register 0 INTM0 269 External interrupt mode register 1 INTM1 269 270 I Interr...

Page 318: ...p resistor option register B2 PUB2 99 Pull up resistor option register B3 PUB3 99 Pull up resistor option register B7 PUB7 100 Pull up resistor option register B8 PUB8 100 Pull up resistor option register B9 PUB9 101 R Receive buffer register 20 RXB20 214 S Serial operation mode register 20 CSIM20 215 222 225 237 Subclock control register CSS 107 Suboscillation mode register SCKM 106 16 bit captur...

Page 319: ...0 8 bit compare register 60 135 CR90 16 bit compare register 90 118 CRH60 8 bit compare register H60 135 CSIM20 Serial operation mode register 20 215 222 225 237 CSS Subclock control register 107 I IF0 Interrupt request flag register 0 267 IF1 Interrupt request flag register 1 267 INTM0 External interrupt mode register 0 269 INTM1 External interrupt mode register 1 269 270 K KRM00 Key return mode ...

Page 320: ...register B3 99 PUB7 Pull up resistor option register B7 100 PUB8 Pull up resistor option register B8 100 PUB9 Pull up resistor option register B9 101 R RXB20 Receive buffer register 20 214 S SCKM Suboscillation mode register 106 T TCA60 Carrier generator output control register 60 142 TCP90 16 bit capture register 90 118 TM50 8 bit timer counter 50 136 TM60 8 bit timer counter 60 136 TM90 16 bit t...

Page 321: ... 02 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6462 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 044 435 9608 I ...

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