CHAPTER 4 BUS CONTROL FUNCTION
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User’s Manual U14492EJ3V0UD
4.7
Idle State Insertion Function
To facilitate interfacing with low-speed memory devices, a set number of idle states (TI) can be inserted into the
starting bus cycle after the T3 state to secure the data output float delay time (t
DF
) of the memory when each CS
space is read accessed. The bus cycle following the T3 state starts after the inserted idle state(s).
Idle states are inserted at the following timing.
•
After the read cycle for SRAM, external I/O, or external ROM.
The idle state insertion setting can be specified using the bus cycle control register (BCC). Idle state insertion is
automatically programmed for all memory blocks immediately after a system reset.
(1) Bus cycle control register (BCC)
This register can be read/written in 16-bit units.
Cautions 1. Idle states cannot be inserted in internal ROM, internal RAM, on-chip peripheral I/O, or
programmable peripheral I/O areas.
2. Write to the BCC register after reset, and then do not change the set values. Also, do
not access an external memory area other than the one for this initialization routine
until the initial setting for this register is complete. However, it is possible to access
external memory areas whose initial settings are complete.
CS4
CS0
BCC
CSn signal
15
BC71
14
0
0
0
0
0
0
0
0
13
BC61
12
11
BC51
10
9
BC41
8
7
BC31
6
5
BC21
4
3
BC11
2
1
BC01
0
Address
FFFFF48AH
Initial value
AAAAH
CS7
CS6
CS5
CS3
CS2
CS1
Bit Position
Bit Name
Function
15, 13, 11, 9,
7, 5, 3, 1
BCn1
(n = 0 to 7)
Specifies the insertion of idle states after the T3 state in each CSn space.
0: Idle state not inserted
1: Idle state inserted
