NEC mPD70F3116GJ(A)-UEN, User Manual

Page: 776 / 832

CHAPTER 18 ELECTRICAL SPECIFICATIONS
776
User’s Manual U14492EJ3V0UD
(4) Multiplex bus timing
(a) CLKOUT asynchronous (T
A
= –40 to
++++
85
°°°°
C:
µµµµ
PD703116, 703116(A), 70F3116, 70F3116(A),
T
A
= –40 to
++++
110
°°°°
C:
µµµµ
PD703116(A1), 70F3116(A1),
V
DD3
= CV
DD
= 3.0 to 3.6 V, V
DD5
= 5 V
±±±±
0.5 V, V
SS3
= V
SS5
= CV
SS
= 0 V,
output pin load capacitance: C
L
= 50 pF)
Parameter Symbol Conditions MIN. MAX. Unit
Address setup time (to ASTB
↓
)
<16> t
SAST
(0.5 + w
AS
)T – 16 ns
Address hold time (from ASTB
↓
)
<17> t
HSTA
(0.5 + w
AH
)T – 15 ns
Address float delay time from RD
↓
<18> t
FRDA
11 ns
Data input setup time from address <19> t
SAID
(2 + w + w
AS
+ w
AH
)T
– 40
ns
Data input setup time from RD
↓
<20> t
SRDID
(1 + w)T – 40 ns
Delay time from ASTB
↓
to RD, LWR, UWR
↓
<21> t
DSTRDWR
(0.5 + w
AH
)T – 15 ns
Data input hold time (from RD
↑
)
<22> t
HRDID
0 ns
Address output time from RD
↑
<23> t
DRDA
(1 + i)T – 15 ns
Delay time from RD, LWR, UWR
↑
to ASTB
↑
<24> t
DRDWRST
0.5T – 15 ns
Delay time from RD
↑
to ASTB
↓
<25> t
DRDST
(1.5 + i + w
AS
)T
– 15
ns
RD, LWR, UWR low-level width <26> t
WRDWRL
(1 + w)T – 22 ns
ASTB high-level width <27> t
WSTH
(1 + w
AS
)T – 15 ns
Data output time from LWR, UWR
↓
<28> t
DWROD
10 ns
Data output setup time (to LWR, UWR
↑
)
<29> t
SODWR
(1 + w)T – 25 ns
Data output hold time (from LWR, UWR
↑
)
<30> t
HWROD
T – 20 ns
<31> t
SAWT1
w
≥
1
(1.5 + w
AS
+ w
AH
)T
– 40
ns WAIT setup time (to address)
<32> t
SAWT2
(1.5 + w + w
AS
+ w
AH
)T
– 40
ns
<33> t
HAWT1
w
≥
1
(0.5 + w + w
AS
+ w
AH
)T ns WAIT hold time (from address)
<34> t
HAWT2
(1.5 + w + w
AS
+ w
AH
)T ns
<35> t
SSTWT1
w
≥
1
(1 + w
AH
)T – 32 ns
WAIT setup time (to ASTB
↓
)
<36> t
SSTWT2
(1 + w + w
AH
)T
– 32
ns
<37> t
HSTWT1
w
≥
1
(w + w
AH
)T ns
WAIT hold time (from ASTB
↓
)
<38> t
HSTWT2
(1 + w + w
AH
)T ns
HLDRQ high-level width <39> t
WHQH
T + 10 ns
HLDAK low-level width <40> t
WHAL
T – 15 ns
Delay time from address float to HLDAK
↓
<41> t
DFHA
–12 ns
Delay time from HLDAK
↑
to bus output
<42> t
DHAC
–7 ns
Delay time from HLDRQ
↓
to HLDAK
↓
<43> t
DHQHA1
2T ns
Delay time from HLDRQ
↑
to HLDAK
↑
<44> t
DHQHA2
0.5T 1.5T + 30 ns
Remarks 1. T = t
CYK
2. w: Number of wait clocks inserted in the bus cycle
The sampling timing changes when a programmable wait is inserted.
3. i: Number of idle states inserted after the read cycle (0 or 1)
4. w
AS
: Number of address setup wait states (0 or 1)
5. w
AH
: Number of address hold wait states (0 or 1)
6. Observe at least either of the data input hold time t
HKID
or
t
HRDID
.