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NEC mPD70F3116GJ(A)-UEN, User Manual

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NEC mPD70F3116GJ(A)-UEN User Manual Download Page 512

CHAPTER  10   SERIAL  INTERFACE  FUNCTION

User’s Manual  U14492EJ3V0UD

512

Figure 10-31.  Timing Chart of Next Transfer Reservation Period (2/2)

(c)  When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 1

SCKn

(I/O)

INTCSIn

interrupt

Reservation period: 6.5 SCKn cycles

(d)  When data length: 16 bits, operation mode: CKP bit = 0, DAP bit = 1

SCKn

 (I/O)

INTCSIn

interrupt

Reservation period: 14.5 SCKn cycles

Remark

  n = 0, 1

Summary of Contents for mPD70F3116GJ(A)-UEN

Page 1: ...J3V0UD00 3rd edition Date Published February 2003 N CP K V850E IA1 TM 32 Bit Single Chip Microcontrollers Hardware User s Manual µ µ µ µPD703116 µ µ µ µPD703116 A µ µ µ µPD703116 A1 µ µ µ µPD70F3116 µ µ µ µPD70F3116 A µ µ µ µPD70F3116 A1 ...

Page 2: ...2 User s Manual U14492EJ3V0UD MEMO ...

Page 3: ...t pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to VDD or GND with a resistor if it is considered to have a possibility of being an output pin ...

Page 4: ...fety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Ele...

Page 5: ...1 6841 1138 Fax 021 6841 1137 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 Fax 6250 3583 J02 11 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 Sucursal en España Madrid Spain Tel 091 504 27 87 Fax 091 504 28 60 Vélizy Villacoublay France Tel 01 30 67 58 00 Fax...

Page 6: ...dition of description to 6 3 8 DMA trigger factor registers 0 to 3 DTFR0 to DTFR3 p 158 Modification of description in Table 6 1 Relationship Between Transfer Type and Transfer Object p 158 Modification of description in Remark in 6 7 1 Transfer type and transfer object pp 159 160 Modification and addition of description in 6 9 Next Address Setting Function p 161 Modification of description in 6 1...

Page 7: ...peration How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering logic circuits and microcontrollers Cautions 1 The application examples in this manual apply to standard quality grade products for general electronic systems When using an example in this manual for an application that requires a special quality grade produ...

Page 8: ...d lower address on the bottom Note Footnote for item marked with Note in the text Caution Information requiring particular attention Remark Supplementary information Numeric representation Binary xxxx or xxxxB Decimal xxxx Hexadecimal xxxxH Prefix indicating power of 2 address space memory capacity K kilo 2 10 1 024 M mega 2 20 1 024 2 G giga 2 30 1 024 3 Data type Word 32 bits Halfword 16 bits By...

Page 9: ...gger Operation WindowsTM Based U15181E SM850 Ver 2 40 System Simulator Operation Windows Based U15182E SM850 Ver 2 00 or Later System Simulator External Part User Open Interface Specifications U14873E Basics U13430E Installation U13410E RX850 Ver 3 13 or Later Real Time OS Technical U13431E Basics U13773E Installation U13774E RX850 Pro Ver 3 13 Real Time OS Technical U13772E RD850 Ver 3 01 Task De...

Page 10: ...ures 62 3 2 CPU Register Set 63 3 2 1 Program register set 64 3 2 2 System register set 65 3 3 Operation Modes 67 3 3 1 Operation modes 67 3 3 2 Operation mode specification 68 3 4 Address Space 69 3 4 1 CPU address space 69 3 4 2 Image 70 3 4 3 Wrap around of CPU address space 71 3 4 4 Memory map 72 3 4 5 Area 73 3 4 6 External memory expansion 78 3 4 7 Recommended use of address space 79 3 4 8 O...

Page 11: ... 5 MEMORY ACCESS CONTROL FUNCTION 132 5 1 SRAM External ROM External I O Interface 132 5 1 1 Features 132 5 1 2 SRAM external ROM external I O access 133 CHAPTER 6 DMA FUNCTIONS DMA CONTROLLER 138 6 1 Features 138 6 2 Configuration 139 6 3 Control Registers 140 6 3 1 DMA source address registers 0 to 3 DSA0 to DSA3 140 6 3 2 DMA destination address registers 0 to 3 DDA0 to DDA3 142 6 3 3 DMA trans...

Page 12: ...le Interrupts 172 7 3 1 Operation 172 7 3 2 Restore 174 7 3 3 Priorities of maskable interrupts 175 7 3 4 Interrupt control register xxICn 179 7 3 5 Interrupt mask registers 0 to 3 IMR0 to IMR3 182 7 3 6 In service priority register ISPR 183 7 3 7 Maskable interrupt status flag ID 184 7 3 8 Interrupt trigger mode selection 185 7 4 Software Exception 194 7 4 1 Operation 194 7 4 2 Restore 195 7 4 3 ...

Page 13: ...9 1 6 Operation timing 289 9 2 Timer 1 298 9 2 1 Features timer 1 298 9 2 2 Function overview timer 1 298 9 2 3 Basic configuration 300 9 2 4 Control registers 307 9 2 5 Operation 318 9 2 6 Supplementary description of internal operation 330 9 3 Timer 2 334 9 3 1 Features timer 2 334 9 3 2 Function overview timer 2 334 9 3 3 Basic configuration 336 9 3 4 Control registers 343 9 3 5 Operation 359 9...

Page 14: ...ation 459 10 3 6 Synchronous mode 469 10 3 7 Dedicated baud rate generators 1 2 BRG1 BRG2 474 10 4 Clocked Serial Interfaces 0 1 CSI0 CSI1 482 10 4 1 Features 482 10 4 2 Configuration 483 10 4 3 Control registers 486 10 4 4 Operation 500 10 4 5 Output pins 515 10 4 6 Dedicated baud rate generator 3 BRG3 516 CHAPTER 11 FCAN CONTROLLER 520 11 1 Function Overview 520 11 2 Configuration 521 11 3 Confi...

Page 15: ...Down FCAN Controller 625 11 17 Cautions on Use 626 CHAPTER 12 NBD FUNCTION µ µ µ µPD70F3116 627 12 1 Overview 627 12 2 NBD Function Register Map 628 12 3 NBD Function Protocol 629 12 4 NBD Function 632 12 4 1 RAM monitoring accessing NBD space 632 12 4 2 Event detection function 634 12 4 3 Chip ID registers TID0 to TID2 636 12 5 Control Registers 637 12 6 Restrictions on NBD 640 12 6 1 General res...

Page 16: ... interrupt in timer trigger mode 672 13 10 6 Timing that makes the A D conversion result undefined 672 13 11 How to Read A D Converter Characteristics Table 673 CHAPTER 14 PORT FUNCTIONS 677 14 1 Features 677 14 2 Basic Configuration of Ports 677 14 3 Pin Functions of Each Port 692 14 3 1 Port 0 692 14 3 2 Port 1 693 14 3 3 Port 2 696 14 3 4 Port 3 699 14 3 5 Port 4 701 14 3 6 Port DH 703 14 3 7 P...

Page 17: ...Self programming function number 744 16 7 7 Calling parameters 745 16 7 8 Contents of RAM parameters 746 16 7 9 Errors during self programming 747 16 7 10 Flash information 747 16 7 11 Area number 748 16 7 12 Flash programming mode control register FLPMC 749 16 7 13 Calling device internal processing 751 16 7 14 Erasing flash memory flow 754 16 7 15 Continuous writing flow 755 16 7 16 Internal ver...

Page 18: ...18 User s Manual U14492EJ3V0UD APPENDIX C INSTRUCTION SET LIST 805 C 1 Functions 805 C 2 Instruction Set Alphabetical Order 808 APPENDIX D INDEX 814 APPENDIX E REVISION HISTORY 823 ...

Page 19: ...160 7 1 Servicing Configuration of Non Maskable Interrupt 168 7 2 Acknowledging Non Maskable Interrupt Request 169 7 3 RETI Instruction Processing 170 7 4 Servicing Configuration of Maskable Interrupt 173 7 5 RETI Instruction Processing 174 7 6 Example of Servicing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced 176 7 7 Example of Servicing Interrupt Requests Gene...

Page 20: ...n Timing in PWM Mode 0 Symmetric Triangular Wave BFCMnx 0000H 265 9 19 Change Timing from 100 Duty State PWM Mode 0 266 9 20 Operation Timing in PWM Mode 1 Asymmetric Triangular Wave 270 9 21 Overall Operation Image of PWM Mode 1 Asymmetric Triangular Wave 271 9 22 Operation Timing in PWM Mode 1 Asymmetric Triangular Wave BFCMnx CM0n3 272 9 23 Operation Timing in PWM Mode 1 Asymmetric Triangular W...

Page 21: ...f TM1n Operation When Interval Operation and Transfer Operation Are Combined 327 9 55 Example of TM1n Operation in UDC Mode 329 9 56 Clear Operation upon Match with CM1n0 During TM1n Up Count Operation 330 9 57 Clear Operation upon Match with CM1n1 During TM1n Down Count Operation 330 9 58 Count Value Clear Operation upon Compare Match 331 9 59 Internal Operation During Transfer Operation 332 9 60...

Page 22: ...LE0 Register s ODLEn2 to ODLEn0 Bits 0 374 9 79 Signal Output Operation Toggle Mode 2 and Toggle Mode 3 When OCTLE0 Register s SWFEn Bit 0 and ODELE0 Register s ODLEn2 to ODLEn0 Bits 0 375 9 80 Signal Output Operation During Software Control When OCTLE0 Register s OTMEn1 OTMEn0 Bits Arbitrary SWFEn Bit 1 and ODELE0 Register s ODLEn2 to ODLEn0 Bits 0 375 9 81 Signal Output Operation During Delay Ou...

Page 23: ...nous Mode 469 10 21 Transmission Reception Timing Chart for Synchronous Mode 470 10 22 Reception Completion Interrupt and Error Interrupt Generation Timing During Synchronous Mode Reception 473 10 23 Block Diagram of Baud Rate Generators 1 2 BRG1 BRG2 474 10 24 Allowable Baud Rate Range During Reception 480 10 25 Block Diagram of Clocked Serial Interface 485 10 26 Timing Chart in Single Transfer M...

Page 24: ...C1SYNC Settings 604 11 32 CAN1 Interrupt Enable Register C1IE Settings 605 11 33 CAN1 Definition Register C1DEF Settings 606 11 34 CAN1 Control Register C1CTRL Settings 607 11 35 CAN1 Address Mask a Registers L and H C1MASKLa and C1MASKHa a 0 to 3 Settings 608 11 36 Message Buffer Settings 609 11 37 CAN Message Configuration Registers 00 to 31 M_CONF00 to M_CONF31 Settings 610 11 38 CAN Message Co...

Page 25: ...4 Conversion Result Read Timing When Conversion Result Is Undefined 672 13 15 Conversion Result Read Timing When Conversion Result Is Normal 672 13 16 Overall Error 673 13 17 Quantization Error 674 13 18 Zero Scale Error 674 13 19 Full Scale Error 675 13 20 Differential Linearity Error 675 13 21 Integral Linearity Error 676 13 22 Sampling Time 676 14 1 Type A Block Diagram 681 14 2 Type B Block Di...

Page 26: ... 16 14 Example of Self Programming Circuit Configuration 741 16 15 Timing to Apply Voltage to VPP Pin 742 16 16 Area Configuration 748 16 17 Erasing Flash Memory Flow 754 16 18 Continuous Writing Flow 755 16 19 Internal Verify Flow 756 16 20 Acquiring Flash Information Flow 757 16 21 Functional Outline of Self Programming Library 758 16 22 Outline of Self Programming Library Configuration 759 17 1...

Page 27: ...pt Request 221 8 6 Operation Status in Software STOP Mode 222 8 7 Operation After Software STOP Mode Is Released by Interrupt Request 223 8 8 Counting Time Examples fXX 10 fX 225 9 1 Timer 0 Operation Modes 230 9 2 Output Status of External Pulse Output In Case of TO0n0 256 9 3 Timer 0 TM0n Operation Modes 258 9 4 Timer 1 Configuration List 300 9 5 Timer 1 TM1n Clear Conditions 303 9 6 Capture Tri...

Page 28: ... 11 13 Error Counter 543 11 14 Addresses of M_DLCn n 00 to 31 551 11 15 Addresses of M_CTRLn n 00 to 31 554 11 16 Addresses of M_TIMEn n 00 to 31 555 11 17 Addresses of M_DATAnx n 00 to 31 x 0 to 7 557 11 18 Addresses of M_IDLn n 00 to 31 559 11 19 Addresses of M_IDHn n 00 to 31 559 11 20 Addresses of M_CONFn n 00 to 31 561 11 21 Addresses of M_STATn n 00 to 31 563 11 22 Addresses of SC_STATn n 00...

Page 29: ...tion of V850E IA1 Flash Programming Adapter FA 144GJ 8EU 730 16 2 Pins Used by Each Serial Interface 733 16 3 List of Communication Mode 737 16 4 Commands for Controlling Flash Memory 738 16 5 Response Commands 739 16 6 Function List 740 16 7 Software Environmental Conditions 743 16 8 Self Programming Function Number 744 16 9 Calling Parameters 745 16 10 Description of RAM Parameter 746 16 11 Erro...

Page 30: ...ing processing by the on chip interrupt controller also is fast this CPU is suited to the realm of advanced real time control 2 External bus interface function As the external bus interface there is a multiplex bus configuration that is an address bus 24 bits and data bus select 8 bits or 16 bits suitable for compact system design SRAM and ROM memories can be connected In the DMA controller a tran...

Page 31: ...rovided Provided pins also used with CSI1 UART2 Provided Not provided CSI0 Provided Provided CSI1 Provided Provided pins also used with UART1 Serial interface FCAN Provided Not provided Debug support function NBD Provided Not provided Analog input Total of two circuits 16 ch A D converter 0 8 ch A D converter 1 8 ch Total of two circuits 14 ch A D converter 0 6 ch A D converter 1 8 ch A D converte...

Page 32: ...ons Signed load instructions Memory space 256 MB linear address space shared by program and data Chip select output function 8 spaces Memory block division function 2 4 or 8 MB block Programmable wait function Idle state insertion function External bus interface 16 bit data bus address data multiplex 16 8 bit bus sizing function Bus hold function External wait function On chip memory Product Name ...

Page 33: ...channel Serial interface SIO Asynchronous serial interface UART 3 channels Clocked serial interface CSI 2 channels FCAN Full Controller Area Network 1 channel NBD Non Break Debug function 1 channel µPD70F3116 only RAM monitoring Event detection A D converter 10 bit resolution A D converter 8 channels 2 units Clock generator Multiplication function 1 2 5 5 10 using PLL clock synthesizer Divide by 2...

Page 34: ... UEN 144 pin plastic LQFP fine pitch 20 20 Special Remark xxx ROM code suffix Please refer to Quality Grades on NEC Semiconductor Devices Document No C11531E published by NEC Electronics Corporation to know the specification of quality grade on the devices and its recommended applications Differences between µ µ µ µPD703116 703116 A 703116 A1 70F3116 70F3116 A and 70F3116 A1 Part No Item µPD703116...

Page 35: ... PDL6 AD7 PDL7 AD8 PDL8 AD9 PDL9 AD10 PDL10 AD11 PDL11 AD12 PDL12 AD13 PDL13 AD14 PDL14 AD15 PDL15 ANI06 ANI05 ANI04 ANI03 ANI02 ANI01 ANI00 AV REF0 AV SS AV DD TO015 TO014 TO013 TO012 TO011 TO010 V DD3 V SS3 V SS5 V DD5 TO005 TO004 TO003 TO002 TO001 TO000 INTP6 P07 INTP5 P06 INTP4 P05 ADTRG1 INTP3 P04 ADTRG0 INTP2 P03 ESO1 INTP1 P02 ESO0 INTP0 P01 NMI P00 TCLR11 INTP111 P15 TCUD11 INTP110 P14 1 2...

Page 36: ...controller area network Clock generator power supply Clock generator ground Emergency shut off Hold acknowledge Hold request Internally connected Interrupt request from peripherals Lower write strobe Mode Non maskable interrupt request Port 0 Port 1 P20 to P27 P30 to P37 P40 to P47 PCM0 to PCM4 PCS0 to PCS7 PCT0 to PCT7 PDH0 to PDH7 PDL0 to PDL15 RD RESET RXD0 to RXD2 SCK0 SCK1 SI0 SI1 SO0 SO1 SYN...

Page 37: ...el shifter Multiplier 32 32 64 CPU ROM RAM BCU ALU MEMC HLDRQ HLDAK CS0 to CS7 CKSEL CLKOUT X1 X2 CVDD CVSS PDL0 to PDL15 PDH0 to PDH7 PCS0 to PCS7 PCT0 to PCT7 PCM0 to PCM4 P40 to P47 P30 to P37 P20 to P27 P10 to P15 P00 to P07 ADTRG0 ANI00 to ANI07 AV SS AV REF0 AV DD ADTRG1 ANI10 to ANI17 AV SS AV REF1 AV DD MODE0 to MODE2 RESET VDD5 VSS5 VDD3 VSS3 VPPNote 4 UWR LWR WAIT A16 to A23 AD0 to AD15 ...

Page 38: ...le step transfer and block transfer 5 ROM There is on chip flash memory 256 KB in the µPD70F3116 and mask ROM 256 KB in the µPD703116 On an instruction fetch the ROM can be accessed by the CPU in one clock When single chip mode 0 or flash memory programming mode is set ROM is mapped starting from address 00000000H When single chip mode 1 is set it is mapped starting from address 00100000H ROM cann...

Page 39: ... NBD on chip as a debugging interface µPD70F3116 only 12 A D converter ADC Two units of a high speed high resolution 10 bit A D converter having eight analog input pins are implemented The ADC converts using a successive approximation method 13 Ports As shown in the table below ports function as general purpose ports and as control pins Port I O Control Functions Port 0 8 bit input NMI input Real ...

Page 40: ...o AD3_DBG SYNC CLK_DBG Flash memory programming pin Not provided IC5 Provided VPP Flash memory programming mode Not provided Provided MODE0 H L MODE1 H MODE2 L VPP 7 8 V Quality grade Standard grade Special grade Standard grade Special grade Electrical specifications The maximum operating frequency operating ambient temperature and current consumption differ refer to the data sheet of each product...

Page 41: ...Port 0 8 bit input only port INTP6 P10 TIUD10 TO10 P11 TCUD10 INTP100 P12 TCLR10 INTP101 P13 TIUD11 TO11 P14 TCUD11 INTP110 P15 I O Port 1 6 bit I O port Input or output can be specified in 1 bit units TCLR11 INTP111 P20 TI2 INTP20 P21 TO21 INTP21 P22 TO22 INTP22 P23 TO23 INTP23 P24 TO24 INTP24 P25 TCLR2 INTP25 P26 TI3 TCLR3 INTP30 P27 I O Port 2 8 bit I O port Input or output can be specified in ...

Page 42: ... Port CM 5 bit I O port Input or output can be specified in 1 bit units PCT0 LWR PCT1 UWR PCT2 PCT3 PCT4 RD PCT5 PCT6 ASTB PCT7 I O Port CT 8 bit I O port Input or output can be specified in 1 bit units PCS0 CS0 PCS1 CS1 PCS2 CS2 PCS3 CS3 PCS4 CS4 PCS5 CS5 PCS6 CS6 PCS7 I O Port CS 8 bit I O port Input or output can be specified in 1 bit units CS7 PDH0 A16 PDH1 A17 PDH2 A18 PDH3 A19 PDH4 A20 PDH5 ...

Page 43: ...me I O Function Alternate Function PDL0 AD0 PDL1 AD1 PDL2 AD2 PDL3 AD3 PDL4 AD4 PDL5 AD5 PDL6 AD6 PDL7 AD7 PDL8 AD8 PDL9 AD9 PDL10 AD10 PDL11 AD11 PDL12 AD12 PDL13 AD13 PDL14 AD14 PDL15 I O Port DL 16 bit I O port Input or output can be specified in 1 bit units AD15 ...

Page 44: ...31 ESO0 P01 INTP0 ESO1 I Timer 00 or 01 output stop signal input P02 INTP1 TIUD10 P10 TO10 TIUD11 I External count clock input to up down counter timer 10 or 11 P13 TO11 TCUD10 P11 INTP100 TCUD11 I Count operation switching signal to up down counter timer 10 or 11 P14 INTP110 TCLR10 P12 INTP101 TCLR11 I Clear signal input to up down counter timer 10 or 11 P15 INTP111 TI2 P20 INTP20 TI3 I Timer 2 o...

Page 45: ...41 SO1 O Serial transmit data output 3 wire of CSI0 and CSI1 P44 SI0 P40 SI1 I Serial receive data input 3 wire of CSI0 and CSI1 P43 SCK0 P42 SCK1 I O Serial clock I O 3 wire of CSI0 and CSI1 P45 TXD0 P31 TXD1 P33 TXD2 O Serial transmit data output of UART0 to UART2 P36 RXD0 P30 RXD1 P32 RXD2 I Serial receive data input of UART0 to UART2 P35 ASCK1 P34 ASCK2 I O Serial clock I O of UART1 and UART2 ...

Page 46: ...em clock generation Input to X1 pin when providing clocks from outside CLKOUT O System clock output PCM1 CKSEL I Input specifying clock generator operation mode AVREF0 I Reference voltage input for A D converter 0 AVREF1 I Reference voltage input for A D converter 1 AVDD Positive power supply for A D converter AVSS Ground potential for A D converter CVDD Positive power supply for dedicated clock g...

Page 47: ...i Z Hi Z Hi Z Operating Hi Z AD0 to AD15 PDL0 to PDL15 Hi Z Hi Z Hi Z Operating Hi Z CS0 to CS7 PCS0 to PCS7 Hi Z Hi Z H Operating Hi Z LWR UWR PCT0 PCT1 Hi Z Hi Z H Operating Hi Z RD PCT4 Hi Z Hi Z H Operating Hi Z ASTB PCT6 Hi Z Hi Z H Operating Hi Z WAIT PCM0 Hi Z Hi Z Operating CLKOUT PCM1 Hi Z Operating L Operating Operating HLDAK PCM2 Hi Z Hi Z H Operating L HLDRQ PCM3 Hi Z Hi Z Operating Op...

Page 48: ...ore the input port cannot be switched with the NMI input pin RPU output stop signal input pin external interrupt request input pin and A D converter ADC external trigger input pin Read the status of each pin by reading the port a Port mode P00 to P07 are input only b Control mode P00 to P07 also serve as NMI ESO0 ESO1 ADTRG0 ADTRG1 and INTP0 to INTP6 pins but they cannot be switched i NMI Non mask...

Page 49: ... PMC1 i TO10 TO11 Timer output Output These pins output timer 10 and timer 11 pulse signals ii TIUD10 TIUD11 Timer count pulse input Input These are external count clock input pins to the up down counter timer 10 timer 11 iii TCUD10 TCUD11 Timer control pulse input Input These pins input count operation switching signals to the up down counter timer 10 timer 11 iv TCLR10 TCLR11 Timer clear Input T...

Page 50: ...rol mode P20 to P27 can be set to port or control mode in 1 bit units using PMC2 i TO21 to TO24 Timer output Output These pins output a timer 2 pulse signal ii TO3 Timer output Output This pin outputs a timer 3 pulse signal iii TI2 TI3 Timer input Input These are timer 2 and timer 3 external count clock input pins iv TCLR2 TCLR3 Timer clear Input These are timer 2 and timer 3 clear signal input pi...

Page 51: ...h bit and specified by the port 3 mode control register PMC3 a Port mode P30 to P37 can be set to input or output in 1 bit units using the port 3 mode register PM3 b Control mode P30 to P37 can be set to port or control mode in 1 bit units using PMC3 i TXD0 to TXD2 Transmit data Output These pins output serial transmit data of UART0 to UART2 ii RXD0 to RXD2 Receive data Input These pins input seri...

Page 52: ...to P47 can be set to input or output in 1 bit units using the port 4 mode register PM4 b Control mode P40 to P47 can be set to port or control mode in 1 bit units using PMC4 i SO0 SO1 Serial output Output These pins output CSI0 and CSI1 serial transmit data ii SI0 SI1 Serial input Input These pins input CSI0 and CSI1 serial receive data iii SCK0 SCK1 Serial clock I O These are CSI0 and CSI1 serial...

Page 53: ...m clock output pin In single chip mode 1 and ROMless mode 0 or 1 output is not performed by the CLKOUT pin because it is in port mode during the reset period To perform CLKOUT output set this pin to control mode using the port CM mode control register PMCCM iii HLDAK Hold acknowledge Output This is an acknowledge signal output pin that shows that the V850E IA1 received a bus hold request and that ...

Page 54: ... the bus cycle is a lower memory write it becomes active at the falling edge of a T1 state CLKOUT signal and becomes inactive at the falling edge of a T2 state CLKOUT signal ii UWR Upper byte write strobe Output This is a strobe signal that shows that the executing bus cycle is a write cycle for SRAM external ROM or an external peripheral I O area In the data bus the upper byte is in effect If the...

Page 55: ...al peripheral I O The signal CSn is assigned to memory block n n 0 to 7 This is active for the period during which a bus cycle that accesses the corresponding memory block is activated It is inactive in an idle state TI 9 PDH0 to PDH7 Port DH I O Port DH is an 8 bit I O port in which input or output can be set in 1 bit units Besides functioning as a port in control mode external expansion mode the...

Page 56: ...PDL0 to PDL15 can be used as AD0 to AD15 by using PMCDL i AD0 to AD15 Address data bus I O This is a multiplexed bus for an address or data on an external access When used for an address T1 state they are 24 bit address output pins A0 to A15 and when used for data T2 TW T3 they are 16 bit data I O bus pins 11 TO000 to TO005 Timer output Output These pins output the pulse signal of timer 00 12 TO01...

Page 57: ...ration Mode 0 V L L L ROMless mode 0 0 V L L H ROMless mode 1 0 V L H L Single chip mode 0 0 V L H H Normal operation mode Single chip mode 1 7 8 V L H Flash memory programming mode Other than above Setting prohibited Remark L Low level input H High level input don t care 16 RESET Reset Input RESET input is asynchronous input When a signal having a certain low level width is input in asynchronous ...

Page 58: ... 3 3 V interface 25 SYNC Debug synchronization Input This is the command synchronization input pin for debugging 3 3 V interface 26 AD0_DBG to AD3_DBG Debug address data bus I O These are command interface pins for debugging 3 3 V interface 27 TRIG_DBG Debug trigger Output This is the address match trigger signal output pin for debugging 3 3 V interface 28 AVDD Analog power supply This is the anal...

Page 59: ...to P07 INTP6 2 Connect directly to VSS5 P10 TIUD10 TO10 P11 TCUD10 INTP100 P12 TCLR10 INTP101 P13 TIUD11 TO11 P14 TCUD11 INTP110 P15 TCLR11 INTP111 P20 TI2 INTP20 P21 TO21 INTP21 to P24 TO24 INTP24 P25 TCLR2 INTP25 P26 TI3 TCLR3 INTP30 P27 TO3 INTP31 P30 RXD0 5 AC P31 TXD0 5 P32 RXD1 5 AC P33 TXD1 5 P34 ASCK1 P35 RXD2 5 AC P36 TXD2 5 P37 ASCK2 P40 SI0 5 AC P41 SO0 5 P42 SCK0 P43 SI1 5 AC P44 SO1 5...

Page 60: ...to AD3_DBGNote 1 5 AC Independently connect to CVDD or CVSS via a resistor TRIG_DBGNote 1 3 Leave open low level output CLK_DBGNote 1 Independently connect to CVSS via a resistor SYNCNote 1 2 Independently connect to CVDD via a resistor IC1 to IC4Note 2 Leave open ANI00 to ANI07 ANI10 to ANI17 7 Connect to AVSS TO000 to TO005 TO010 to TO015 4 Leave open MODE0 to MODE2 VPP Note 1 Connect to VSS5 IC...

Page 61: ...ristics IN Type 3 P ch OUT VDD N ch Type 4 Push pull output with possible high impedance output P ch N ch both off Data Output disable P ch OUT VDD N ch Type 5 Data Output disable P ch IN OUT VDD N ch Input enable Type 5 AC Type 7 IN Comparator _ VREF threshold voltage P ch N ch P ch N ch VDD IN OUT Data Output disable Input enable ...

Page 62: ...tion execution time 20 ns internal 50 MHz operation Memory space Program space 64 MB linear Data space 4 GB linear Thirty two 32 bit general purpose registers Internal 32 bit architecture Five stage pipeline control Multiplication division instructions Saturated operation instructions One clock 32 bit shift instruction Long short format load store instructions Four types of bit manipulation instru...

Page 63: ...r26 r27 r28 r29 r30 r31 Zero register Assembler reserved register Stack pointer SP Global pointer GP Text pointer TP Element pointer EP Link pointer LP PC Program counter PSW Program status word ECR Interrupt source register FEPC FEPSW Status saving register during NMI Status saving register during NMI EIPC EIPSW Status saving register during interrupt Status saving register during interrupt 31 0 ...

Page 64: ...sters Name Usage Operation r0 Zero register Always holds 0 r1 Assembler reserved register Working register for generating address r2 Address data variable register when not being used by the real time OS r3 Stack pointer Used to generate stack frame when function is called r4 Global pointer Used to access global variable in data area r5 Text pointer Register to indicate the start of the text area ...

Page 65: ...egister during CALLT execution CTPSW 18 Status saving register during exception debug trap DBPC Note 2 19 Status saving register during exception debug trap DBPSW Note 2 20 CALLT base pointer CTBP 21 to 31 Reserved number for future function expansion operations that access these register numbers cannot be guaranteed Notes 1 Because this register has only one set to allow multiple interrupts it is...

Page 66: ...urated To clear 0 this bit load the data in PSW Note that in a general arithmetic operation this bit is neither set 1 nor cleared 0 0 Not saturated 1 Saturated 3 CY This flag is set if carry or borrow occurs as result of an operation if carry or borrow does not occur it is reset 0 Carry or borrow does not occur 1 Carry or borrow occurs 2 OVNote This flag is set if an overflow occurs during operati...

Page 67: ...nal device s memory reset entry address and instruction processing starts The internal ROM area is mapped from address 100000H b ROMless modes 0 1 After the system reset is cleared each pin related to the bus interface enters the control mode program execution branches to the external device s memory reset entry address and instruction processing starts Fetching of instructions and data access for...

Page 68: ... bus L H L Single chip mode 0 Internal ROM area is allocated from address 000000H L H H Normal operation mode Single chip mode 1 Internal ROM area is allocated from address 100000H Other than above Setting prohibited b µ µ µ µPD70F3116 VPP MODE2 MODE1 MODE0 Operation Mode Remark 0 V L L L ROMless mode 0 16 bit data bus 0 V L L H ROMless mode 1 8 bit data bus 0 V L H L Single chip mode 0 Internal R...

Page 69: ... to 4 GB of linear address space data space during operand addressing data access Also in instruction address addressing a maximum of 64 MB of linear address space program space is supported Figure 3 1 shows the CPU address space Figure 3 1 CPU Address Space FFFFFFFFH 04000000H 03FFFFFFH 00000000H Data area 4 GB linear Program area 64 MB linear CPU address space ...

Page 70: ...ows the image of the virtual addressing space Physical address x0000000H can be seen as CPU address 00000000H and in addition can be seen as address 10000000H address 20000000H address E0000000H or address F0000000H Figure 3 2 Image on Address Space FFFFFFFFH F0000000H EFFFFFFFH 00000000H Internal ROM Image Image Image Internal RAM On chip peripheral I O External memory Physical address space FFFF...

Page 71: ...ecome contiguous Caution The 4 KB area of 03FFF000H to 03FFFFFFH can be seen as an image of 0FFFF000H to 0FFFFFFFH No instruction can be fetched from this area because this area is defined as on chip peripheral I O area Therefore do not execute any branch address calculation in which the result will reside in any part of this area 03FFFFFEH 03FFFFFFH 00000000H 00000001H Program space Program space...

Page 72: ...ea On chip peripheral I O area Internal RAM area Access prohibitedNote External memory area Internal ROM area External memory area Internal ROM area External memory area Single chip mode 0 Single chip mode 1 ROMless mode 0 1 256 MB 1 MB 1 MB 4 KB xFFFF000H xFFFEFFFH xFFFE800H xFFFE7FFH x0200000H x01FFFFFH x0100000H x00FFFFFH x0000000H xFFFC000H xFFFBFFFH 10 KB Note By setting the PMCDH PMCDL PMCCS...

Page 73: ...ash memory area Single chip mode 0 Single chip mode 1 0FFFFFH 040000H 000000H 03FFFFH 1FFFFFH 140000H 100000H 13FFFFH b Interrupt exception table The V850E IA1 increases the interrupt response speed by assigning handler addresses corresponding to interrupts exceptions The collection of these handler addresses is called an interrupt exception table which is located in the internal ROM area When an ...

Page 74: ...31 000000B0H INTP3 00000280H INTCM4 000000C0H INTP4 00000290H INTDMA0 000000D0H INTP5 000002A0H INTDMA1 000000E0H INTP6 000002B0H INTDMA2 000000F0H INTDET0 000002C0H INTDMA3 00000100H INTDET1 000002D0H INTCREC 00000110H INTTM00 000002E0H INTCTRX 00000120H INTCM003 000002F0H INTCERR 00000130H INTTM01 00000300H INTCMAC 00000140H INTCM013 00000310H INTCSI0 00000150H INTP100 INTCC100 00000320H INTCSI1...

Page 75: ...l ROM Area in Single Chip Mode 1 Internal ROM area External memory area 200000H 1FFFFFH 100000H 0FFFFFH 000000H Block 0 Note Note See 4 3 Memory Block Function 2 Internal RAM area 12 KB of memory addresses FFFC000H to FFFEFFFH is reserved for the internal RAM area The 12 KB area of 3FFC000H to 3FFEFFFH can be seen as an image of FFFC000H to FFFEFFFH In the V850E IA1 10 KB of memory addresses FFFC0...

Page 76: ...of the hardware specification 2 In the V850E IA1 no registers exist that are capable of word access but if a register is word accessed halfword access is performed twice in the order of lower address then higher address of the word area ignoring the lower 2 bits of the address 3 For registers in which byte access is possible if halfword access is executed the higher 8 bits become undefined during ...

Page 77: ...en in single chip mode 1 x0000000H to x00FFFFFH x0200000H to xFFFBFFFH When in ROMless modes 0 and 1 x0000000H to xFFFBFFFH Access to the external memory area uses the chip select signal assigned to each memory block which is carried out in the CS unit set by chip area selection control registers 0 and 1 CSC0 CSC1 Note that the internal ROM internal RAM on chip peripheral I O and programmable peri...

Page 78: ...hanges to the port n mode control register PMCn the external data bus width is 16 bits b In the case of ROMless mode 1 Because each pin of ports DH DL CS CT and CM enters control mode following a reset external memory can be used without making changes to the port n mode control register PMCn the external data bus width is 8 bits c In the case of single chip mode 0 Since the internal ROM area is a...

Page 79: ...rom address 00000000H unconditionally corresponds to the memory map of the program space 2 Data space For the efficient use of resources that make use of the wrap around feature of the data space the continuous 16 MB address spaces 00000000H to 00FFFFFFH and FF000000H to FFFFFFFFH of the 4 GB CPU are used as the data space With the V850E IA1 a 256 MB physical address space is seen as 16 images in ...

Page 80: ... x00FFFFFH x0040000H x003FFFFH x0000000H xFFFFA78H xFFFFA77H Data space Program space On chip peripheral I O On chip peripheral I O Internal RAM Internal RAM External memory Internal ROM External memory External memory Internal RAM On chip peripheral I ONote Program space 64 MB Internal ROM Internal ROM Note Access to this area is prohibited To access the on chip peripheral I O specify addresses F...

Page 81: ...FFF046H Port DH mode control register PMCDH R W 00H FFH FFFFF048H Port CS mode control register PMCCS R W 00H FFH FFFFF04AH Port CT mode control register PMCCT R W 00H 53H FFFFF04CH Port CM mode control register PMCCM R W 00H 0FH FFFFF060H Chip area selection control register 0 CSC0 R W 2C11H FFFFF062H Chip area selection control register 1 CSC1 R W 2C11H FFFFF064H Peripheral area selection contro...

Page 82: ...ister 3 DADC3 R W 0000H FFFFF0E0H DMA channel control register 0 DCHC0 R W 00H FFFFF0E2H DMA channel control register 1 DCHC1 R W 00H FFFFF0E4H DMA channel control register 2 DCHC2 R W 00H FFFFF0E6H DMA channel control register 3 DCHC3 R W 00H FFFFF0F0H DMA disable status register DDIS R 00H FFFFF0F2H DMA restart register DRST R W 00H FFFFF100H Interrupt mask register 0 IMR0 R W FFFFH FFFFF100H In...

Page 83: ...47H FFFFF138H Interrupt control register CM11IC1 R W 47H FFFFF13AH Interrupt control register TM2IC0 R W 47H FFFFF13CH Interrupt control register TM2IC1 R W 47H FFFFF13EH Interrupt control register CC2IC0 R W 47H FFFFF140H Interrupt control register CC2IC1 R W 47H FFFFF142H Interrupt control register CC2IC2 R W 47H FFFFF144H Interrupt control register CC2IC3 R W 47H FFFFF146H Interrupt control reg...

Page 84: ...ADSCM00H R W 00H FFFFF202H A D scan mode register 01 ADSCM01 R W 0000H FFFFF202H A D scan mode register 01L ADSCM01L R 00H FFFFF203H A D scan mode register 01H ADSCM01H R W 00H FFFFF204H A D voltage detection mode register 0 ADETM0 R W 0000H FFFFF204H A D voltage detection mode register 0L ADETM0L R W 00H FFFFF205H A D voltage detection mode register 0H ADETM0H R W 00H FFFFF210H A D conversion res...

Page 85: ...rt 1 P1 R W Undefined FFFFF404H Port 2 P2 R W Undefined FFFFF406H Port 3 P3 R W Undefined FFFFF408H Port 4 P4 R W Undefined FFFFF422H Port 1 mode register PM1 R W FFH FFFFF424H Port 2 mode register PM2 R W FFH FFFFF426H Port 3 mode register PM3 R W FFH FFFFF428H Port 4 mode register PM4 R W FFH FFFFF442H Port 1 mode control register PMC1 R W 00H FFFFF444H Port 2 mode control register PMC2 R W 00H ...

Page 86: ...5B6H Buffer register CM12 BFCM12 R W FFFFH FFFFF5B8H Buffer register CM13 BFCM13 R W FFFFH FFFFF5BAH Timer control register 01 TMC01 R W 0508H FFFFF5BAH Timer control register 01L TMC01L R W 08H FFFFF5BBH Timer control register 01H TMC01H R W 05H FFFFF5BCH Timer unit control register 01 TUC01 R W 01H FFFFF5BDH Timer output mode register 1 TOMR1 R W 00H FFFFF5BEH PWM software timing output register...

Page 87: ...FFFF618H Timer 11 noise elimination time selection register NRC11 R W 00H FFFFF620H Timer connection selection register 0 TMIC0 R W 00H FFFFF630H Timer 2 input filter mode register 0 FEM0 R W 00H FFFFF631H Timer 2 input filter mode register 1 FEM1 R W 00H FFFFF632H Timer 2 input filter mode register 2 FEM2 R W 00H FFFFF633H Timer 2 input filter mode register 3 FEM3 R W 00H FFFFF634H Timer 2 input ...

Page 88: ...annel 1 main capture compare register CVPE10 R 0000H FFFFF654H Timer 2 sub channel 2 sub capture compare register CVSE20 R W 0000H FFFFF656H Timer 2 sub channel 2 main capture compare register CVPE20 R 0000H FFFFF658H Timer 2 sub channel 3 sub capture compare register CVSE30 R W 0000H FFFFF65AH Timer 2 sub channel 3 main capture compare register CVPE30 R 0000H FFFFF65CH Timer 2 sub channel 4 sub c...

Page 89: ...0H FFFFF812H DMA trigger factor register 1 DTFR1 R W 00H FFFFF814H DMA trigger factor register 2 DTFR2 R W 00H FFFFF816H DMA trigger factor register 3 DTFR3 R W 00H FFFFF820H Power save mode register PSMR R W 00H FFFFF822H Clock control register CKC R W 00H FFFFF824H Lock register LOCKR R 0000000xB FFFFF880H External interrupt mode register 0 INTM0 R W 00H FFFFF882H External interrupt mode registe...

Page 90: ...1 R 0000H FFFFF916H Clocked serial interface read only reception buffer register L1 SIRBEL1 R 00H FFFFF918H Clocked serial interface initial transmission buffer register 1 SOTBF1 R W 0000H FFFFF918H Clocked serial interface initial transmission buffer register L1 SOTBFL1 R W 00H FFFFF91AH Serial I O shift register 1 SIO1 R 0000H FFFFF91AH Serial I O shift register L1 SIOL1 R 00H FFFFF920H Prescale...

Page 91: ...gister L2 TXSL2 W Undefined FFFFFA48H Asynchronous serial interface mode register 20 ASIM20 R W 81H FFFFFA4AH Asynchronous serial interface mode register 21 ASIM21 R W 00H FFFFFA4CH Asynchronous serial interface status register 2 ASIS2 R 00H FFFFFA4EH Prescaler mode register 2 PRSM2 R W 00H FFFFFA50H Prescaler compare register 2 PRSCM2 R W 00H FFFFFA60H RAM access data buffer register L NBDL R W 0...

Page 92: ... this area the written contents are reflected on the on chip peripheral I O area Therefore access to this area is prohibited To access the on chip peripheral I O area be sure to specify addresses FFFF000H to FFFFFFFH Figure 3 7 Programmable Peripheral I O Register Outline 3FFFFFFH 3FFF000H 3FFEFFFH xxxxNFFFH xxxxM000H x3FFFH x3000H x2FFFH x2000H x0000H x1FFFH 0000000H On chip peripheral I O regist...

Page 93: ...04 PA03 PA02 PA01 PA00 FFFFF064H 0000H Bit Position Bit Name Function Enables disables usage of programmable peripheral I O area PA15 Usage of Programmable Peripheral I O Area 0 Disables usage of programmable peripheral I O area 1 Enables usage of programmable peripheral I O area 15 PA15 13 to 0 PA13 to PA00 Specifies an address in programmable peripheral I O area corresponds to A27 to A14 respect...

Page 94: ...set clear register 00 SC_STAT00 W 0000H xxxxn824H CAN message data length register 01 M_DLC01 R W Undefined xxxxn825H CAN message control register 01 M_CTRL01 R W Undefined xxxxn826H CAN message time stamp register 01 M_TIME01 R W Undefined xxxxn828H CAN message data register 010 M_DATA010 R W Undefined xxxxn829H CAN message data register 011 M_DATA011 R W Undefined xxxxn82AH CAN message data regi...

Page 95: ...ge data register 030 M_DATA030 R W Undefined xxxxn869H CAN message data register 031 M_DATA031 R W Undefined xxxxn86AH CAN message data register 032 M_DATA032 R W Undefined xxxxn86BH CAN message data register 033 M_DATA033 R W Undefined xxxxn86CH CAN message data register 034 M_DATA034 R W Undefined xxxxn86DH CAN message data register 035 M_DATA035 R W Undefined xxxxn86EH CAN message data register...

Page 96: ...sage data register 054 M_DATA054 R W Undefined xxxxn8ADH CAN message data register 055 M_DATA055 R W Undefined xxxxn8AEH CAN message data register 056 M_DATA056 R W Undefined xxxxn8AFH CAN message data register 057 M_DATA057 R W Undefined xxxxn8B0H CAN message ID register L05 M_IDL05 R W Undefined xxxxn8B2H CAN message ID register H05 M_IDH05 R W Undefined xxxxn8B4H CAN message configuration regis...

Page 97: ...message ID register L07 M_IDL07 R W Undefined xxxxn8F2H CAN message ID register H07 M_IDH07 R W Undefined xxxxn8F4H CAN message configuration register 07 M_CONF07 R W Undefined xxxxn8F5H CAN message status register 07 M_STAT07 R Undefined xxxxn8F6H CAN status set clear register 07 SC_STAT07 W 0000H xxxxn904H CAN message data length register 08 M_DLC08 R W Undefined xxxxn905H CAN message control re...

Page 98: ...set clear register 09 SC_STAT09 W 0000H xxxxn944H CAN message data length register 10 M_DLC10 R W Undefined xxxxn945H CAN message control register 10 M_CTRL10 R W Undefined xxxxn946H CAN message time stamp register 10 M_TIME10 R W Undefined xxxxn948H CAN message data register 100 M_DATA100 R W Undefined xxxxn949H CAN message data register 101 M_DATA101 R W Undefined xxxxn94AH CAN message data regi...

Page 99: ...ge data register 120 M_DATA120 R W Undefined xxxxn989H CAN message data register 121 M_DATA121 R W Undefined xxxxn98AH CAN message data register 122 M_DATA122 R W Undefined xxxxn98BH CAN message data register 123 M_DATA123 R W Undefined xxxxn98CH CAN message data register 124 M_DATA124 R W Undefined xxxxn98DH CAN message data register 125 M_DATA125 R W Undefined xxxxn98EH CAN message data register...

Page 100: ...sage data register 144 M_DATA144 R W Undefined xxxxn9CDH CAN message data register 145 M_DATA145 R W Undefined xxxxn9CEH CAN message data register 146 M_DATA146 R W Undefined xxxxn9CFH CAN message data register 147 M_DATA147 R W Undefined xxxxn9D0H CAN message ID register L14 M_IDL14 R W Undefined xxxxn9D2H CAN message ID register H14 M_IDH14 R W Undefined xxxxn9D4H CAN message configuration regis...

Page 101: ...message ID register L16 M_IDL16 R W Undefined xxxxnA12H CAN message ID register H16 M_IDH16 R W Undefined xxxxnA14H CAN message configuration register 16 M_CONF16 R W Undefined xxxxnA15H CAN message status register 16 M_STAT16 R Undefined xxxxnA16H CAN status set clear register 16 SC_STAT16 W 0000H xxxxnA24H CAN message data length register 17 M_DLC17 R W Undefined xxxxnA25H CAN message control re...

Page 102: ... set clear register 18 SC_STAT18 W 0000H xxxxnA64H CAN message data length register 19 M_DLC19 R W Undefined xxxxnA65H CAN message control register 19 M_CTRL19 R W Undefined xxxxnA66H CAN message time stamp register 19 M_TIME19 R W Undefined xxxxnA68H CAN message data register 190 M_DATA190 R W Undefined xxxxnA69H CAN message data register 191 M_DATA191 R W Undefined xxxxnA6AH CAN message data reg...

Page 103: ...age data register 210 M_DATA210 R W Undefined xxxxnAA9H CAN message data register 211 M_DATA211 R W Undefined xxxxnAAAH CAN message data register 212 M_DATA212 R W Undefined xxxxnAABH CAN message data register 213 M_DATA213 R W Undefined xxxxnAACH CAN message data register 214 M_DATA214 R W Undefined xxxxnAADH CAN message data register 215 M_DATA215 R W Undefined xxxxnAAEH CAN message data registe...

Page 104: ...ssage data register 234 M_DATA234 R W Undefined xxxxnAEDH CAN message data register 235 M_DATA235 R W Undefined xxxxnAEEH CAN message data register 236 M_DATA236 R W Undefined xxxxnAEFH CAN message data register 237 M_DATA237 R W Undefined xxxxnAF0H CAN message ID register L23 M_IDL23 R W Undefined xxxxnAF2H CAN message ID register H23 M_IDH23 R W Undefined xxxxnAF4H CAN message configuration regi...

Page 105: ... message ID register L25 M_IDL25 R W Undefined xxxxnB32H CAN message ID register H25 M_IDH25 R W Undefined xxxxnB34H CAN message configuration register 25 M_CONF25 R W Undefined xxxxnB35H CAN message status register 25 M_STAT25 R Undefined xxxxnB36H CAN status set clear register 25 SC_STAT25 W 0000H xxxxnB44H CAN message data length register 26 M_DLC26 R W Undefined xxxxnB45H CAN message control r...

Page 106: ... set clear register 27 SC_STAT27 W 0000H xxxxnB84H CAN message data length register 28 M_DLC28 R W Undefined xxxxnB85H CAN message control register 28 M_CTRL28 R W Undefined xxxxnB86H CAN message time stamp register 28 M_TIME28 R W Undefined xxxxnB88H CAN message data register 280 M_DATA280 R W Undefined xxxxnB89H CAN message data register 281 M_DATA281 R W Undefined xxxxnB8AH CAN message data reg...

Page 107: ...age data register 300 M_DATA300 R W Undefined xxxxnBC9H CAN message data register 301 M_DATA301 R W Undefined xxxxnBCAH CAN message data register 302 M_DATA302 R W Undefined xxxxnBCBH CAN message data register 303 M_DATA303 R W Undefined xxxxnBCCH CAN message data register 304 M_DATA304 R W Undefined xxxxnBCDH CAN message data register 305 M_DATA305 R W Undefined xxxxnBCEH CAN message data registe...

Page 108: ...ain clock selection register CGCS R W 7F05H xxxxnC18H CAN time stamp count register CGTSC R 0000H CAN message search start register CGMSS W 0000H xxxxnC1AH CAN message search result register CGMSR R 0000H xxxxnC40H CAN1 address mask 0 register L C1MASKL0 R W Undefined xxxxnC42H CAN1 address mask 0 register H C1MASKH0 R W Undefined xxxxnC44H CAN1 address mask 1 register L C1MASKL1 R W Undefined xxx...

Page 109: ...n 8 bit units address FFFFF06EH initial value 77H Remark If the timing of changing the flag or count value conflicts with the timing of accessing a register when a register including a status flag that indicates the status of an on chip peripheral function such as ASIF0 or a register indicating the count value of a timer such as TM0n is accessed a register access retry operation is performed As a ...

Page 110: ...ress data bus AD0 to AD15 PDL0 to PDL15 Port DL PMCDL Address bus A16 to A23 PDH0 to PDH7 Port DH PMCDH Chip select CS0 to CS7 PCS0 to PCS7 Port CS PMCCS Read write control LWR UWR RD ASTB PCT0 PCT1 PCT4 PCT6 Port CT PMCCT External wait control WAIT PCM0 Port CM Internal system clock CLKOUT PCM1 Port CM Bus hold control HLDRQ HLDAK PCM2 PCM3 Port CM PMCCM Remark In the case of single chip mode 1 a...

Page 111: ...BFFFFFFH 8000000H 7FFFFFFH 4000000H 3FFFFFFH 0800000H 07FFFFFH 0600000H 05FFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H Block 1 2 MB Block 0 2 MB Block 2 2 MB Block 3 2 MB 64 MB 64 MB Block 5 2 MB Block 6 2 MB Block 4 2 MB Block 7 2 MB 3FFFFFFH On chip peripheral I O area 4 KB Note 2 Internal RAM area 12 KBNote 1 3FFC000H 3FFF000H 3FFEFFFH 00FFFFFH Internal ROM area 1 MB Note 3 0000000H CS7 ...

Page 112: ...w 1 Chip area selection control registers 0 1 CSC0 CSC1 These registers can be read written in 16 bit units and become valid by setting each bit to 1 If different chip select signal outputs are set to the same block the priority order is controlled as follows CSC0 On chip peripheral I O area CS0 CS2 CS1 CSC1 On chip peripheral I O area CS7 CS5 CS6 If both the CS0m and CS2m bits of the CSC0 registe...

Page 113: ...ess CS22 CS2 output during block 2 access CS23 CS2 output during block 3 access CS30 to CS33 Note 2 CS40 to CS43 Note 3 CS50 CS5 output during block 7 access CS51 CS5 output during block 6 access CS52 CS5 output during block 5 access CS53 CS5 output during block 4 access CS60 to CS63 Note 4 CS70 CS7 output during block 7 access CS71 CS7 output during block 6 access CS72 CS7 output during block 5 a...

Page 114: ...since CS0 has priority over CS2 CS0 is output if the addresses of block 0 and block 1 are accessed If the address of block 3 is accessed both the CS03 and CS23 bits of the CSC0 register are 0 and CS1 is output Figure 4 1 Example When CSC0 Register Is Set to 0703H 3FFFFFFH 0600000H 05FFFFFH 0800000H 07FFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H Block 2 2 MB Block 3 2 MB Block 1 2 MB Block 0...

Page 115: ...an external memory area other than the one for this initialization routine until the initial setting of the BCT0 and BCT1 registers is complete However it is possible to access external memory areas whose initial settings are complete 15 ME3 BCT0 CSn signal Address FFFFF480H Initial value CCCCH 14 1 1 0 0 13 12 11 ME2 10 9 0 0 0 0 8 7 ME1 6 1 5 4 3 ME0 2 1 1 0 0 0 CS3 CS2 CS1 CS0 15 ME7 BCT1 CSn s...

Page 116: ... Status Resource Bus Width Instruction Fetch Operand Data Access Internal ROM 32 bits 1Note 1 5 Internal RAM 32 bits 1Note 2 1 On chip peripheral I O 16 bits 5Note 3 Programmable peripheral I O 5Note 3 External memory 16 bits 3Note 3 3Note 3 Notes 1 This value is 2 in the case of instruction branch 2 This value is 2 if there is contention with data access 3 MIN value Remark Unit Clock access ...

Page 117: ...memory areas whose initial settings are complete 2 When the data bus width is specified as 8 bits only the signals shown below become active LWR When accessing SRAM external ROM or external I O write cycle 15 0 BSC CSn signal Address FFFFF066H Initial valueNote 0000H 5555H 14 BS70 13 0 12 BS60 11 0 10 BS50 9 0 8 BS40 7 0 6 BS30 5 0 4 BS20 3 0 2 BS10 1 0 0 BS00 CS3 CS2 CS1 CS0 CS4 CS5 CS6 CS7 Note ...

Page 118: ...arting from the lower side 1 Byte access 8 bits a When the data bus width is 16 bits little endian 1 Access to even address 2n 2 Access to odd address 2n 1 7 0 7 0 Byte data 15 8 External data bus 2n Address 7 0 7 0 Byte data 15 8 External data bus 2n 1 Address b When the data bus width is 8 bits little endian 1 Access to even address 2n 2 Access to odd address 2n 1 7 0 7 0 Byte data External data...

Page 119: ...fword data 15 8 15 8 External data bus 2n 1 Address 7 0 7 0 Halfword data 15 8 15 8 External data bus 2n 2 Address 2n b When the data bus width is 8 bits little endian 1 Access to even address 2n 2 Access to odd address 2n 1 1st access 2nd access 1st access 2nd access 7 0 7 0 Halfword data 15 8 External data bus Address 7 0 7 0 Halfword data 15 8 External data bus 2n 1 Address 2n 7 0 7 0 Halfword ...

Page 120: ...5 8 External data bus 4n Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 2 Address 15 8 4n 3 23 16 31 24 2 Access to address 4n 1 1st access 2nd access 3rd access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 2 Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 23 16...

Page 121: ...l data bus 4n 2 Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 4n 5 23 16 31 24 4 Access to address 4n 3 1st access 2nd access 3rd access 7 0 7 0 Word data 15 8 External data bus Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 4 Address 15 8 4n 5 23 16 31 24 7 0 7 0 Word data 15 8 External data bus 4n 6 Address 15 8 23 16 31 24 ...

Page 122: ... Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 Address 15 8 23 16 31 24 2 Access to address 4n 1 1st access 2nd access 3rd access 4th access 7 0 7 0 Word data External data bus Address 15 8 4n 1 23 16 31 24 7 0 7 0 Word data External data bus 4n 2 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 3 ...

Page 123: ... 3 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n 5 Address 15 8 23 16 31 24 4 Access to address 4n 3 1st access 2nd access 3rd access 4th access 7 0 7 0 Word data External data bus Address 15 8 4n 3 23 16 31 24 7 0 7 0 Word data External data bus 4n 4 Address 15 8 23 16 31 24 7 0 7 0 Word data External data bus 4n ...

Page 124: ...ripheral function only 2 Write to the DWC0 and DWC1 registers after reset and then do not change the set values Also do not access an external memory area other than the one for this initialization routine until the initial setting of the DWC0 and DWC1 registers is complete However it is possible to access external memory areas whose initial settings are complete 15 DWC0 CSn signal Address FFFFF48...

Page 125: ...s CS4 CS0 AWC CSn signal 15 AHW7 14 ASW7 13 AHW6 12 ASW6 11 AHW5 10 ASW5 9 AHW4 8 ASW4 7 AHW3 6 ASW3 5 AHW2 4 ASW2 3 AHW1 2 ASW1 1 AHW0 0 ASW0 Address FFFFF488H Initial value 0000H CS7 CS6 CS5 CS3 CS2 CS1 Bit Position Bit Name Function 15 13 11 9 7 5 3 1 AHWn n 0 to 7 Sets the insertion of an address hold wait state in each CSn space after the T1 cycle 0 Address hold wait state not inserted 1 Addr...

Page 126: ... time in the sampling timing is not satisfied the wait state may or may not be inserted in the next state 4 6 3 Relationship between programmable wait and external wait A wait cycle is inserted as the result of an OR operation between the wait cycle specified by the set value of the programmable wait and the wait cycle controlled by the WAIT pin In other words the number of wait cycles is determin...

Page 127: ...system reset 1 Bus cycle control register BCC This register can be read written in 16 bit units Cautions 1 Idle states cannot be inserted in internal ROM internal RAM on chip peripheral I O or programmable peripheral I O areas 2 Write to the BCC register after reset and then do not change the set values Also do not access an external memory area other than the one for this initialization routine u...

Page 128: ...nal operations of the V850E IA1 continue until the external memory or on chip peripheral I O register is accessed The bus hold state can be known by the HLDAK pin becoming active low level The period from when the HLDRQ pin becomes active low level to when the HLDAK pin becomes active low level is at least 2 clocks In a multiprocessor configuration etc a system with multiple bus masters can be con...

Page 129: ...LDRQ pin becomes active and the bus hold state is set When the HLDRQ pin becomes inactive after that the HLDAK pin also becomes inactive As a result the bus hold state is cleared and the HALT mode is set again 4 8 4 Bus hold timing T2 T3 TH TH TH TH TI T1 CLKOUT output HLDRQ input HLDAK output A16 to A23 output AD0 to AD15 I O ASTB output RD output LWR UWR output CSn output WAIT input Address Addr...

Page 130: ... cycle operand data access and instruction fetch in that order An instruction fetch may be inserted between a read access and write access during a read modify write access Also an instruction fetch may be inserted between bus accesses when a CPU bus clock is used Table 4 1 Bus Priority Order Priority Order External Bus Cycle Bus Master High Bus hold External device DMA cycle DMA controller Operan...

Page 131: ...tch is valid only in the external memory area In memory block 7 it is terminated when the internal address count value has reached the upper limit of the external memory area 4 10 2 Data space The V850E IA1 is provided with an address misalign function Through this function regardless of the data format word data or halfword data data can be allocated to all addresses However in the case of word d...

Page 132: ...imum of 2 states A maximum of 7 programmable data wait states can be inserted according to DWC0 and DWC1 register settings Data waits can be controlled by WAIT pin input An idle state 1 state can be inserted after a read write cycle by setting the BCC register An address hold wait state or address setup wait state can be inserted by setting the AWC register ...

Page 133: ... 5 1 SRAM External ROM External I O Access Timing 1 5 a On a read 1 wait insertion T1 T2 TW T3 Address Data H CLKOUT Output A16 to A23 Output AD0 to AD15 I O ASTB Output RD Output UWR LWR Output CSn Output WAIT Input Address Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance 3 n 0 to 7 ...

Page 134: ...ng 2 5 b On a read 0 wait address setup wait address hold wait state insertion TASW T1 TAHW Address Address T2 T3 Data H CLKOUT Output A16 to A23 Output AD0 to AD15 I O ASTB Output RD Output UWR LWR Output CSn Output WAIT Input Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance 3 n 0 to 7 ...

Page 135: ...aNote H CLKOUT Output A16 to A23 Output AD0 to AD15 I O ASTB Output RD Output UWR LWR Output CSn Output WAIT Input Address Note AD0 to AD7 output invalid data when accessed to odd numbered address byte data AD8 to AD15 output invalid data when accessed to even numbered address byte data Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance 3 n 0 to 7 ...

Page 136: ...r 8 bit data bus T1 T2 T3 Address Address Address H CLKOUT Output A16 to A23 Output AD8 to AD15 I O AD0 to AD7 I O ASTB Output RD Output UWR LWR Output CSn Output WAIT Input DataNote Note AD0 to AD7 output invalid data when accessed to odd numbered address byte data Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance 3 n 0 to 7 ...

Page 137: ...ned Note 2 Address Undefined T3 TH TH TH TH TI T1 CLKOUT Output A16 to A23 Output AD0 to AD15 I O HLDAK Output ASTB Output RD Output UWR LWR Output CSn Output HLDRQ Input WAIT Input Undefined Notes 1 On a read Undefined On a write Address 2 On a read Data On a write Undefined Remarks 1 The circles indicate the sampling timing 2 Broken lines indicate high impedance 3 n 0 to 7 ...

Page 138: ...pulse unit and A D converter or software triggers memory refers to internal RAM or external memory 6 1 Features 4 independent DMA channels Transfer units 8 16 bits Maximum transfer count 65 536 2 16 Transfer type Two cycle transfer Three transfer modes Single transfer mode Single step transfer mode Block transfer mode Transfer requests Request by interrupts from on chip peripheral I O such as seri...

Page 139: ...control Channel control DMAC V850E IA1 Bus interface External bus External RAM External ROM External I O DMA source address register DSAnH DSAnL DMA transfer count register DBCn DMA channel control register DCHCn DMA destination address register DDAnH DDAnL DMA addressing control register DADCn DMA disable status register DDIS DMA trigger factor register n DTFRn DMA restart register DRST Remark n ...

Page 140: ...source address registers 0H to 3H DSA0H to DSA3H These registers can be read written in 16 bit units Be sure to set bits 12 to 14 to 0 If they are set to 1 the operation is not guaranteed Caution When setting an address of an on chip peripheral I O register for the source address be sure to specify an address between FFFF000H and FFFFFFFH An address of the on chip peripheral I O register image 3FF...

Page 141: ...A7 6 SA6 5 SA5 4 SA4 3 SA3 2 SA2 1 SA1 0 SA0 SA15 DSA1L FFFFF088H Undefined SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SA15 DSA2L FFFFF090H Undefined SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SA15 DSA3L FFFFF098H Undefined SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Bit Position Bit Name Function 15 to 0 SA15 to SA0 Sets the DMA sou...

Page 142: ...ss registers 0H to 3H DDA0H to DDA3H These registers can be read written in 16 bit units Be sure to set bits 12 to 14 to 0 If they are set to 1 the operation is not guaranteed Caution When setting an address of an on chip peripheral I O register for the destination address be sure to specify an address between FFFF000H and FFFFFFFH An address of the on chip peripheral I O register image 3FFF000H t...

Page 143: ... 6 DA6 5 DA5 4 DA4 3 DA3 2 DA2 1 DA1 0 DA0 DA15 DDA1L FFFFF08CH Undefined DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA15 DDA2L FFFFF094H Undefined DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DA15 DDA3L FFFFF09CH Undefined DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Bit Position Bit Name Function 15 to 0 DA15 to DA0 Sets the DMA desti...

Page 144: ...transfer Transfer is terminated if a borrow occurs These registers can be read written in 16 bit units Remark If the DBCn register is read after a terminal count has occurred during DMA transfer without the value of the DBCn register being rewritten the value set immediately before DMA transfer is read 0000H is not read even after completion of transfer 15 BC15 DBC0 Address FFFFF0C0H Initial value...

Page 145: ...of the following periods the operation is not guaranteed if set at another timing Time from system reset to the start of the first DMA transfer Time from DMA transfer end after terminal count to the start of the next DMA transfer Time from the forcible termination of DMA transfer after the INITn bit of DMA channel control register n DCHCn has been set to 1 to the start of the next DMA transfer 1 2...

Page 146: ... 0 1 Decrement 1 0 Fixed 1 1 Setting prohibited 7 6 SAD1 SAD0 Sets the count direction of the destination address for DMA channel n n 0 to 3 DAD1 DAD0 Count Direction 0 0 Increment 0 1 Decrement 1 0 Fixed 1 1 Setting prohibited 5 4 DAD1 DAD0 Sets the transfer mode during DMA transfer TM1 TM0 Transfer Mode 0 0 Single transfer mode 0 1 Single step transfer mode 1 0 Setting prohibited 1 1 Block trans...

Page 147: ... guaranteed if set at another timing Time from system reset to the start of the first DMA transfer Time from DMA transfer end after terminal count to the start of the next DMA transfer Time from the forcible termination of DMA transfer after the INITn bit has been set to 1 to the start of the next DMA transfer 3 If DMA transfer is forcibly terminated in the last transfer cycle with the MLEn bit se...

Page 148: ... DMA transfer request can be accepted even when the TCn bit is not read When the next DMA transfer request is the setting of the STGn bit to 1 software DMA the DMA transfer request can be accepted by reading and clearing the TCn bit to 0 When this bit is cleared to 0 at terminal count output the Enn bit is cleared to 0 and the DMA transfer disable state is entered At the next DMA transfer request ...

Page 149: ...ext forcible interruption by NMI input or until the system is reset 6 3 7 DMA restart register DRST The ENn bit of the DRST register and the Enn bit of the DCHCn register are linked to each other n 0 to 3 This register can be read written in 8 bit units Be sure to set bits 4 to 7 to 0 If they are set to 1 the operation is not guaranteed Address FFFFF0F2H 7 0 DRST 6 0 5 0 4 0 3 EN3 2 EN2 1 EN1 0 EN...

Page 150: ...IFC12 IFC11 IFC10 FFFFF812H 00H 7 DTFR2 6 5 4 3 2 1 0 DF2 0 IFC25 IFC24 IFC23 IFC22 IFC21 IFC20 FFFFF814H 00H 7 DTFR3 6 5 4 3 2 1 0 DF3 0 IFC35 IFC34 IFC33 IFC32 IFC31 IFC30 FFFFF816H 00H Bit Position Bit Name Function 7 DFn This is a DMA transfer request flag Only 0 can be written to this flag 0 No DMA transfer request 1 DMA transfer request If an interrupt that causes DMA transfer occurs while D...

Page 151: ...TCC20 0 1 1 0 0 1 INTP21 INTCC21 0 1 1 0 1 0 INTP22 INTCC22 0 1 1 0 1 1 INTP23 INTCC23 0 1 1 1 0 0 INTP24 INTCC24 0 1 1 1 0 1 INTP25 INTCC25 0 1 1 1 1 0 INTTM3 0 1 1 1 1 1 INTP30 INTCC30 1 0 0 0 0 0 INTP31 INTCC31 1 0 0 0 0 1 INTCM4 1 0 0 0 1 0 INTDMA0 1 0 0 0 1 1 INTDMA1 1 0 0 1 0 0 INTDMA2 1 0 0 1 0 1 INTDMA3 1 0 0 1 1 0 INTCREC 1 0 0 1 1 1 INTCTRX 1 0 1 0 0 0 INTCERR 1 0 1 0 0 1 INTCMAC 1 0 1 0...

Page 152: ...rresponds to the last state of a read operation in the two cycle transfer mode or to a wait state In the last T2R state read data is sampled After entering the last T2R state the bus invariably enters the T1W state 6 T2RI state The T2RI state is a state in which the bus is ready for DMA transfer to on chip peripheral I O or internal RAM state in which the bus mastership is acquired for DMA transfe...

Page 153: ...s are initialized n 0 to 3 After entering the TE state the bus invariably enters the TI state 6 4 2 DMAC bus cycle state transition Except for the block transfer mode each time the processing for a DMA transfer is completed the bus mastership is released Figure 6 1 DMAC Bus Cycle Two Cycle Transfer State Transition TI T0 T1R T1RI T2R T1W T2W TE TI T2RI T1WI ...

Page 154: ...eleased for the CPU is a transfer based on the newly generated lower priority DMA transfer request Figures 6 2 to 6 5 show examples of single transfer Figure 6 2 Single Transfer Example 1 CPU DMA3 CPU CPU DMA3 CPU CPU CPU CPU CPU DMA3 CPU DMA3 DMA3 CPU CPU CPU DMARQ3 Internal signal CPU CPU DMA channel 3 terminal count Note Note Note Note Note The bus is always released Figure 6 3 shows a single t...

Page 155: ... Note Note Internal signal Internal signal Note The bus is always released Figure 6 5 shows a single transfer mode example in which two or more lower priority DMA transfer requests are generated within one clock after the end of a single transfer DMA channels 0 2 and 3 are used for a single transfer When three or more DMA transfer request signals are activated at the same time always the two highe...

Page 156: ...e used for the single step transfer Figure 6 6 Single Step Transfer Example 1 DMA1 CPU CPU CPU CPU CPU CPU CPU CPU DMA1 CPU CPU DMA1 DMA1 CPU DMARQ1 CPU CPU DMA channel 1 terminal count Note Note Note Internal signal Note The bus is always released Figure 6 7 Single Step Transfer Example 2 DMA0 DMA0 CPU CPU DMA1 CPU CPU CPU CPU DMA1 CPU CPU DMA1 DMA0 CPU DMARQ1 DMA1 CPU DMARQ0 DMA channel 0 termin...

Page 157: ...cles a read cycle source to DMAC and a write cycle DMAC to destination In the first cycle the source address is output and reading is performed from the source to the DMAC In the second cycle the destination address is output and writing is performed from the DMAC to the destination Caution An idle cycle of 1 clock is always inserted between the read cycle and write cycle ...

Page 158: ...er if the data bus width of the transfer source and that of the transfer destination are different the operation becomes as follows If the object of the DMA transfer is an on chip peripheral I O register transfer source transfer destination be sure to specify the same transfer size as the register size For example in the case of DMA transfer to an 8 bit register be sure to specify byte 8 bit trans...

Page 159: ... the higher priority DMA transfer request is acknowledged Caution Do not start more than one DMA channel using the same start factor If more than one DMA channel is started a lower priority DMA channel may be acknowledged prior to a higher priority DMA channel 6 9 Next Address Setting Function The DMA source address registers DSAnH DSAnL DMA destination address registers DDAnH DDAnL and DMA transf...

Page 160: ... DMA transfer The settings made are incorporated in only the master register and not in the slave register the slave register maintains the value set for the next DMA transfer However the contents of the master register are automatically overwritten in the slave register after DMA transfer ends 3 Time from DMA transfer end to the start of the next DMA transfer The settings made are incorporated in...

Page 161: ... interrupt request is issued from the on chip peripheral I O that is set in the DTFRn register DMA transfer starts n 0 to 3 Enn bit 1 TCn bit 0 6 11 Forcible Interruption DMA transfer can be forcibly interrupted by NMI input during DMA transfer At such a time the DMAC clears the Enn bit of the DCHCn register of all channels to 0 and the DMA transfer disabled state is entered An NMI request can the...

Page 162: ...ns 1 Memory boundary The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA objects external memory internal RAM or on chip peripheral I O during DMA transfer 2 Transfer of misaligned data DMA transfer of 16 bit bus width misaligned data is not supported 3 Times related to DMA transfer The overhead before and after DMA transfer and the minimum exe...

Page 163: ... DMA transfer for the internal RAM Execution of a bit manipulation instruction SET1 CLR1 or NOT1 allocated to the internal RAM or data access instruction to a misaligned address Prevent deadlock using one of the following methods Prevention methods Do not execute instructions allocated to the internal RAM if executing DMA transfer for the internal RAM Do not execute DMA transfer for the internal R...

Page 164: ...l opcode exception trap Eight levels of software programmable priorities can be specified for each interrupt request Interrupt servicing starts after no fewer than 4 system clocks 100 ns 50 MHz following the generation of an interrupt request 7 1 Features Interrupts Non maskable interrupts 1 source Maskable interrupts 52 sources 8 levels of programmable priorities maskable interrupts Multiple inte...

Page 165: ...0120H nextPC Interrupt INTTM01 TM0IC1 TM01 underflow RPU 11 0130H 00000130H nextPC Interrupt INTCM013 CM03IC1 CM013 match RPU 12 0140H 00000140H nextPC Interrupt INTP100 INTCC100 CC10IC0 INTP100 pin CC100 match Pin RPU 13 0150H 00000150H nextPC Interrupt INTP101 INTCC101 CC10IC1 INTP101 INTP100 pin CC101 match Pin RPU 14 0160H 00000160H nextPC Interrupt INTCM100 CM10IC0 CM100 match RPU 15 0170H 00...

Page 166: ...Interrupt INTCSI1 CSIIC1 CSI1 transmission reception complete SIO 42 0320H 00000320H nextPC Interrupt INTSR0 SRIC0 UART0 reception complete SIO 43 0330H 00000330H nextPC Interrupt INTST0 STIC0 UART0 transmission complete SIO 44 0340H 00000340H nextPC Interrupt INTSER0 SEIC0 UART0 reception error SIO 45 0350H 00000350H nextPC Interrupt INTSR1 SRIC1 UART1 reception complete SIO 46 0360H 00000360H ne...

Page 167: ...e external interrupt mode register 0 INTM0 is detected on the NMI pin the interrupt occurs While the service program of the non maskable interrupt is being executed PSW NP 1 the acknowledgement of another non maskable interrupt request is held pending The pending NMI is acknowledged after the original service program of the non maskable interrupt under execution has been terminated by the RETI ins...

Page 168: ...halfword FECC of ECR 4 Sets the NP and ID bits of the PSW and clears the EP bit 5 Sets the handler address 00000010H corresponding to the non maskable interrupt to the PC and transfers control The servicing configuration of a non maskable interrupt is shown in Figure 7 1 Figure 7 1 Servicing Configuration of Non Maskable Interrupt PSW NP FEPC FEPSW ECR FECC PSW NP PSW EP PSW ID PC restored PC PSW ...

Page 169: ...uest PSW NP 1 NMI request held pending regardless of the value of the NP bit of the PSW Pending NMI request processed b If a new NMI request is generated twice while an NMI service program is being executed Main routine NMI request NMI request Held pending because NMI service program is being processed Only one NMI request is acknowledged even though two NMI requests are generated NMI request Held...

Page 170: ...is 1 2 Transfers control back to the address of the restored PC and PSW Figure 7 3 illustrates how the RETI instruction is processed Figure 7 3 RETI Instruction Processing PSW EP RETI instruction PSW NP Original processing restored 1 1 0 0 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Caution When the PSW EP bit and PSW NP bit are changed by the LDSR instruction during non maskable interrupt servicing in or...

Page 171: ...0 0 0 0 0 0 0 Bit Position Bit Name Function 7 NP Indicates whether NMI interrupt servicing is in progress 0 No NMI interrupt servicing 1 NMI interrupt currently being serviced 7 2 4 Edge detection function 1 External interrupt mode register 0 INTM0 External interrupt mode register 0 INTM0 is a register that specifies the valid edge of a non maskable interrupt NMI The NMI valid edge can be specifi...

Page 172: ...g a higher priority than the interrupt request in progress specified by the interrupt control register Note that only interrupts with a higher priority will have this capability interrupts with the same priority level cannot be nested However if multiple interrupts are executed the following processing is necessary 1 Save EIPC and EIPSW in memory or a general purpose register before executing the ...

Page 173: ...that of other interrupt request Highest default priority of interrupt requests with the same priority EIPC EIPSW ECR EICC PSW EP PSW ID Corresponding bit of ISPRNote PC restored PC PSW exception code 0 1 1 handler address Note For the ISPR register see 7 3 6 In service priority register ISPR The INT input masked by the interrupt controllers and the INT input that occurs while another interrupt is ...

Page 174: ...and PSW Figure 7 5 illustrates the processing of the RETI instruction Figure 7 5 RETI Instruction Processing Note For the ISPR register see 7 3 6 In service priority register ISPR Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during maskable interrupt servicing in order to restore the PC and PSW correctly during recovery by the RETI instruction it is necessary ...

Page 175: ...iority level specified by the xxPRn bit are generated at the same time interrupts are serviced in order depending on the priority level allocated to each interrupt request type default priority level beforehand For more information refer to Table 7 1 Interrupt Exception Source List The programmable priority control customizes interrupt requests into eight levels by setting the priority level speci...

Page 176: ...upt request d is higher than that of c d is held pending because interrupts are disabled Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g Interrupt request b level 2 Interrupt request d level 2 Interrupt request f level 3 Ca...

Page 177: ...d Interrupt request j is held pending because its priority is lower than that of i k that occurs after j is acknowledged because it has the higher priority Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status Pending interrupt requests are acknowledged after servicing of interrupt request l At this time interrupt requests n is acknowledge...

Page 178: ...Servicing of interrupt request a Interrupt requests b and c are acknowledged first according to their priorities Because the priorities of b and c are the same b is acknowledged first according to the default priority Caution The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts When returning from multiple interrupt servicing restore the values of EIPC and ...

Page 179: ...t Name Function 7 xxIFn This is an interrupt request flag 0 Interrupt request not issued 1 Interrupt request issued The flag xxlFn is reset automatically by the hardware if an interrupt request is acknowledged 6 xxMKn This is an interrupt mask flag 0 Enables interrupt servicing 1 Disables interrupt servicing pending 8 levels of priority order are specified for each interrupt xxPRn2 xxPRn1 xxPRn0 I...

Page 180: ... FFFFF134H CC11IC1 CC11IF1 CC11MK1 0 0 0 CC11PR12 CC11PR11 CC11PR10 FFFFF136H CM11IC0 CM11IF0 CM11MK0 0 0 0 CM11PR02 CM11PR01 CM11PR00 FFFFF138H CM11IC1 CM11IF1 CM11MK1 0 0 0 CM11PR12 CM11PR11 CM11PR10 FFFFF13AH TM2IC0 TM2IF0 TM2MK0 0 0 0 TM2PR02 TM2PR01 TM2PR00 FFFFF13CH TM2IC1 TM2IF1 TM2MK1 0 0 0 TM2PR12 TM2PR11 TM2PR10 FFFFF13EH CC2IC0 CC2IF0 CC2MK0 0 0 0 CC2PR02 CC2PR01 CC2PR00 FFFFF140H CC2IC...

Page 181: ...MK0 0 0 0 SRPR02 SRPR01 SRPR00 FFFFF168H STIC0 STIF0 STMK0 0 0 0 STPR02 STPR01 STPR00 FFFFF16AH SEIC0 SEIF0 SEMK0 0 0 0 SEPR02 SEPR01 SEPR00 FFFFF16CH SRIC1 SRIF1 SRMK1 0 0 0 SRPR12 SRPR11 SRPR10 FFFFF16EH STIC1 STIF1 STMK1 0 0 0 STPR12 STPR11 STPR10 FFFFF170H SRIC2 SRIF2 SRMK2 0 0 0 SRPR22 SRPR21 SRPR20 FFFFF172H STIC2 STIF2 STMK2 0 0 0 STPR22 STPR21 STPR20 FFFFF174H ADIC0 ADIF0 ADMK0 0 0 0 ADPR0...

Page 182: ... 15 CM10MK0 7 DETMK0 IMR0 14 CC10MK1 6 P0MK6 13 CC10MK0 5 P0MK5 12 CM03MK1 4 P0MK4 11 TM0MK1 3 P0MK3 10 CM03MK0 2 P0MK2 9 TM0MK0 1 P0MK1 8 DETMK1 0 P0MK0 Address FFFFF100H Initial value FFFFH 15 CC3MK1 7 CC2MK0 IMR1 14 CC3MK0 6 TM2MK1 13 TM3MK0 5 TM2MK0 12 CC2MK5 4 CM11MK1 11 CC2MK4 3 CM11MK0 10 CC2MK3 2 CC11MK1 9 CC2MK2 1 CC11MK0 8 CC2MK1 0 CM10MK1 Address FFFFF102H Initial value FFFFH 15 STMK1 7...

Page 183: ...rned from non maskable interrupt servicing or exception processing This register is read only in 8 bit or 1 bit units Caution In the interrupt enabled EI state if an interrupt is acknowledged during the reading of the ISPR register the value of the ISPR register may be read after the bit is set to 1 by this interrupt acknowledgement To read the value of the ISPR register properly before interrupt ...

Page 184: ...errupt servicing is enabled or disabled 0 Maskable interrupt request acknowledgement enabled 1 Maskable interrupt request acknowledgement disabled pending This bit is set to 1 by the DI instruction and reset to 0 by the EI instruction Its value is also modified by the RETI instruction or LDSR instruction when referencing the PSW Non maskable interrupt requests and exceptions are acknowledged regar...

Page 185: ...lection register SESC and TM2 input filter mode registers 0 to 5 FEM0 to FEM5 1 External interrupt mode registers 1 2 INTM1 INTM2 These registers specify the valid edge for external interrupt requests INTP0 to INTP6 input via external pins The correspondence between each register and the external interrupt requests that register controls is shown below INTM1 INTP0 INTP1 INTP2 ADTRG0 INTP3 ADTRG1 I...

Page 186: ...ADTRG1 INTP2 ADTRG0 INTP1 INTP0 7 0 INTM2 6 0 5 ES61 4 ES60 3 ES51 2 ES50 1 ES41 0 ES40 Address FFFFF884H Initial value 00H INTP6 INTP5 INTP4 Bit Position Bit Name Function Specifies the valid edge of the INTPn ADTRG0 and ADTRG1 pins ESn1 ESn0 Operation 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges 7 to 0 INTM1 5 to 0 INTM2 ESn1 ESn0 n 0 to 6 ...

Page 187: ...ently for each pin rising edge falling edge or both rising and falling edges These registers can be read written in 8 bit or 1 bit units Cautions 1 The bits of the SESA1n register cannot be changed during TM1n operation TM1CEn bit of timer control registers 10 11 TMC10 TMC11 1 2 The TM1CEn bit must be set 1 before using the TCUD10 INTP100 TCLR10 INTP101 TCUD11 INTP110 and TCLR11 INTP111 pins as IN...

Page 188: ...lid only in UDC mode ANote 1 and UDC mode BNote 1 2 If TM1n operation has been specified in mode 4Note 2 the valid edge specification TESUDn1 and TESUDn0 bits for the TIUD1n and TCUD1n pins is invalid Specifies the valid edge of the TCLR10 and TCLR11 pins CESUDn1 CESUDn0 Valid Edge 0 0 Falling edge 0 1 Rising edge 1 0 Low level 1 1 High level 5 4 CESUDn1 CESUDn0 The setting values of the CESUDn1 a...

Page 189: ... of the CSL1n register INTP1n1 INTP1n0 IES1n11 IES1n10 Valid Edge 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges 3 2 IES1n11 IES1n10 Specifies the valid edge of the INTP100 and INTP110 pins IES1n01 IES1n00 Valid Edge 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 0 IES1n01 IES1n00 1 1 Both rising and falling edges Remark n 0 1 ...

Page 190: ...3 INTP30 and TO3 INTP31 pins as INTP30 and INTP31 even if not using timer 3 2 Before setting the INTP30 INTP31 TCLR3 and TI3 pins to the trigger mode set the PMC2 register If the PMC2 register is set after the SESC register has been set an illegal interrupt may occur as soon as the PMC2 register is set 7 TES31 SESC 6 TES30 5 CES31 4 CES30 3 IES311 2 IES310 1 IES301 0 IES300 Address FFFFF689H Initi...

Page 191: ...d edge can be specified independently for each pin rising edge falling edge or both rising and falling edges These registers can be read written in 8 bit or 1 bit units Cautions 1 The STFTE bit of timer 2 clock stop register 0 STOPTE0 must be cleared 0 before using the TI2 INTP20 TO21 INTP21 TO22 INTP22 TO23 INTP23 TO24 INTP24 and TCLR2 INTP25 pins as INTP20 INTP21 INTP22 INTP23 INTP24 and INTP25 ...

Page 192: ...04 1 TMS014 0 TMS004 Address FFFFF634H Initial value 00H INTP24 7 DFEN05 FEM5 6 0 5 0 4 0 3 EDGE015 2 EDGE005 1 TMS015 0 TMS005 Address FFFFF635H Initial value 00H INTP25 Bit Position Bit Name Function 7 DFEN0n Specifies the filter of the INTP2n pin 0 Analog filter 1 Digital filter Caution When the DFEN0n bit 1 the sampling clock of the digital filter is fXXTM2 clock of TM20 and TM21 selected by P...

Page 193: ...n Note Selection of capture input based on INTCM100 and INTCM101 is valid only for the FEM1 and FEM2 registers Set the TMS01m and TMS00m bits of the FEMm register to 00B or 01B All other settings are prohibited m 1 3 to 5 Sub channels 1 and 2 of timer 2 can be captured by INTP21 INTP22 and INTCM100 INTCM101 An example is given below a When sub channel 1 is captured by INTCM101 FEM1 register xxxxxx...

Page 194: ...nterrupt source 4 Sets the EP and ID bits of the PSW 5 Sets the handler address 00000040H or 00000050H corresponding to the software exception to the PC and transfers control Figure 7 8 illustrates the processing of a software exception Figure 7 8 Software Exception Processing TRAP instruction EIPC EIPSW ECR EICC PSW EP PSW ID PC restored PC PSW exception code 1 1 handler address CPU processing Ex...

Page 195: ...to the address of the restored PC and PSW Figure 7 9 illustrates the processing of the RETI instruction Figure 7 9 RETI Instruction Processing PSW EP RETI instruction PC PSW EIPC EIPSW PSW NP Original processing restored PC PSW FEPC FEPSW 1 1 0 0 Caution When the PSW EP bit and the PSW NP bit are changed by the LDSR instruction during the software exception processing in order to restore the PC an...

Page 196: ...d to indicate that exception processing is in progress It is set when an exception occurs 31 0 PSW Initial value 00000020H 7 NP 6 EP 5 ID 4 SAT 3 CY 2 OV 1 S Z 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Position Bit Name Function 6 EP Shows that exception processing is in progress 0 Exception processing not in progress 1 Exception processing in progress ...

Page 197: ...ion trap is generated when an instruction applicable to this illegal instruction is executed 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to Arbitrary Caution Since it is possible to assign this instruction to an illegal opcode in the future it is recommended that it not be used 1 Operation If an exception trap occurs the CPU performs the following processing and transfers contro...

Page 198: ...tion trap is carried out by the DBRET instruction By executing the DBRET instruction the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Figure 7 11 illustrates the restore processing from an exception trap Figure 7 11 Restore Processing f...

Page 199: ...performs the following processing 1 Operation 1 Saves the restored PC to DBPC 2 Saves the current PSW to DBPSW 3 Sets the NP EP and ID bits of the PSW 4 Sets the handler address 00000060H corresponding to the debug trap to the PC and transfers control Figure 7 12 illustrates the processing of the debug trap Figure 7 12 Debug Trap Processing DBTRAP instruction DBPC DBPSW PSW NP PSW EP PSW ID PC res...

Page 200: ...n the CPU carries out the following processing and controls the address of the restored PC 1 Loads the restored PC and PSW from DBPC and DBPSW 2 Transfers control to the address indicated by the restored PC and PSW Figure 7 13 illustrates the restore processing from a debug trap Figure 7 13 Restore Processing from Debug Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC ...

Page 201: ...ervicing control is executed when interrupts are enabled ID 0 Thus if multiple interrupts are executed it is necessary for interrupts to be enabled ID 0 even during an interrupt servicing routine If a maskable interrupt or a software exception is generated in a maskable interrupt or software exception service program it is necessary to save EIPC and EIPSW This is accomplished by the following proc...

Page 202: ...rupt request After system reset an interrupt request is masked by the xxMKn bit and the priority order is set to level 7 by the xxPRn0 to xxPRn2 bits The priority order of maskable interrupts is as follows High Level 0 Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 Low Interrupt servicing that has been suspended as a result of multiple servicing control is resumed after the servicing of t...

Page 203: ...P100 INTP30 INTP101 INTP31 INTP110 INTP111 Condition Mini mum 4 4 analog delay time 4 digital noise filter 4 Note 1 digital noise filter Maxi mum 7Note 2 7 analog delay time 7 digital noise filter 7 Note 1 digital noise filter The following cases are exceptions In IDLE software STOP mode External bus access Two or more interrupt request non sampling instructions are executed in succession Access t...

Page 204: ...ruction and the next instruction interrupt is held pending The interrupt request non sampling instructions are as follows EI instruction DI instruction LDSR reg2 0x5 instruction for PSW The load store and bit manipulation instructions for the interrupt control register xxlCn in service priority register ISPR and interrupt mask registers 0 to 3 IMR0 to IMR3 The store instruction for the command reg...

Page 205: ...tiplier function using a phase locked loop PLL synthesizer Clock sources Oscillation by connecting a resonator External clock Power saving modes HALT mode IDLE mode Software STOP mode Internal system clock output function 8 2 Configuration X1 X2 Clock generator CG CKSEL fX CPU on chip peripheral I O Time base counter TBC CLKOUT fXX Remark fX External resonator or external clock frequency fXX Inter...

Page 206: ...ect mode an external clock must be input an external resonator should not be connected 8 3 2 PLL mode In PLL mode an external resonator is connected or external clock is input and multiplied by the PLL synthesizer The multiplied PLL output is divided by the division ratio specified by the clock control register CKC to generate a system clock that is 10 5 2 5 or 1 times the frequency fX of the exte...

Page 207: ...sters that can significantly affect the system so that the application system is not halted unexpectedly due to erroneous program execution This register can be written only in 8 bit units when it is read undefined data is read out Writing to the first specific register CKC or FLPMC register is only valid after first writing to the PHCMD register Because of this the register value can be overwritt...

Page 208: ...e X1 and X2 pins 0 A resonator is connected to the X1 and X2 pins 1 An external clock is connected to the X1 pin When CESEL 1 the oscillator feedback loop is disconnected to prevent current leak in software STOP mode Sets the internal system clock frequency fXX when PLL mode is used CKDIV2 CKDIV1 CKDIV0 Internal System Clock fXX 0 0 0 fX 0 0 1 2 5 fX 0 1 1 5 fX 1 1 1 10 fX Other than above Setting...

Page 209: ...n to PSW rY Value returned to PSW No special sequence is required to read the specific register Cautions 1 If an interrupt is acknowledged between the issuing of data to the PHCMD 3 and writing to the specific register immediately after 4 the write operation to the specific register is not performed and a protection error the PRERR bit of the PHS register 1 may occur Therefore set the NP bit of th...

Page 210: ... 7 6 5 4 3 2 1 0 Address Initial value PHS 0 0 0 0 0 0 0 PRERR FFFFF802H 00H Bit Position Bit Name Function 0 PRERR Protection error 0 Protection error does not occur 1 Protection error occurs The operation conditions of the PRERR flag are as follows Set conditions 1 If the operation of the relevant store instruction for the on chip peripheral I O is not a write operation for the PHCMD register bu...

Page 211: ...ame Function 0 LOCK This is a read only flag that indicates the PLL state This flag holds the value 0 as long as a lockup state is maintained and is not initialized by a system reset 0 Indicates that the PLL is locked 1 Indicates that the PLL is not locked UNLOCK state If the clock stops the power fails or some other factor operates to cause an unlock state to occur for control processing that dep...

Page 212: ...STOP mode and HALT mode in relation to the clock stabilization time and current consumption It is used for situations in which a low current consumption mode is to be used and the clock stabilization time is to be eliminated after the mode is released 3 Software STOP mode In this mode the overall system is stopped by stopping the clock generator oscillator and PLL synthesizer The system enters an ...

Page 213: ...ed use Figure 8 1 Power Save Mode State Transition Diagram Note INTPn n 0 to 6 20 to 25 However when a digital filter using clock sampling is selected as the noise eliminator for INTP20 to INTP25 the software STOP or IDLE mode cannot be released Normal operation mode Software STOP mode Set STOP mode IDLE mode Set IDLE mode Release according to RESET NMI or maskable interrupt Note Set HALT mode Rel...

Page 214: ... Mode Oscillator PLL Synthesizer Clock Supply to Peripheral I O Clock Supply to CPU Normal operation HALT mode IDLE mode Oscillation with resonator Software STOP mode Normal operation HALT mode IDLE mode PLL mode External clock Software STOP mode Normal operation HALT mode IDLE mode Direct mode External clock Software STOP mode Remark Operating Stopped ...

Page 215: ...TOP mode 2 Command register PRCMD This is an 8 bit register that is used to set protection for write operations to registers that can significantly affect the system so that the application system is not halted unexpectedly due to erroneous program execution Writing to the first specific register power save control register PSC is only valid after first writing to the PRCMD register Because of thi...

Page 216: ...d maskable interrupt INTPn n 0 to 6 20 to 25 30 31 100 101 110 111 0 Enables maskable interrupt cancellation 1 Disables maskable interrupt cancellation 1 STB Indicates the standby mode status If 1 is written to this bit the system enters IDLE or software STOP mode set by the PSM bit of the PSMR register When standby mode is released this bit is automatically reset to 0 0 Standby mode is released 1...

Page 217: ...not acknowledge interrupts This coding is made on assumption that 3 and 4 above are executed by the program with consecutive store instructions If another instruction is set between 3 and 4 the above sequence may become in effective when the interrupt is acknowledged by that instruction and a malfunction of the program may result 2 Although the data written to the PRCMD register is dummy data use ...

Page 218: ...ents of all registers internal RAM and ports are maintained in the state they were in immediately before HALT mode began Also operation continues for all on chip peripheral I O units other than ports that do not depend on CPU instruction processing Table 8 2 shows the status of each hardware unit in HALT mode Table 8 2 Operation Status in HALT Mode Function Operation Status Clock generator Operati...

Page 219: ...er priority than that of the interrupt request that is currently being serviced HALT mode is released but the newly generated interrupt request is not acknowledged The new interrupt request is held pending ii If an interrupt request including non maskable interrupt requests is generated with a higher priority than that of the interrupt request that is currently being serviced HALT mode is released...

Page 220: ...mode program execution is stopped and the contents of all registers internal RAM and ports are maintained in the state they were in immediately before execution stopped The operation of on chip peripheral I O units excluding ports also is stopped Table 8 4 shows the status of each hardware unit in IDLE mode Table 8 4 Operation Status in IDLE Mode Function Operation Status Clock generator Operating...

Page 221: ...n maskable interrupt requests is generated with a higher priority than that of the interrupt request that is currently being serviced IDLE mode is released and the newly generated interrupt request is acknowledged Table 8 5 Operation After IDLE Mode Is Released by Interrupt Request Release Source Enable Interrupt EI Status Disable Interrupt DI Status Non maskable interrupt request Branch to handle...

Page 222: ...re STOP mode the contents of all registers internal RAM and ports are maintained in the state they were in immediately before software STOP mode began The operation of all on chip peripheral I O units excluding ports is also stopped Table 8 6 shows the status of each hardware unit in software STOP mode Table 8 6 Operation Status in Software STOP Mode Function Operation Status Clock generator Stopp...

Page 223: ...de is released but the newly generated interrupt request is not acknowledged The new interrupt request is held pending ii If an interrupt request including non maskable interrupt requests is generated with a higher priority than that of the interrupt request that is currently being serviced software STOP mode is released and the newly generated interrupt request is acknowledged Table 8 7 Operation...

Page 224: ...processing branches to the NMI interrupt or maskable interrupt INTPn handler address Oscillation waveform X2 Set software STOP mode Oscillator is stopped CLKOUT output Internal main clock STOP state NMI input Note Time base counter s counting time Note Valid edge When specified as the rising edge The NMI pin should usually be set to an inactive level for example high level when the valid edge is s...

Page 225: ...illation stabilization time secured by RESET RESET input Undefined CLKOUT output Undefined 8 6 2 Time base counter TBC The time base counter TBC is used to secure the oscillator s oscillation stabilization time when software STOP mode is released When an external clock is connected CESEL bit of CKC register 1 or a resonator is connected PLL mode and CESEL bit of CKC register 0 the TBC counts the o...

Page 226: ...triangular wave PWM mode 2 sawtooth wave Interrupt culling function Culling ratios 1 1 1 2 1 4 1 8 1 16 Forcible 3 phase PWM output stop function 3 phase PWM output can be forcibly stopped by inputting a signal from external signal input pin ESOn during anomalies This function can also be used when the clock is stopped Real time output function 3 phase PWM output or rectangular wave output can be ...

Page 227: ...LK 2 types set fCLK to 40 MHz or less fXX and fXX 2 can be selected Prescaler division ratio The following division ratios can be selected according to the base clock fCLK Base Clock fCLK Division Ratio fXX Selected fXX 2 Selected 1 1 fXX fXX 2 1 2 fXX 2 fXX 4 1 4 fXX 4 fXX 8 1 8 fXX 8 fXX 16 1 16 fXX 16 fXX 32 1 32 fXX 32 fXX 64 Interrupt request sources Compare match interrupt request 2 types IN...

Page 228: ... DTRRn 6 TO0n0 U phase TO0n1 U phase TO0n2 V phase TO0n3 V phase TO0n4 W phase TO0n5 W phase Selector Output control by external input ESOn TM0n timer operation Underflow Underflow Underflow ALVUB ALVVB ALVWB R S R S R S R S R S R S ALVTO fXX Remarks 1 TM0n Timer register CM0n0 to CM0n3 Compare registers BFCMn0 to BFCMn3 Buffer registers DTRRn Dead time timer reload register DTMn0 to DTMn2 Dead ti...

Page 229: ...n4 W phase TO0n5 W phase Underflow Underflow Underflow fXX 2 Selector Clear Output control by external input ESOn TM0n timer operation fCLK R S R S R S R S R S R S ALVUB ALVVB ALVWB ALVTO fXX Remarks 1 TM0n Timer register CM0n0 to CM0n3 Compare registers BFCMn0 to BFCMn3 Buffer registers DTRRn Dead time timer reload register DTMn0 to DTMn2 Dead time timers ALVTO Bit 7 of TOMRn register ALVUB Bit 6...

Page 230: ...r 0n3 CM0n3 match PWM mode 2 sawtooth wave only Immediately after overflow or underflow The TM0n timer has 3 operation modes shown in Table 9 1 The operation mode is selected with timer control register 0n TMC0n Table 9 1 Timer 0 Operation Modes Operation Mode Count Operation Timer Clear Source Interrupt Source BFCMn3 CM0n3 Transfer Timing BFCMn0 to BFCMn2 CM0n0 to CM0n2 Transfer Timing PWM mode 0...

Page 231: ...e timer count operation disabled an inverted signal without dead time is output to TO0n0 and TO0n1 TO0n2 and TO0n3 and TO0n4 and TO0n5 3 Dead time timer reload registers 0 1 DTRR0 DTRR1 DTRRn register is a 12 bit register used to set the values of the three dead time timers DTMn0 to DTMn2 registers n 0 1 However a value is transferred from the DTRRn register to each dead time register independentl...

Page 232: ...responding to each buffer register when an interrupt signal INTCM0n3 INTTM0n is generated BFCMn0 to BFCMn2 can be read written in 16 bit units Caution The set values of the BFCMn0 to BFCMn2 registers are transferred to the CM0n0 to CM0n2 registers in the following timing n 0 1 When TM0CEn bit of TMC0n register 0 Transfer at next operation timing after writing to BFCMn0 to BFCMn2 registers When TM0...

Page 233: ... to the CM0n3 register in the following timing n 0 1 When TM0CEn bit of TMC0n register 0 Transfer at next operation timing after writing to BFCMn3 register When TM0CEn bit of TMC0n register 1 Value of BFCMn3 register is transferred to CM0n3 register upon occurrence of INTTM0n At this time transfer enable or disable is controlled by the BFTE3 bit of the timer control register TMC0n 2 Setting the BF...

Page 234: ...1 bit units Caution Always set this register before using the timer 7 0 PRM01 6 0 5 0 4 0 3 0 2 0 1 0 0 PRM1 Address FFFFF5D0H Initial value 00H Bit Position Bit Name Function 0 PRM1 Specifies the base clock fCLK of timer 0 TM0n See Figure 9 3 0 fXX 2 When fXX 40 MHz 1 fXX When fXX 40 MHz Remark fXX Internal system clock Figure 9 3 Timer 00 and Timer 01 Clock Timer 00 Timer 01 PRM1 fCLK fXX 2 Sele...

Page 235: ...00 15 TM0CE1 1 MOD01 0 MOD00 TMC01 Address FFFFF5BAH Initial value 0508H Bit Position Bit Name Function 15 TM0CEn Specifies the operation of TM0n 0 Count disabled stops after all count values are cleared 1 Count enabled Caution When TM0CEn 0 TO0n0 to TO0n5 output becomes high impedance 14 STINTn Specifies interrupt during TM0n timer start 0 Don t generate interrupt at operation start 1 Generate in...

Page 236: ...ge see Figure 9 5 Specifies the count clock for TM0n PRM02 PRM01 PRM00 Count Clock 0 0 0 fCLK 0 0 1 fCLK 2 0 1 0 fCLK 4 0 1 1 fCLK 8 1 0 0 fCLK 16 1 0 1 fCLK 32 Other than above Setting prohibited 10 to 8 PRM02 to PRM00 Caution The division ratio switch timing is from when the TM0n value has become 0000H and an INTTM0n interrupt has occurred Therefore in the timing that corresponds to interrupt cu...

Page 237: ...c triangular wave INTTM0n 1 PWM mode 1 asymmetric triangular wave INTTM0n INTCM0n3 1 PWM mode 2 sawtooth wave INTCM0n3 3 BFTEN When the BFTEN bit 1 the values of the BFCMn0 to BFCMn2 registers are transferred to the CM0n0 to CM0n2 registers upon occurrence of an INTTM0n or INTCM0n3 interrupt When culling of INTTM0n and INTCM0n3 interrupts is set with the CUL02 to CUL00 bits specifies whether enabl...

Page 238: ... mode 2 sawtooth wave Up INTCM0n3 INTCM0n3 INTCM0n3 1 1 Setting prohibited 1 0 MOD01 MOD00 Caution Changing the value of the MOD01 MOD00 bits during TM0n operation TM0CEn bit 1 is prohibited Remark n 0 1 Figure 9 4 Specification of INTTM0n Interrupt During PWM Mode 0 Symmetric Triangular Wave PWM Mode 1 Asymmetric Triangular Wave MOD01 MOD00 Bits of TMC0n Register 0n CM0n3 TM0n count value 0000H T...

Page 239: ... b PWM mode 1 asymmetric triangular wave CM0n3 TM0n count value 0000H CUL02 to CUL00 INTTM0n occurrence INTCM0n3 occurrence Interrupt request INTCM0n3 occurrence INTCM0n3 occurrence INTCM0n3 occurrence INTTM0n occurrence Interrupt culling 1 1 cycle Interrupt culling 1 2 cycle INTTM0n occurrence INTTM0n occurrence 000 001 Remark n 0 1 c PWM mode 2 sawtooth wave CM0n3 TM0n count value 0000H CUL02 to...

Page 240: ...3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTCM0n3 001 010 000 Interrupt culling 1 2 cycle Interrupt culling 1 4 cycle Interrupt culling 1 1 cycle TM0CEn bit TM0n count value CUL02 to CUL00 bits STINTn 1 INTTM0n INTTM0n INTTM0n INTTM0n INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTCM0n3 001 010 000 Interrupt culling 1 2 cycle Interrupt culling 1 4 cycle Interrupt culli...

Page 241: ...Sn bit Cautions 1 If the level is set for the ESOn pin input level TOMR register TOEDG1 bit 1 TOEDG0 bit 0 or 1 the output disabled state is not released TOSTAn bit 1 even if 1 is written to the TORSn bit while the output is disabled TOSTAn bit 1 If the input level is inactive the output disabled state is released TOSTAn bit 0 The value of the TORSn bit is held 2 If the edge is set for the ESOn pi...

Page 242: ... using the internal bus during servicing of these interrupts Add one of the following processing items during the TOMRn register write routine Prior to write access to the TOMRn register disable acknowledge of all interrupts of CPU Following write access to the TOMRn register check that write was performed normally 1 2 7 ALVTO TOMR0 6 ALVUB 5 ALVVB 4 ALVWB 3 TOSP 2 0 1 TOEDG1 0 TOEDG0 Address FFFF...

Page 243: ... pin output stop through ESOn pin input 0 Enables ESOn pin input 1 Disables ESOn pin input Cautions 1 The output stop status can be released by writing 1 to the TORSn bit of the TUC0n register The operation continues even if output is prohibited for all timers and counters 2 Before changing the ESOn pin input status from disable to enable changing TOSP bit from 1 to 0 write 1 to the TORSn bit of t...

Page 244: ...in PWM mode 0 symmetric triangular waves are shown below Figure 9 7 Output Waveforms of TO000 and TO001 in PWM Mode 0 Symmetric Triangular Waves Without Dead Time TM0CED0 Bit 1 a TOMR0 register value 80H TM00 CM000 TO000 TO001 TM00 CM000 b TOMR0 register value 00H TM00 CM000 TO000 TO001 TM00 CM000 c TOMR0 register value C0H TM00 CM000 TO000 TO001 TM00 CM000 d TOMR0 register value 40H TM00 CM000 TO...

Page 245: ...M0CED0 Bit 0 a TOMR0 register value 80H TM00 CM000 TO000 TO001 TM00 CM000 Dead time period Dead time period b TOMR0 register value 00H TM00 CM000 TO000 TO001 TM00 CM000 Dead time period Dead time period c TOMR0 register value C0H TM00 CM000 TO000 TO001 TM00 CM000 Dead time period Dead time period d TOMR0 register value 40H TM00 CM000 TO000 TO001 TM00 CM000 Dead time period Dead time period ...

Page 246: ...structions Bit manipulation instruction SET1 CLR1 NOT1 instructions Description example 1 MOV 0x04 r10 2 ST B r10 SPECn r0 3 ST B r10 TOMRn r0 Remark n 0 1 To read the TOMRn register no special sequence is required Cautions 1 Disable interrupts between SPECn issue 2 and TOMRn register write that immediately follows 3 2 The data written to the SPECn register is dummy data use the same register as t...

Page 247: ...TO0n4 output status is high impedance 1 TO0n4 output status is controlled by TM0CEn bit of TMC0n register and TORTOn bit of PSTOn register and ESOn pin 3 OE11n Specifies output status of TO0n3 pin 0 TO0n3 output status is high impedance 1 TO0n3 output status is controlled by TM0CEn bit of TMC0n register and TORTOn bit of PSTOn register and ESOn pin 2 OE10n Specifies output status of TO0n2 pin 0 TO...

Page 248: ... during TM0n operation TM0CEn bit 1 INTTM0n and INTCM0n3 interrupts Continue occurring at each timing in accordance with timer and compare operations TO0n0 to TO0n5 outputs Software output has priority 3 If the TORTOn bit is changed from 1 to 0 during TM0n operation TM0CEn bit 1 the software output state is retained for the TO0n0 to TO0n5 outputs until one of the set reset condition of the flip fl...

Page 249: ...the same way as during normal timer operation 1 VPORTn Specifies the TO0n2 V phase TO0n3 V phase pin output value Caution If the VPORTn bit setting value is changed when TORTOn 1 the dead time setting becomes valid for the TO0n2 TO0n3 output signal in the same way as during normal timer operation Remark n 0 1 ALVTO bit Bit 7 of the TOMRn register ALVUB bit Bit 6 of the TOMRn register ALVVB bit Bit...

Page 250: ...M0CEn 1 timer operation enabled TORTOn 1 software output enabled to TM0CEn 1 timer operation enabled TORTOn 0 software output disabled the TO0n0 to TO0n5 pins continue to perform software output until the occurrence of the first F F set reset due to a match between TM0n and the compare register after the TORTOn bit setting changes The relationship between the settings of the TORTOn and TM0CEn bits...

Page 251: ... Note 2 Note 2 Note 1 Note 4 Notes 1 F F set by compare match during up count 2 F F reset by compare match during down count 3 F F set by writing UPORTn bit 4 F F reset by writing UPORTn bit Remark n 0 1 If the setting of the TORTOn bit changes from 1 to 0 while the UPORTn bit is set to 1 in the P1 period in Figure 9 9 above the F F continues to hold the TORTOn bit setting of 1 until the T1 timing...

Page 252: ...ch during up count 2 F F reset by compare match during down count 3 F F set by writing UPORTn bit 4 F F reset by writing UPORTn bit Remark n 0 1 If the setting of the TORTOn bit changes from 1 to 0 while the UPORTn bit is set to 0 in the P1 period in Figure 9 10 above the F F continues to hold the TORTOn bit setting of 0 until the T2 timing However because the F F is set at the T2 timing by a comp...

Page 253: ...e 3 Notes 1 F F set by compare match during up count 2 F F reset by compare match during down count 3 F F set by writing UPORTn bit 4 F F reset by writing UPORTn bit Remark n 0 1 If the setting of the TORTOn bit changes from 0 to 1 while the UPORTn bit is set to 0 during TM0n operation TM0CEn 1 the TO0n0 output changes from 1 to 0 because the F F is reset at the T3 timing Examples of the software ...

Page 254: ...Software Output Waveforms of TO000 and TO001 Without Dead Time TM0CED0 1 a TOMR0 register value 80H UPORT0 1 TO000 TO001 UPORT0 0 b TOMR0 register value 00H UPORT0 1 TO000 TO001 UPORT0 0 c TOMR0 register value C0H UPORT0 1 TO000 TO001 UPORT0 0 d TOMR0 register value 40H UPORT0 1 TO000 TO001 UPORT0 0 ...

Page 255: ... 0 a TOMR0 register value 80H UPORT0 1 TO000 TO001 UPORT0 0 Dead time period Dead time period b TOMR0 register value 00H UPORT0 1 TO000 TO001 UPORT0 0 Dead time period Dead time period c TOMR0 register value C0H UPORT0 1 TO000 TO001 UPORT0 0 Dead time period Dead time period d TOMR0 register value 40H UPORT0 1 TO000 TO001 UPORT0 0 Dead time period Dead time period ...

Page 256: ...PORT0 1 UPORT0 0 UPORT0 1 TO000 TO001 Dead time period Dead time period The following table shows the output status of external pulse output in the case of TO0n0 Table 9 2 Output Status of External Pulse Output In Case of TO0n0 OE00n Bit TORTOn UPORTn Bits TM0CEn Bit TO0n0 0 0 1 0 1 High impedance 0 High impedance 0 1 Timer output 1 1 0 1 Output by UPORTn bit Remarks 1 OE00n bit Bit 0 of POERn reg...

Page 257: ...ediately after write to the SPECn register any data can be written write processing to the TOMRn register is not performed normally Normally 0000H is read The SPECn register can be read written in 16 bit units Remark n 0 1 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 15 0 1 0 0 0 SPEC0 Address FFFFF580H Initial value 0000H 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 15 0 1...

Page 258: ...a match interrupt INTCM0n3 is generated The count clock to TM0n can be selected from among 6 internal clocks with the TMC0n register If the TM0n has been set as an up down timer an underflow interrupt INTTM0n is generated when TM0n becomes 0000H during down counting The TM0n has the following three operation modes which are selected with timer control register 0n TMC0n PWM mode 0 Triangular wave m...

Page 259: ...clock is set with the TMC0n register iii Set the dead time width in DTRRn Dead time width DTRRn 1 fCLK fCLK Base clock iv Set the set reset timing of the F F used in the PWM cycle in BFCMn0 to BFCMn2 d Clear 0 the TM0CEDn bit of the TMC0n register to enable dead time timer operation Set TM0CEDn 1 when not using dead time e Setting 1 the TM0CEn bit of the TMC0n register starts TM0n counting and a 6...

Page 260: ...ration of the INTTM0n interrupt Furthermore software processing is started up and calculation performed and set reset timing of the F F for the next cycle is set to BFCMn0 to BFCMn2 The PWM cycle and the PWM duty are set in the above procedure The F F set reset conditions upon match of CM0n0 to CM0n2 are as follows Set CM0n0 to CM0n2 match detection during TM0n up count operation Reset CM0n0 to CM...

Page 261: ...0nXup Set value of CM0n0 to CM0n2 while TM0n is counting up CM0nXdown Set value of CM0n0 to CM0n2 while TM0n is counting down The pin level when the TO0n0 to TO0n5 pins are reset is the high impedance state When the control mode is selected thereafter the following levels are output until the TM0n is started TO0n0 TO0n2 TO0n4 When low active High level When high active Low level TO0n1 TO0n3 TO0n5 ...

Page 262: ...TO0n4 Negative phase TO0n1 TO0n3 TO0n5 BFCMnx BFCMn3 CM0n3 DTMnx F F CM0nx Interrupt request 0000H Remarks 1 The above figure shows the timing chart when BFTE3 and BFTEN of the TMC0n register are 1 and transfer from BFCMn3 to CM0n3 or from BFCMnx to CM0nx is enabled Transfer is not performed when BFTE3 0 or BFTEN 0 2 n 0 1 3 x 0 to 2 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 To not use dead tim...

Page 263: ...0 Symmetric Triangular Wave CM0n3 TM0n count value TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output 0000H CM0n2 CM0n2 CM0n1 CM0n1 CM0n0 CM0n0 CM0n3 CM0n2 CM0n2 CM0n1 CM0n1 CM0n0 CM0n0 Without dead time With dead time Remark n 0 1 ...

Page 264: ... n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows an active high case When a value greater than CM0n3 is set to BFCMnx the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a low level and the negative phase side TO0n1 TO0n3 TO0n5 pins continues to output a high level This feature is effective for outputting a low level or high level width exceeding the PWM cyc...

Page 265: ...TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 BFCMnx DTMnx F F Interrupt request CM0nx 0000H Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows an active high case Since TM0n CM0nx 0000H match is detected during up counting by TM0n the F F is just set and does not get reset Even when the setting value is 0000H F F is changed in the cycle during which tran...

Page 266: ...TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 0000H 0000H b c a 0000H 0000H Note b CM0n3 CM0n3 a a CM0nx match CM0nx match CM0nx match CM0n3 b b t t t t t t INTTM0n INTTM0n INTTM0n INTTM0n CM0nx match CM0nx match CM0nx match a INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 Note F F is reset upon INTTM0n occurrence Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure s...

Page 267: ...ock is set with the TMC0n register iii Set the dead time width in DTRRn Dead time width DTRRn 1 fCLK fCLK Base clock iv Set the set timing of the F F used in the PWM cycle in BFCMn0 to BFCMn2 d Clear 0 the TM0CEDn bit of the TMC0n register to enable dead time timer operation Set TM0CEDn 1 when not using dead time e Setting 1 the TM0CEn bit of the TMC0n register starts TM0n counting and a 6 channel...

Page 268: ... the PWM duty are set in the above procedure The F F set reset conditions upon match of CM0n0 to CM0n2 are as follows Set CM0n0 to CM0n2 match detection during TM0n up count operation Reset CM0n0 to CM0n2 match detection during TM0n down count operation The values of DTRRn are transferred to the corresponding dead time timers DTMn0 to DTMn2 in synchronization with the set reset timing of the F F a...

Page 269: ...to CM0n2 while TM0n is counting down The pin level when the TO0n0 to TO0n5 pins are reset is the high impedance state When the control mode is selected thereafter the following levels are output until the TM0n is started TO0n0 TO0n2 TO0n4 When low active High level When high active Low level TO0n1 TO0n3 TO0n5 When low active Low level When high active High level The active level is set with the AL...

Page 270: ...0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 Interrupt request BFCMnx BFCMn3 CM0n3 DTMnx F F CM0nx 0000H Remarks 1 The above figure shows the timing chart when BFTE3 and BFTEN of the TMC0n register are 1 and transfer from BFCMn3 to CM0n3 or from BFCMnx to CM0nx is enabled Transfer is not performed when BFTE3 0 or BFTEN 0 2 n 0 1 3 x 0 to 2 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 To not use dead...

Page 271: ... Asymmetric Triangular Wave CM0n3 TM0n count value TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output 0000H CM0n2 CM0n2 CM0n1 CM0n1 CM0n0 CM0n0 CM0n3 CM0n2 CM0n2 CM0n1 CM0n1 CM0n0 CM0n0 Without dead time With dead time Remark n 0 1 ...

Page 272: ...CLK Base clock 5 The above figure shows an active high case When a value greater than CM0n3 is set to BFCMnx the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a low level and the negative phase side TO0n1 TO0n3 TO0n5 pins continues to output a high level This feature is effective for outputting a low level or high level width exceeding the PWM cycle in an application such as inverter control ...

Page 273: ... 2 3 b CM0n3 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case When a value greater than CM0n3 is set to BFCMnx the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a high level and the negative phase side TO0n1 TO0n3 TO0n5 pins continues to output a low level This feature is effective for outputting a low level or high level width exceeding the PWM cycle in...

Page 274: ...est Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 b b b b b c d e Note CM0n3 CM0n3 a CM0nx match CM0n3 c d CM0nx match CM0nx match a b b b b b c d e t t t t INTTM0n INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTTM0n Note F F is reset upon INTTM0n occurrence Remarks 1 n 0 1 2 x 0 to 2 3 b CM0n3 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an activ...

Page 275: ...gative phase TO0n1 TO0n3 TO0n5 BFCMnx DTMnx F F Interrupt request CM0nx 0000H b 0000H 0000H 0000H a b a 0000H 0000H 0000H INTCM0n3 INTCM0n3 INTTM0n Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows an active high case Since TM0n CM0nx 0000H match is detected during up counting by TM0n the F F is just set and does not get reset Moreover the F F gets set ...

Page 276: ...TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 b c d e Note CM0n3 CM0n3 a c CM0nx match CM0n3 d b CM0nx match CM0nx match 0000H 0000H 0000H 0000H d e t t t t t t INTTM0n INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTTM0n CM0nx match CM0nx match 0000H 0000H 0000H 0000H b c a INTCM0n3 INTCM0n3 Note F F is reset upon INTTM0n occurrence Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The ...

Page 277: ...H 0000H 0000H INTCM0n3 INTCM0n3 Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows an active high case Since TM0n CM0nx 0000H match is detected during up counting by TM0n the F F is just set and does not get reset Therefore the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a high level and the negative phase side TO0n1 TO0n3 TO0n5 pins continues to ...

Page 278: ...hase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 b c d Note CM0n3 CM0n3 a CM0nx match CM0n3 b c CM0nx match CM0nx match a 0000H 0000H 0000H 0000H 0000H b d t t t t INTTM0n INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTTM0n 0000H 0000H 0000H 0000H 0000H c Note F F is reset upon INTTM0n occurrence Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figur...

Page 279: ... 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case Since TM0n and CM0nx match is detected during count down of TM0n when BFCMnx CM0n3 has been set the F F remains reset as is and does not get set Therefore the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a low level and the negative phase side TO0n1 TO0n3 TO0n5 pins continues to output a high level Moreo...

Page 280: ...th bit BFTEN c Set the initial values i Specify the interrupt culling ratio with bits CUL02 to CUL00 of the TMC0n register ii Set the cycle width of the PWM cycle in BFCMn3 PWM cycle BFCMn3 value 1 TM0n count clock The TM0n count clock is set with the TMC0n register iii Set the dead time width in DTRRn Dead time width DTRRn 1 fCLK fCLK Base clock iv Set the set reset timing of the F F used in the ...

Page 281: ... calculation performed and reset timing of the F F for the next cycle is set to BFCMn0 to BFCMn2 The PWM cycle and the PWM duty are set in the above procedure The F F set reset conditions upon match of CM0n0 to CM0n2 are as follows Set TM0n and CM0n3 match detection and rising edge of TM0CEn bit of TMC0n register Reset TM0n and CM0n0 to CM0n2 match detection The values of DTRRn are transferred to ...

Page 282: ...O0n0 to TO0n5 pins are reset is the high impedance state When the control mode is selected thereafter the following levels are output until the TM0n is started TO0n0 TO0n2 TO0n4 When low active High level When high active Low level TO0n1 TO0n3 TO0n5 When low active Low level When high active High level The active level is set with the ALVTO bit of the TOMRn register The default is low active Cauti...

Page 283: ...0n3 TO0n5 Interrupt request BFCMnx BFCMn3 CM0n3 DTMnx F F CM0nx 0000H INTCM0n3 INTCM0n3 Set by rising edge of TM0CEn bit Remarks 1 The above figure shows the timing chart when BFTE3 and BFTEN of the TMC0n register are 1 and transfer from BFCMn3 to CM0n3 or from BFCMnx to CM0nx is enabled Transfer is not performed when BFTE3 0 or BFTEN 0 2 n 0 1 3 x 0 to 2 4 t Dead time DTRRn 1 fCLK fCLK Base clock...

Page 284: ... TO0n2 output TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output TO0n2 output TO0n3 output TO0n4 output TO0n5 output 0000H CM0n2 CM0n1 CM0n0 CM0n3 CM0n2 CM0n1 CM0n0 Without dead time With dead time Remarks 1 n 0 1 2 The above figure shows an active low case Since the F F is set at the rising edge of the TM0CEn bit of the TMC0n register in the first cycle the PWM signal can be output ...

Page 285: ...e clock 5 The above figure shows an active high case When a value greater than CM0n3 is set to BFCMnx the positive phase side TO0n0 TO0n2 TO0n4 pins outputs a high level and the negative phase side TO0n1 TO0n3 TO0n5 pins continues to output a low level Since TM0n and CM0nx match does not occur the F F does not get reset This feature is effective for outputting a low level or high level width excee...

Page 286: ...TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 a b b c d a b b c Note CM0n3 CM0n3 a c CM0nx match CM0nx match CM0n3 t t t t t INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 Note F F is reset upon occurrence of match with CM0nx Remarks 1 n 0 1 2 x 0 to 2 3 b CM0n3 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case The timing at which the F F is reset is upon occurrence...

Page 287: ...0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 Interrupt request BFCMnx DTMnx F F CM0nx 0000H INTCM0n3 INTCM0n3 INTCM0n3 Set by rising edge of TM0CEn bit a Remarks 1 n 0 1 2 x 0 to 2 3 b CM0n3 4 t Dead time DTRRn 1 fCLK fCLK Base clock 5 The above figure shows an active high case If match signal INTCM0n3 for TM0n and CM0n3 and the match signal for TM0n and CM0nx conflict reset of the F F takes precede...

Page 288: ...lue Positive phase TO0n0 TO0n2 TO0n4 Negative phase TO0n1 TO0n3 TO0n5 Interrupt request BFCMnx DTMnx F F CM0nx 0000H Note INTCM0n3 INTCM0n3 INTCM0n3 a Note Set by rising edge of TM0CEn bit Remarks 1 n 0 1 2 x 0 to 2 3 t Dead time DTRRn 1 fCLK fCLK Base clock 4 The above figure shows an active high case 5 W Width between CM0n3 match and CM0nx match timer count clock If CM0nx 0000H has been set the ...

Page 289: ...36 shows the timing from write of the TM0CEn bit of the TMC0n register until the TM0n timer starts operating Figure 9 36 TM0CEn Bit Write and TM0n Timer Operation Timing Register write timing 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H fCLK TM0CEn bit write timing TM0n Caution The operation of TM0n starts 2fCLK after the register write timing Remark fCLK Base clock ...

Page 290: ...t clock fCLK 0002H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H CM0n3 TM0n INTCM0n3 INTTM0n fCLK b When count clock fCLK 4 0002H 0000H 0001H 0002H 0001H 0000H CM0n3 TM0n INTCM0n3 INTTM0n fCLK Cautions 1 INTCM0n3 is generated at the next fCLK after detection of TM0n and CM0n3 match 2 INTTM0n is generated at the next fCLK aft...

Page 291: ...000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H CM0n3 TM0n INTCM0n3 fCLK b When count clock fCLK 4 0002H 0000H 0001H 0002H 0000H 0001H CM0n3 TM0n INTCM0n3 fCLK Cautions 1 INTCM0n3 is generated at the next fCLK after detection of TM0n and CM0n3 match 2 INTCM0n3 is generated at the next fCLK after detection of TM0n and CM0n3 match even if the count clock is 1 2 1 8 1 16 or 1 3...

Page 292: ...o other than 1 1 and count operation is started the interrupt output order differs according to the setting of the STINTn bit when counting starts Figure 9 39 Interrupt Generation Timing in PWM Mode 0 Symmetric Triangular Wave PWM Mode 1 Asymmetric Triangular Wave In Case of Interrupt Culling Ratio of 1 1 a When STINTn bit 0 0004H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0...

Page 293: ...ing Ratio of 1 2 a When STINTn bit 0 0004H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 INTTM0n fCLK b When STINTn bit 1 0004H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 INTTM0n fCLK Rem...

Page 294: ...f 1 1 a When STINTn bit 0 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 fCLK b When STINTn bit 1 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 fCLK Remarks 1 n 0 1 2 fCLK Base clock ...

Page 295: ...f 1 2 a When STINTn bit 0 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 fCLK b When STINTn bit 1 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H CM0n3 TM0CEn bit TM0n INTCM0n3 fCLK Remarks 1 n 0 1 2 fCLK Base clock ...

Page 296: ... 0008H 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0002H FFFFH FFFFH FFFFH 0001H 0000H 0002H 0001H 0000H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H CM0nx TM0n DTMnx Match signal F F TO0n0 TO0n2 TO0n4 TO0n1 TO0n3 TO0n5 DTRRn fCLK CM0n3 TM0CEn bit Remarks 1 The above figure shows the timing until the compare register and the TM0n timer match and the TO0n0 to TO0n5 ou...

Page 297: ...H 0000H FFFFH FFFFH 0001H 0000H 0002H 0001H 0000H 0002H FFFFH 0001H 0000H 0006H 0007H 0008H 0009H 000AH 0000H 0001H 0002H 0003H 0004H 0005H 0006H CM0nx TM0n DTMnx Match signal F F TO0n0 TO0n2 TO0n4 TO0n1 TO0n3 TO0n5 DTRRn fCLK CM0n3 TM0CEn bit Remarks 1 The above figure shows the timing until the compare register and the TM0n timer match and the TO0n0 to TO0n5 outputs change 2 x 0 to 2 3 n 0 1 4 f...

Page 298: ...t 2 types 2 channels Compare match interrupt request 2 types 2 channels Capture request signal 2 types 2 channels The TM1n value can be latched using the valid edge of the INTP1n0 INTP1n1 pins corresponding to the capture compare register as the capture trigger Count clocks selectable through division by prescaler set the frequency of the count clock to 8 MHz or less Base clock fCLK 2 types set fC...

Page 299: ... of the pulses PWM output function In the general purpose timer mode 16 bit resolution PWM output can be output from the TO1n pin Timer clear The following timer clear operations are performed according to the mode that is used a General purpose timer mode Timer clear operation is possible upon occurrence of match with CM1n0 set value b Up down counter mode The timer clear operation can be selecte...

Page 300: ... write INTCM101 CC100 Read write INTCC100 INTP100 CC101 Read write INTCC101 INTP100 or INTP101 TM11 Read write CM110 Read write INTCM110 CM111 Read write INTCM111 CC110 Read write INTCC110 INTP110 Timer 1 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 CC111 Read write INTCC111 INTP110 or INTP111 Notes 1 When fXX 2 is selected as the base clock t...

Page 301: ...0 TM1n TM10 clear controller CC1n1 CC1n0 MSEL CMD TM1UBDn ENMD ALVT10 RLEN TM1UDFn TM1OVFn Clear TCLR SELCLK fCLK Internal bus Internal bus TCLR1n INTP1n1 TCUD1n INTP1n0 TIUD1n fXX 4 fXX 2 INTP1n0 INTCC1n0 INTP1n1Note INTCC1n1 TO1n INTCM1n0 INTCM1n1 Selector Note The INTP1n1 interrupt is the signal of the interrupt from the INTP1n1 pin or the interrupt from the INTP1n0 pin selected by the CSLn bit...

Page 302: ...tion Correct usage example Incorrect usage example TM10 read TM10 read TM11 read TM10 read TM10 read TM11 read TM11 read TM11 read 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 TM10 Address FFFFF5E0H Initial value 0000H 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 TM11 Address FFFFF600H Initial value 0000H TM1n start and stop is controlled by the TM1CEn bit of timer control register 1n TMC1n The TM1n operation c...

Page 303: ...eral purpose mode and it counts up down when the operation mode is the UDC mode The conditions for clearing the TM1n are classified as follows depending on the operation mode Table 9 5 Timer 1 TM1n Clear Conditions TUMn Register TMC1n Register Operation Mode CMD Bit MSEL Bit ENMD Bit CLR1 Bit CLR0 Bit TM1n Clear 0 Clearing not performed General purpose timer mode 0 0 1 Cleared upon match with CM1n...

Page 304: ...8 9 10 11 15 1 0 CM100 Address FFFFF5E2H Initial value 0000H 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 CM110 Address FFFFF602H Initial value 0000H 3 Compare registers 101 111 CM101 CM111 CM1n1 is a 16 bit register that always compares its value with the value of TM1n When the value of a compare register matches the value of TM1n an interrupt signal is generated The interrupt generation timing in the v...

Page 305: ...irst and the second read operation Correct usage example Incorrect usage example CC100 read CC100 read CC110 read CC100 read CC100 read CC110 read CC110 read CC110 read Remark n 0 1 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 CC100 Address FFFFF5E6H Initial value 0000H 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 CC110 Address FFFFF606H Initial value 0000H a When set as a capture register When CC1n0 is set as ...

Page 306: ...rect usage example CC101 read CC101 read CC111 read CC101 read CC101 read CC111 read CC111 read CC111 read Remark n 0 1 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 CC101 Address FFFFF5E8H Initial value 0000H 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 CC111 Address FFFFF608H Initial value 0000H a When set as a capture register When CC1n1 is set as a capture register the valid edge of either corresponding exte...

Page 307: ... of timer 1 TM1n and timer 2 TM2n This register can be read written in 8 bit or 1 bit units Caution Always set this register before using the timers 1 and 2 7 0 PRM02 6 0 5 0 4 0 3 0 2 0 1 0 0 PRM2 Address FFFFF5D8H Initial value 00H Bit Position Bit Name Function 0 PRM2 Specifies the base clock of timer 1 TM1n and timer 2 TM2n 0 fXX 4 when fXX 32 MHz 1 fXX 2 when fXX 32 MHz Remark fXX Internal sy...

Page 308: ...n count 3 TOE10 Specifies timer output TO1n enable 0 Timer output disabled 1 Timer output enabled Caution When CMD bit 1 UDC mode timer output is not performed regardless of the setting of the TOE10 bit At this time timer output consists of the negative phase level of the level set by the ALVT10 bit 2 ALVT10 Specifies active level of timer output TO1n 0 Active level is high level 1 Active level is...

Page 309: ... count operation 3 RLEN Enables disables transfer from CM1n0 to TM1n 0 Disable transfer 1 Enable transfer Cautions 1 When RLEN 1 the value set to CM1n0 is transferred to TM1n upon occurrence of TM1n underflow 2 When the CMD bit of the TUMn register 0 general purpose timer mode the RLEN bit setting becomes invalid 3 The RLEN bit is valid only in UDC mode A CMD bit of TUMn register 1 and MSEL bit 0 ...

Page 310: ...n0 set value 1 1 Don t clear 1 0 CLR1 CLR0 Cautions 1 Clearing by match of the TM1n count value and CM1n0 set value is valid only during TM1n up count operation TM1n is not cleared during TM1n down count operation 2 When the CMD bit of the TUMn register 0 general purpose timer mode the CLR1 and CLR0 bit settings are invalid 3 When the MSEL bit of the TUMn register 1 UDC mode B the CLR1 and CLR0 bi...

Page 311: ... or 1 bit units Caution Overwriting the CCRn register during TM1n operation TM1CEn bit 1 is prohibited 7 0 CCR0 6 0 5 0 4 0 3 0 2 0 1 CMS1 0 CMS0 Address FFFFF5EAH Initial value 00H 7 0 CCR1 6 0 5 0 4 0 3 0 2 0 1 CMS1 0 CMS0 Address FFFFF60AH Initial value 00H Bit Position Bit Name Function 1 CMS1 Specifies operation mode of CC1n1 0 Capture register 1 Compare register 0 CMS0 Specifies operation mo...

Page 312: ...11 TMC10 TMC11 even when timer 1 is not used and the TCUD10 INTP100 TCLR10 INTP101 TCUD11 INTP110 and TCLR11 INTP111 pins are used as INTP100 INTP101 INTP110 and INTP111 1 2 7 TESUD01 SESA10 6 TESUD00 5 CESUD01 4 CESUD00 3 IES1011 2 IES1010 1 IES1001 0 IES1000 Address FFFFF5EDH Initial value 00H TIUD10 TCUD10 TCLR10 INTP101 INTP100 7 TESUD11 SESA11 6 TESUD10 5 CESUD11 4 CESUD10 3 IES1111 2 IES1110...

Page 313: ... falling edge of TCLR1n 10 TM1n cleared status held while TCLR1n input is low level 11 TM1n cleared status held while TCLR1n input is high level Caution The set values of the CESUDn1 and CESUDn0 bits are valid only in UDC mode A Specifies valid edge of the pin INTP1n1 INTP1n0 selected by the CSLn bit of the CSL1n register IES1n11 IES1n10 Valid Edge 0 0 Falling edge 0 1 Rising edge 1 0 Setting proh...

Page 314: ...ited 3 When TM1n is in mode 4 specification of the valid edge for the TIUD1n and TCUD1n pins is invalid 7 0 PRM10 6 0 5 0 4 0 3 0 2 PRM12 1 PRM11 0 PRM10 Address FFFFF5EEH Initial value 07H 7 0 PRM11 6 0 5 0 4 0 3 0 2 PRM12 1 PRM11 0 PRM10 Address FFFFF60EH Initial value 07H Bit Position Bit Name Function Specifies the up down count operation mode during input of the clock rate when the internal c...

Page 315: ... register 1 The TM1n count sources in the UDC mode are as follows Operation Mode TM1n Operation Mode 1 Down count when TCUD1n high level Up count when TCUD1n low level Mode 2 Up count upon detection of valid edge of TIUD1n input Down count upon detection of valid edge of TCUD1n input Mode 3 Automatic judgment with TCUD1n input level upon detection of valid edge of TIUD1n input Mode 4 Automatic jud...

Page 316: ...g 0 No TM1n count underflow 1 TM1n count underflow Caution The TM1UDFn bit is cleared to 0 upon completion of read access to the STATUSn register from the CPU 1 TM1OVFn TM1n overflow flag 0 No TM1n count overflow 1 TM1n count overflow Caution The TM1OVFn bit is cleared to 0 upon completion of read access to the STATUSn register from the CPU 0 TM1UBDn Indicates the operating status of TM1n up down ...

Page 317: ...0 2 0 1 0 0 CSL0 Address FFFFF5F6H Initial value 00H Bit Position Bit Name Function 0 CSL0 Specifies capture input to CC101 0 INTP101 1 INTP100 9 CC111 capture input selection register CSL11 The CSL11 register specifies capture input that is input to TM11 CSL11 can be read written in 8 bit or 1 bit units 7 0 CSL11 6 0 5 0 4 0 3 0 2 0 1 0 0 CSL1 Address FFFFF616H Initial value 00H Bit Position Bit ...

Page 318: ...d into two modes according to the TM1n clear conditions UDC mode A TUMn register s CMD bit 1 MSEL bit 0 The TM1n clear source can be selected as only external clear input TCLR1n a match signal between the TM1n count value and the CM1n0 set value during up count operation or logical sum OR of the two signals using bits CLR1 and CLR0 of the TMC1n register TM1n can reload the value of CM1n0 upon occu...

Page 319: ...ree running operation TM1n performs full count operation from 0000H to FFFFH and after the TM1OVFn bit of the STATUSn register is set to 1 TM1n is cleared and resumes counting The free running cycle can be calculated with the following formula Free running cycle 65536 TM1n count clock rate Caution The free running operation can be achieved by setting the ENMD bit of the TMC1n register to 0 c Compa...

Page 320: ...d CC1n1 are capture compare registers Which of these registers is used is specified with capture compare control register n CCRn 2 n 0 1 The valid edge of the capture trigger is specified by signal edge selection register 1n SESA1n If both the rising edge and the falling edge are selected as the capture triggers it is possible to measure the input pulse width from external If a single edge is sele...

Page 321: ...lue of this register matches the value of TM1n the INTCM1n0 interrupt is generated Compare match is saved by hardware and TM1n is cleared at the next count clock after the match The CM1n1 register is a compare register used to set the PWM output duty Set the duty required for the PWM cycle Figure 9 47 PWM Signal Output Example When ALVT10 Bit 0 Is Set CM1n0 set value CM1n1 set value TM1n TO1n INTC...

Page 322: ...IUD1n input and both edges of TCUD1n input The UDC mode is further divided into two modes according to the TM1n clear conditions count operation is performed only with TIUD1n TCUD1n input in both modes UDC mode A TUMn register s CMD bit 1 MSEL bit 0 The TM1n clear source can be selected as only external clear input TCLR1n a match signal between the TM1n count value and the CM1n0 set value during u...

Page 323: ...ister setting i Mode 1 PRM12 bit 1 PRM11 bit 0 PRM10 bit 0 In mode 1 the following count operations are performed based on the level of the TCUD1n pin upon detection of the valid edge of the TIUD1n pin TM1n down count operation when TCUD1n pin high level TM1n up count operation when TCUD1n pin low level Figure 9 48 Mode 1 When Rising Edge Is Specified as Valid Edge of TIUD1n Pin TIUD1n TCUD1n TM1n...

Page 324: ...PRM11 bit 0 PRM10 bit 1 The count conditions in mode 2 are as follows TM1n up count upon detection of valid edge of TIUD1n pin TM1n down count upon detection of valid edge of TCUD1n pin Caution If the count clock is simultaneously input to the TIUD1n pin and the TCUD1n pin count operation is not performed and the immediately preceding value is held Figure 9 50 Mode 2 When Rising Edge Is Specified ...

Page 325: ...TM1n counts down when the valid edge is input to the TIUD1n pin If the TCUD1n pin level sampled at the valid edge input to the TIUD1n pin is high TM1n counts up when the valid edge is input to the TIUD1n pin Figure 9 51 Mode 3 When Rising Edge Is Specified as Valid Edge of TIUD1n Pin 0007H TIUD1n TCUD1n TM1n 0008H Up count Down count 0009H 000AH 0009H 0008H 0007H Remark n 0 1 Figure 9 52 Mode 3 Wh...

Page 326: ...ges of the two signals input to the TIUD1n and TCUD1n pins Therefore TM1n counts four times per cycle of an input signal 4 count Figure 9 53 Mode 4 TIUD1n TCUD1n TM1n 0004H 0003H 0006H 0005H 0008H 0007H 000AH 0009H 0008H 0009H 0006H 0007H 0005H Up count Down count Cautions 1 When mode 4 is specified as the operation mode of TM1n the valid edge specifications for pins TIUD1n and TCUD1n are not vali...

Page 327: ...e transfer operation ii Transfer operation The operations at the next count clock after the count value of TM1n becomes 0000H during TM1n count down operation are as follows In case of down count operation The data held in CM1n0 is transferred In case of up count operation The TM1n count value is incremented 1 Remarks 1 Transfer enable disable can be set with the RLEN bit of the TMC10 register 2 T...

Page 328: ...TCM1n0 INTCM1n1 INTCC1n0 Note INTCC1n1 Note is output Note This match interrupt is generated when CC1n0 and CC1n1 are set to the compare register mode iv Capture function TM1n connects two capture compare register CC1n0 CC1n1 channels When CC1n0 and CC1n1 are set to the capture register mode the value of TM1n is captured in synchronization with the corresponding capture trigger signal When the TM1...

Page 329: ...alue CM1n1 set value TM1n count value Clear TM1n not cleared if count clock counts down following match Clear TM1n not cleared if count clock counts up following match Remark n 0 1 ii Compare function TM1n connects two compare register CM1n0 CM1n1 channels and two capture compare register CC1n0 CC1n1 channels When the TM1n count value and the set value of one of the compare registers match a match...

Page 330: ...tion upon Match with CM1n0 During TM1n Up Count Operation Count clock rising edge set as valid edge CM1n0 FFFEH Clear TM1n Not clear TM1n TM1n FFFFH 0000H FFFEH 0001H FFFDH FFFFH Up count Up count Down count Remarks 1 n 0 1 2 Items between parentheses in the above figure apply to down count operation Figure 9 57 Clear Operation upon Match with CM1n1 During TM1n Down Count Operation Count clock ris...

Page 331: ...pon Compare Match Count clock rising edge set as valid edge CM1n0 FFFEH TM1n FFFFH 0000H FFFEH 0001H FFFDH FFFFH Up count Up count Down count Clear TM1n Not clear TM1n Caution The operations at the next count clock after the count value of TM1n and the CM1n0 set value match are as follows In case of up count Clear operation is performed In case of down count Clear operation is not performed Remark...

Page 332: ... set as valid edge CM1n0 0001H Transfer operation is performed Transfer operation is not performed TM1n 0000H FFFFH 0001H FFFEH 0002H FFFFH Down count Down count Up count Caution The count operations after the TM1n count value becomes 0000H are as follows In case of down count Transfer operation is performed In case of up count Transfer operation is not performed Remarks 1 n 0 1 2 Items between pa...

Page 333: ... Purpose Timer Mode and Count Clock Set to fCLK 2 Count clock fCLK CM1n1 0007H TM1n Internal match signal INTCM1n1 0008H 000BH 0009H 0009H 000AH Remarks 1 n 0 1 2 fCLK Base clock An interrupt signal such as illustrated in Figure 9 60 is output at the next count following match of the TM1n count value and the set value of a corresponding compare register 5 TM1UBDn flag bit 0 of STATUSn register ope...

Page 334: ...r counter TM20 TM21 2 channels Bit length Timer 2 registers TM20 TM21 16 bits During cascade operation 32 bits higher 16 bits TM21 lower 16 bits TM20 Capture compare register In 16 bit mode 6 In 32 bit mode 4 capture mode only Count clock division selectable by prescaler set the frequency of the count clock to 8 MHz or less Base clock fCLK 2 types set fCLK to 16 MHz or less fXX 2 and fXX 4 can be ...

Page 335: ...nput Note 2 Timer counter clear operation can be performed with the TCLR2 pin input signal Up down count control Notes 3 5 with external pin input Note 2 Up down count operation in the compare mode can be controlled with the TCLR2 pin input signal Output delay operation A clock synchronized output delay can be added to the output signal of pins TO21 to TO24 This is effective as an EMI countermeasu...

Page 336: ...d write INTCC23 INTP23 INTP22 Buffer Note 4 CVSE40 Read write INTCC24 INTP24 INTP21 Buffer Note 4 CVSE50 Read write INTCC25 INTP25 INTP20 CVPE40 Read INTCC24 INTP24 INTP21 Note 4 CVPE30 Read INTCC23 INTP23 INTP22 Note 4 CVPE20 Read INTCC22 INTP22 INTP23 Note 4 Timer 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 CVPE10 Read INTCC21 INTP21 INTP...

Page 337: ...en n 3 4 y y 1 2 when m 12 y 3 4 when m 34 The following shows the output level sources during timer output Table 9 10 Output Level Sources During Timer Output TO2n Toggle Mode 0 OTMEn1 OTMEn0 00 Toggle Mode 1 OTMEn1 OTMEn0 01 Toggle Mode 2 OTMEn1 OTMEn0 10 Toggle Mode 3 OTMEn1 OTMEn0 11 Trigger Compare match of sub channel n Compare match of sub channel n TM20 0 Compare match of sub channel n TM2...

Page 338: ...D2B ED2 Sub channel 3 CVSE30 16 bit CVPE30 16 bit S T RA RB RN Output circuit 4 CVSE00 16 bit TM20 16 bit INTCC20 INTCC21 INTCC22 INTCC23 INTCC24 INTCC25 INTTM20 TO21 TO22 TO23 TO24 INTTM21 CVSE50 16 bit TM21 16 bit TINE5 edge selection TINE4 edge selection TINE3 edge selection TINE2 edge selection TINE1 edge selection TINE0 edge selection Input filter Input filter Input filter Input filter Input ...

Page 339: ...ch signal input sub channel 0 5 RA TM20 zero count signal input reset signal of output circuit RB TM21 zero count signal input reset signal of output circuit RELOAD2A TM20 zero count signal input generated when TM20 0000H RELOAD2B TM21 zero count signal input generated when TM21 0000H RN Sub channel x interrupt signal input reset signal of output circuit S T Sub channel x interrupt signal input se...

Page 340: ...le can be controlled with external pin TCLR2 Counter up down and clear operation control method can be set by software Stop upon occurrence of count value 0 and count operation start stop can be controlled by software 2 Timer 2 sub channel 0 capture compare register CVSE00 The CVSE00 register is a 16 bit capture compare register of sub channel 0 In the capture register mode it captures the TM20 co...

Page 341: ...de value of TB1En TB0En bits of CMSEm0 register 11B this register captures the contents of TM21 higher 16 bits This register is read only in 16 bit units Caution When the BFEEn bit 1 a compare match occurs on starting the timer in the compare register mode because the values of both the TM2x and CVPEn0 registers are 0 after reset TM2x timer counter selected by TB1En and TB0En bits n 1 to 4 After t...

Page 342: ...hen the BFEEn bit 1 a compare match occurs on starting the timer in the compare register mode because the values of both the TM2x and CVPEn0 registers are 0 after reset TM2x timer counter selected by TB1En and TB0En bits n 1 to 4 After that the value of the sub register CVSEn0 is written to the main register CVPEn0 14 13 12 2 3 4 5 6 7 8 9 10 11 15 1 0 CVSE10 Address FFFFF650H Initial value 0000H ...

Page 343: ...0 STOPTE0 The STOPTE0 register is used to stop the operation clock input to timer 2 This register can be read written in 16 bit units When the higher 8 bits of the STOPTE0 register are used as the STOPTE0H register and the lower 8 bits are used as the STOPTE0L register the STOPTE0H register can be read written in 8 bit or 1 bit units and the STOPTE0L register is read only in 8 bit units Cautions 1...

Page 344: ... Address FFFFF642H Initial value 0000H Bit Position Bit Name Function Specifies the valid edge of the TM2n internal count clock TCOUNTEn signal TESnE1 TESnE0 Valid Edge 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges 11 10 9 8 TESnE1 TESnE0 Specifies the valid edge of the TM2n external clear input TCLR2 CESE1 CESE0 Valid Edge 0 0 Falling edge 0 1 Rising ed...

Page 345: ... used as the SESE0H register and the lower 8 bits are used as the SESE0L register they can be read written in 8 bit or 1 bit units 14 0 13 0 12 0 2 IESE10 3 IESE11 4 IESE20 5 IESE21 6 IESE30 7 IESE31 8 IESE40 9 IESE41 10 IESE50 11 IESE51 15 0 1 IESE01 0 IESE00 SESE0 Address FFFFF644H Initial value 0000H Bit Position Bit Name Function Specifies the valid edge of external capture signal input TINEn ...

Page 346: ...ared until the external clock TI2 is input 3 The ECREn bit and the ECEEn bit cannot be set to 1 4 If the ECEEn bit is set to 1 and the ECREn bit is set to 0 a down count operation cannot be performed 5 When UDSEn1 UDSEn0 01 and OSTEn 1 the counter does not count up when the counter value is 0 Therefore when the counter value is 0 set OSTEn 0 and after the value of the counter ceases to be 0 set OS...

Page 347: ...TCOUNTE1 is selected as the count of TM21 When CASE1 1 TCOUNTE0 and the TM20 overflow signal are selected as the count of TM21 14 6 CLREn Specifies software clear for TM2n 0 TM2n operation continued 1 TM2n count value cleared 0 Caution Do not perform the software clear and hardware clear operations simultaneously 13 5 CEEn Specifies TM2n count operation enable disable 0 Count operation stopped 1 C...

Page 348: ...STE1n bit 1 TM2n count is stopped when the count value is 0 TM2n counts up except when the UDSEn1 UDSEn0 bits 10 The count direction when the UDSEn1 and UDSEn0 bits 10 is determined by the value of ECLR Specifies TM2n up down count UDSEn1 UDSEn0 Count 0 0 Perform only up count Clear TM2n with compare match signal 0 1 Count up after TM2n has become 0 and count down after a compare match occurs for ...

Page 349: ... the TO2n pin output 0 Active level is high level 1 Active level is low level Specifies toggle mode OTMEn1 OTMEn0 Toggle Mode 0 0 Toggle mode 0 Reverse output level of TO2n output every time a sub channel n compare match occurs 0 1 Toggle mode 1 Upon sub channel n compare match set TO2n output to active level and when TM20 is 0 set TO2n output to inactive level 1 0 Toggle mode 2 Upon sub channel n...

Page 350: ...nel n capture compare register 0 ED1 and ED2 signal inputs ignored nothing is done even if these signals are input 1 Operation caused by ED1 and ED2 signal inputs enabled 11 3 LNKEn Specifies capture event signal input from edge selection to ED1 or ED2 0 In capture register mode select ED1 signal input In compare register mode LNKEn bit has no influence 1 In capture register mode select ED2 signal...

Page 351: ...nter selected by TB1En and TB0En bits n 1 to 4 After that the value of the sub register CVSEn0 is written to the main register CVPEn0 Remarks 1 The operations in the capture register mode and compare register mode when the sub channel n sub capture compare register CVSEn0 is not used as a buffer are shown below In capture register mode The CPU can read both the master register CVPEn0 and slave reg...

Page 352: ...ompare register mode the data of the CVSEn0 register is transferred to the CVPEn0 register when the TM2x count value becomes 0 TM2x timer counter selected with bits TB1En TB0En 10 2 CCSEn Selects capture compare register operation mode 0 Capture register mode 1 Compare register mode Sets sub channel n timer counter TB1En TB0En Sub Channel n Timer Counter 0 0 Don t use sub channel n 0 1 Set TM20 to...

Page 353: ...er selected by TB1En and TB0En bits n 1 to 4 After that the value of the sub register CVSEn0 is written to the main register CVPEn0 Remarks 1 The operations in the capture register mode and compare register mode when the sub channel n sub capture compare register CVSEn0 is not used as a buffer are shown below In capture register mode The CPU can read both the master register CVPEn0 and slave regis...

Page 354: ...ompare register mode the data of the CVSEn0 register is transferred to the CVPEn0 register when the TM2x count value becomes 0 TM2x timer counter selected with bits TB1En TB0En 10 2 CCSEn Selects capture compare register operation mode 0 Capture register mode 1 Compare register mode Sets sub channel n timer counter TB1En TB0En Sub Channel n Timer Counter 0 0 Don t use sub channel n 0 1 Set TM20 to...

Page 355: ...nly bits 14 0 13 0 12 0 2 ECFE0 3 OVFE0 4 0 5 0 6 0 7 0 8 UDFE1 9 RSFE1 10 ECFE1 11 OVFE1 15 0 1 RSFE0 0 UDFE0 TBSTATE0 Address FFFFF664H Initial value 0101H Bit Position Bit Name Function 11 3 OVFEn Indicates TM2n overflow status 0 No overflow 1 Overflow Caution If write access to the TBSTATE0 register is performed while overflow is not detected the OVFEn bit is cleared 0 10 2 ECFEn Indicates the...

Page 356: ...ration has occurred In compare register mode No compare match has occurred 1 In capture register mode At least one capture operation has occurred In compare register mode At least one compare match has occurred Caution The CEFEn bit can be cleared 0 by performing write access to the CCSTATE0 register while no capture operation or compare match occurs When bit manipulation is performed for the CEFE...

Page 357: ...2 3 0 4 ODLE20 5 ODLE21 6 ODLE22 7 0 8 ODLE30 9 ODLE31 10 ODLE32 11 0 15 0 1 ODLE11 0 ODLE10 ODELE0 Address FFFFF668H Initial value 0000H Bit Position Bit Name Function Specifies output delay operation ODLEn2 ODLEn1 ODLEn0 Set Output Delay Operation 0 0 0 Don t perform output delay operation 0 0 1 Set output delay of 1 system clock 0 1 0 Set output delay of 2 system clocks 0 1 1 Set output delay o...

Page 358: ... 8 0 9 0 10 0 11 0 15 0 1 SEVE1 0 SEVE0 CSCE0 Address FFFFF66AH Initial value 0000H Bit Position Bit Name Function 5 to 0 SEVEn Specifies capture operation by software in capture register mode 0 Continue normal operation 1 Perform capture operation Cautions 1 The SEVEn bit ignores the settings of the EEVEn and the LNKEn bits of the CMSEm0 register 2 The SEVEn bit is automatically cleared 0 at the ...

Page 359: ... The set values of the TESnE1 TESnE0 bits and the CESE1 CESE0 bits of the CSE0 register and the IESEx1 IESEx0 bits of the SESE0 register are shown Remarks 1 fCLK Base clock 2 CT TM2n count signal input in the 16 bit mode ECLR External control signal input from TCLR2 input ED1 ED2 Capture event signal input from edge selector MUXTB0 TM20 multiplex signal TCOUNTEn Timer 2 count enable signal input T...

Page 360: ...s 00B ECEEn Bit 0 ECREn Bit 0 CLREn Bit 0 CASE1 Bit 0 fCLK FFFDH Stop FFFEH FFFFH 0000H 1234H 1235H 0000H Stop CT CNT RNote 2 INTTM2n output CNT 0 OSTEn bitNote 1 CEEn bitNote 1 Notes 1 Bits OSTE CEE of TCRE0 register 2 Can control TM20 TM21 clear by sub channel 0 5 compare match or count direction Remarks 1 fCLK Base clock 2 CNT Count value of timer 2 CT TM2n count signal input in 16 bit mode R C...

Page 361: ...s UDSEn1 UDSEn0 Bits 00B OSTEn Bit 0 CEEn Bit 1 CASE1 Bit 0 fCLK ECREn bitNote CLREn bitNote ECLR CNT CT ECEEn bitNote 1234H 1235H 0000H 0001H 0000H Note Bits ECEEn ECREn CLREn of TCRE0 register Remarks 1 fCLK Base clock 2 CNT Count value of timer 2 CT TM2n count signal input in 16 bit mode ECLR External control signal input from TCLR2 pin input 3 n 0 1 ...

Page 362: ...n output CNT 0 CT UDSEn1 UDSEn0 bitsNote 1 FFFFH 0000H 0001H don t care 01B 10B 0002H 0001H 0000H 0001H 0002H 0003H 0002H FFFEH Notes 1 UDSEn1 UDSEn0 bits of TCRE0 register 2 Can control TM20 TM21 clear by sub channel 0 5 compare match or count direction Remarks 1 fCLK Base clock 2 CNT Count value of timer 2 CT TM2n count signal input in 16 bit mode ECLR External control signal input from TCLR2 pi...

Page 363: ...1 Bit 1 fCLK CNT TB0 CNT TB1 CTC CASCNote TB1 FFFBH FFFCH FFFDH FFFEH FFFFH 0000H 0001H 0002H 0003H 0004H 1234H 1235H Note If in the 32 bit mode CASC CNT MAX for TM20 is input to TM21 and the CTC rising edge is detected TM21 performs count operation Remarks 1 fCLK Base clock 2 CASC TM21 count signal input in 32 bit mode CNT Count value of timer 2 CTC TM21 count signal input in 32 bit mode TB0 Coun...

Page 364: ...he count value of TM21 is output to sub channels 1 to 4 at the rising edge of MUXTB1 Figure 9 68 shows the block diagram of the timer 2 multiplex count generator and Figure 9 69 shows the multiplex count timing Figure 9 68 Block Diagram of Timer 2 Multiplex Count Generator MUXTB0 to sub channel m capture compare register MUXTB1 to sub channel m capture compare register MUXCNT to sub channel m capt...

Page 365: ...1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 0001H FFFEH 1234H FFFFH FFFFH FFFFH 1234H 1234H 0000H 1234H 1235H 0000H 1235H 0000H 0001H 0001H 0001H 1235H 1235H 1235H Remarks 1 fCLK Base clock 2 CNT Count value of timer 2 MUXTB0 MUXTB1 Multiplex signal of TM20 TM21 MUXCNT Count value to sub channel m m 1 to 4 TB0 Count value of TM20 TB1 Count value of TM21 Figures 9 70 to 9 75 show the operation of the capture...

Page 366: ...1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 1 5 6 2 3 4 7 8 5 9 10 6 11 7 8 9 10 12 13 14 Note 2 Note 2 Undefined Undefined 2 4 13 11 Notes 1 Bits TB0Ey TB1Ey of CMSEx register 2 If an event occurs in this timing it is ignored Remarks 1 fCLK Base clock 2 CAPTURE_P Capture trigger signal of main capture register CAPTURE_S Capture trigger signal of sub capture register ED1 ED2 Capt...

Page 367: ... least twice at the start of operation and read the CVPEm0 register Also read the CVPEm0 register after performing capture at least once 2 Write operation to the CVPEn0 register is not performed at these signal inputs because the CVSEm0 register operates as a buffer 3 After this timing write operation from the CVSEm0 register to the CVPEm0 register is enabled Remarks 1 fCLK Base clock 2 BUFFER Tim...

Page 368: ...1235H 0000H 1235H 0000H 0001H 0001H 0001H 1235H 1235H 1235H Note 2 Note 3 Notes 1 TM21 performs count operation when in the 32 bit mode CASC CNT MAX for TM20 is input to TM21 and the rising edge of CTC is detected 2 If an event occurs during this timing it is ignored 3 CPU read access is not performed in this timing wait status Remarks 1 fCLK Base clock 2 CAPTURE_P Capture trigger signal of main c...

Page 369: ...1 TB0 TB1 TB0 TB1 5 1 6 2 3 4 7 8 5 9 10 6 11 7 8 9 10 12 13 14 Cleared by timer Set by software Event detection by EEVEy bit prohibited L Notes 1 EEVEy bit of CMSEx0 register 2 SEVEy bit of CSCE0 register Remarks 1 fCLK Base clock 2 BUFFER Timing of write operation from CVSEm0 register to CVPEm0 register CAPTURE_P Capture trigger signal of main capture register CAPTURE_S Capture trigger signal of...

Page 370: ... 8 9 10 6 7 8 2 2 9 9 8 8 Note 3 Note 3 Note 3 Note 3 Note 2 Notes 1 TB1Ey TB0Ey bits of CMSEx0 register 2 No interrupt is generated due to compare match with counter differing from TB1Ey TB0Ey bit settings 3 INTCC2m is generated to match the cycle from rising edge to falling edge of MUXTB0 Remarks 1 fCLK Base clock 2 MUXCNT Count value to sub channel m MUXTB0 MUXTB1 Multiplex signal of TM20 TM21 ...

Page 371: ...B1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 5 1 6 2 3 4 7 8 5 9 10 6 11 7 0 1 2 12 13 14 4 4 7 1 7 1 Note LNKEy bit of CMSEx0 register Remarks 1 fCLK Base clock 2 MUXCNT Count value to sub channel m MUXTB0 MUXTB1 Multiplex signal of TM20 TM21 RELOAD1 Compare match signal RELOAD2A Zero count signal input of TM20 occurs when TM20 0000H RELOAD_PRIMARY Timing of write operation from CVSEm0 register to ...

Page 372: ...SE050 Register s CCSEy Bit 0 EEVEy Bit 1 and CSCE0 Register s SEVEy Bit 0 fCLK ED1 ED2 CAPTURE_S READ_ENABLE_S CVSEy0 register CNT LNKEyNote 1 1 2 3 4 5 6 7 8 9 10 0 Note 2 Note 2 Undefined 2 6 9 Notes 1 LNKEy bit of CMSE050 register 2 If an event occurs in this timing it is ignored Remarks 1 fCLK Base clock 2 CNT Count value of timer 2 CAPTURE_S Capture trigger signal of sub capture register ED1 ...

Page 373: ...SEy0 register MATCH RNote 1 INTCC20 INTCC25 output CNT CPU write C C 1 2 2 3 4 4 5 6 7 8 8 9 10 0 Note 2 Note 3 Note 2 Note 2 Note 3 Note 3 Notes 1 Can control TM20 TM21 clear by sub channel 0 5 compare match or count direction 2 When MATCH signal occurs the same waveform as the MATCH signal is generated 3 The pulse width is always 1 clock Remarks 1 fCLK Base clock 2 CNT Count value of timer 2 MAT...

Page 374: ... Bits 0 fCLK RA RB RN TO2n timer output ALVEn bit 0Note 2 TO2n timer output ALVEn bit 1Note 2 OTMEn1 OTMEn0 bitsNote 1 S T 00B 01B Notes 1 OTMEn1 OTMEn0 bits of OCTLE0 register 2 ALVEn bit of OCTLE0 register Remarks 1 fCLK Base clock 2 RA Zero count signal input of TM20 output circuit reset signal RB Zero count signal input of TM21 output circuit reset signal RN Interrupt signal input of sub chann...

Page 375: ...VEn bit of OCTLE0 register Remarks 1 fCLK Base clock 2 RA Zero count signal input of TM20 output circuit reset signal RB Zero count signal input of TM21 output circuit reset signal RN Interrupt signal input of sub channel n output circuit reset signal S T Interrupt signal input of sub channel n output circuit set signal 3 n 1 to 4 Figure 9 80 Signal Output Operation During Software Control When OC...

Page 376: ...J3V0UD Figure 9 81 Signal Output Operation During Delay Output Operation When OCTLE0 Register s OTMEn1 OTMEn0 Bits 0 ALVEn 0 SWFEn Bit 0 fCLK TO2n timer output ODELEn2 to ODELEn0 bitsNote S T 5 2 Note ODELEn2 to ODELEn0 bits of OCTLE0 register Remarks 1 fCLK Base clock 2 n 1 to 4 ...

Page 377: ...k fCLK Division Ratio fXX Selected fXX 2 Selected 1 2 fXX 2 fXX 4 1 4 fXX 4 fXX 8 1 8 fXX 8 fXX 16 1 16 fXX 16 fXX 32 1 32 fXX 32 fXX 64 1 64 fXX 64 fXX 128 1 128 fXX 128 fXX 256 1 256 fXX 256 fXX 512 Interrupt request sources Capture compare match interrupt requests 2 sources In case of capture register INTCC3n generated by INTP3n input In case of compare register INTCC3n generated by CC3n match ...

Page 378: ...2 CC31 Read write INTC31 INTP31 TO3 R Notes 1 When fXX is selected as the base clock fCLK of TM3 2 When fXX 2 is selected as the base clock fCLK of TM3 Remark fXX Internal system clock S R Set Reset Figure 9 82 shows the block diagram of timer 3 Figure 9 82 Block Diagram of Timer 3 RNote Q S Q TM3 16 bit CC30 CC31 INTTM3 INTCC30 INTP31 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 fXX 2 TI3 TCLR3 INTP30 ...

Page 379: ...ctual value Figure 9 83 Timer 3 TM3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TM3 FFFFF680H 0000H Address Initial value 0 TM3 performs the count up operations of an internal count clock or external count clock Timer starting and stopping are controlled by the TM3CE bit of timer control register 30 TMC30 The internal or external count clock is selected by the ETI bit of timer control register 31 TMC31 a ...

Page 380: ...6 fCLK 32 fCLK 64 fCLK 128 and fCLK 256 by the TMC30 register fCLK base clock An overflow interrupt can be generated if the timer overflows Also the timer can be stopped following an overflow by setting the OST bit of the TMC31 register to 1 Caution The count clock cannot be changed while the timer is operating The conditions when the TM3 register becomes 0000H are shown below i Asynchronous reset...

Page 381: ... these registers to capture registers CMS1 and CMS0 of TMC31 0 When these registers are set to capture registers the valid edges of the corresponding external interrupt signals INTP30 and INTP31 are detected as capture triggers The timer TM3 is synchronized with the capture trigger and the value of TM3 is latched in the CC30 and CC31 registers capture operation The valid edge of the INTP30 pin is ...

Page 382: ...set synchronized with the generation of a match signal The interrupt selection source differs according to the function of the selected register Cautions 1 To write to capture compare registers 30 and 31 CC30 CC31 always set the TM3CAE bit to 1 first When the TM3CAE bit is 0 even if writing to registers CC30 and CC31 the data that is written will be invalid because the reset is asynchronous 2 Perf...

Page 383: ...fCLK of timer 3 TM3 This register can be read written in 8 bit or 1 bit units Cautions 1 Always set this register before using the timer 2 Set fCLK to 32 MHz or less 7 0 PRM03 6 0 5 0 4 0 3 0 2 0 1 0 0 PRM3 Address FFFFF690H Initial value 00H Bit Position Bit Name Function 0 PRM3 Specifies the base clock fCLK of timer 3 TM3 0 fXX 2 when fXX 32 MHz 1 fXX when fXX 32 MHz Remark fXX Internal system c...

Page 384: ...al value 00H Bit Position Bit Name Function 7 TM3OVF Flag that indicates TM3 overflow 0 No overflow 1 Overflow The TM3OVF bit becomes 1 when TM3 changes from FFFFH to 0000H An overflow interrupt request INTTM3 is generated at the same time However if CC30 is set to the compare mode CMS0 bit of the TMC31 register 1 and match clear during comparison of TM3 and CC30 is enabled CCLR bit of TMC31 regis...

Page 385: ... clock 1 TM3CE Controls the operation of TM3 0 Disable count timer stopped at 0000H and does not operate 1 Perform count operation Caution If TM3CE 0 the external pulse output TO3 becomes inactive level the active level of TO3 output is set with the ALV bit of the TMC31 register 0 TM3CAE Controls the internal count clock 0 Asynchronously reset entire TM3 unit Stop base clock supply to TM3 unit 1 S...

Page 386: ...will not malfunction even if a glitch is generated or make sure that the ENT1 bit and the ALV bit do not change at the same time 3 TO3 output remains unchanged by external interrupt signals INTP30 INTP31 When using the TO3 signal set the capture compare register to the compare register CMS1 CMS0 bits of TMC31 register 1 Remarks 1 A reset takes precedence for the flip flop of the TO3 output 2 When ...

Page 387: ...output is enabled until a match signal is generated Caution If either CC30 or CC31 is specified as a capture register the ENT1 bit must be set to 0 5 ALV Specifies active level of external pulse output TO3 0 Active level is low level 1 Active level is high level Caution The initial value of the ALV bit is 1 4 ETI Switches count clock between external clock and internal clock 0 Specifies input cloc...

Page 388: ...f SESC register during timer operation If they are to be changed they must be changed after setting the TM3CE bit of the TMC30 register to 0 If the SESC register is overwritten during timer operation the operation is not guaranteed 7 TES31 SESC 6 TES30 5 CES31 4 CES30 3 IES311 2 IES310 1 IES301 0 IES300 Address FFFFF689H Initial value 00H TI3 TCLR3 INTP31 INTP30 Bit Position Bit Name Function 7 6 ...

Page 389: ... timer output signal TO3 can be set or reset Also a capture operation that holds the TM3 count value in the CC30 or CC31 register is performed synchronized with the valid edge that was detected from the external interrupt request input pin as an external trigger The capture value is held until the next capture trigger is generated Caution If the INTP30 TI3 TCLR3 pin is used as TI3 or TCLR3 either ...

Page 390: ...m FFFFH to 0000H Also the overflow interrupt INTTM3 is not generated When the TM3 register is changed from FFFFH to 0000H because the TM3CE bit changes from 1 to 0 the TM3 register is considered to be cleared but the TM3OVF bit is not set 1 and no INTTM3 interrupt is generated Also timer operation can be stopped after an overflow by setting the OST bit of the TMC31 register to 1 When the timer is ...

Page 391: ...P31 is used as an external trigger capture trigger The TM3 count value during counting is captured and held in the capture register synchronized with that capture trigger signal The capture register value is held until the next capture trigger is generated Also an interrupt request INTCC30 or INTCC31 is generated by INTP30 or INTP31 signal input The valid edge of the capture trigger is set by vali...

Page 392: ...2 User s Manual U14492EJ3V0UD Figure 9 87 TM3 Capture Operation Example When Both Edges Are Specified TM3 Count start TM3CE 1 Overflow TM3OVF 1 D0 D1 D2 D0 D1 D2 Interrupt request INTP31 TM3 count values Capture register CC31 Remark D0 to D2 TM3 count values ...

Page 393: ...h signal causes the timer output pin TO3 to change and an interrupt request signal INTCC30 INTCC31 to be generated at the same time If the CC30 or CC31 register is set to 0000H the 0000H after the TM3 register counts up from FFFFH to 0000H is judged as a match In this case the value of the TM3 register is cleared to 0 at the next count timing but 0000H is not judged as a match at that time 0000H w...

Page 394: ...3V0UD Figure 9 88 Compare Operation Example 2 2 b If CCLR bit 1 and CC30 is 0000H 0001H TM3 Count up 0000H 0000H 0000H FFFFH Compare register CC30 INTTM3 Match detection INTCC30 Remark The match is detected immediately after the count up and the match detection signal is generated ...

Page 395: ... output level of the TO3 pin is reset The output level of the TO3 pin can be specified by the TMC31 register Table 9 13 TO3 Output Control TO3 Output ENT1 ALV External Pulse Output Output Level 0 0 Disable High level 0 1 Disable Low level 1 0 Enable When the CC30 register is matched Low level When the CC31 register is matched High level 1 1 Enable When the CC30 register is matched High level When ...

Page 396: ...ting value of the CC30 register the TM3 register is cleared 0000H and an interrupt request signal INTCC30 is generated at the same time that the count operation resumes Figure 9 90 Contents of Register Settings When Timer 3 Is Used as Interval Timer Supply input clocks to internal units Enable count operation 0 0 1 0 1 0 1 1 0 1 0 1 1 OST ENT1 ALV ETI CCLR CMS1 CMS0 0 1 0 1 0 1 0 1 0 0 1 1 TM3OVF ...

Page 397: ...val Timer Operation Timing Example Count start 0001H 0000H 0001H 0000H 0001H p p p p p p p 0000H Interval time Interval time Interval time Count clock t TM3 register CC30 register INTCC30 interrupt Clear Clear Remark p Setting value of CC30 register 0000H to FFFFH t Count clock cycle Interval time p 1 t ...

Page 398: ...0000H and continues counting This enables a PWM of the frequency determined by the setting of the CS2 to CS0 bits of the TMC30 register to be output When the setting value of the CC30 register and the setting value of the CC31 register are the same the TO3 output remains inactive and does not change The active level of TO3 output can be set by the ALV bit of the TMC31 register Figure 9 92 Contents...

Page 399: ...000H FFFFH p p p p p p q q q q q q q p Count clock TM3 register CC30 register CC31 register INTCC30 interrupt INTCC31 interrupt TO3 output t Remarks 1 p Setting value of CC30 register 0000H to FFFFH q Setting value of CC31 register 0000H to FFFFH p q t Count clock cycle PWM cycle 65536 t q p 65536 2 In this example the active level of TO3 output is set to high level Duty ...

Page 400: ...ng the difference between the TM3 register s count value Dx that was captured in the CC30 register according to the x th valid edge input of the INTP30 pin and the TM3 register s count value D x 1 that was captured in the CC30 register according to the x 1 th valid edge input of the INTP30 pin and multiplying the value of this difference by the cycle of the clock control signal The cycle of signal...

Page 401: ... D3 D2 D1 D0 D1 D0 t D3 D2 t 10000H D1 D2 tNote Count clock TM3 register INTP30 input CC30 register INTCC30 interrupt INTTM3 interrupt No overflow Overflow occurs No overflow Clear Count start Note When an overflow occurs once Remarks 1 D0 to D3 TM3 register count values t Count clock cycle 2 In this example the valid edge of INTP30 input has been set to both edges rising and falling ...

Page 402: ...M3 first set 1 the TM3CAE bit 5 The analog noise elimination time two cycles of the input clock are required to detect a valid edge of the external interrupt input INTP30 or INTP31 and external clock input TI3 Therefore edge detection will not be performed normally for changes that are less than the analog noise elimination time two cycles of the input clock For the analog noise elimination refer ...

Page 403: ...he frequency of the count clock to 16 MHz or less Base clock fCLK 1 type set fCLK to 32 MHz or less fXX 2 Prescaler division ratio The following division ratios can be selected according to the base clock fCLK Division Ratio Base Clock fCLK 1 2 fXX 4 1 4 fXX 8 1 8 fXX 16 1 16 fXX 32 1 32 fXX 64 1 64 fXX 128 1 128 fXX 256 1 256 fXX 512 Interrupt request source 1 Compare match interrupt INTCM4 gener...

Page 404: ...apture Trigger Timer Output S R Other Functions TM4 Read Timer 4 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 CM4 Read write INTCM4 Remark fXX Internal system clock S R Set Reset Figure 9 96 shows the block diagram of timer 4 Figure 9 96 Block Diagram of Timer 4 TM4 16 bit CM4 INTCM4 1 2 1 4 1 8 1 16 1 32 1 64 1 128 1 256 fXX 2 Clear start fCLK Remark fCLK Base clock 32 MHz MAX fXX Int...

Page 405: ...ter Overflow Cautions 1 If the TM4CAE0 bit of the TMC4 register is cleared 0 a reset is performed asynchronously 2 If the TM4CE0 bit of the TMC4 register is cleared 0 a reset is performed synchronized with the internal clock Similarly a synchronized reset is performed after a match with the CM4 register and after an overflow 3 The count clock must not be changed during a timer operation If it is t...

Page 406: ...When a read operation to a CM4 register is performed data in the master side is read out CM4 can be read written in 16 bit units Cautions 1 A write operation to a CM4 register requires 4 clocks until the value that was set in the CM4 register is transferred to internal units When writing continuously to the CM4 register be sure to reserve a time interval of at least 4 clocks 2 The CM4 register can...

Page 407: ... 9 97 Example of Timing During TM4 Operation a When TM4 CM4 TM4 TM4CAE0 TM4CE0 CM4 INTCM4 M N N N Remark M TM4 value when overwritten N CM4 value when overwritten M N b When TM4 CM4 TM4 TM4CAE0 TM4CE0 CM4 INTCM4 M FFFFH N N N Remark M TM4 value when overwritten N CM4 value when overwritten M N ...

Page 408: ... timer operation If they are to be changed they must be changed after setting the TM4CE0 bit to 0 If the CS2 to CS0 bits are overwritten during timer operation the operation is not guaranteed 1 TM4CE0 Controls the operation of TM4 0 Disable count timer stopped at 0000H and does not operate 1 Perform count operation Caution TM4CE0 bit is not cleared even if a match is detected by the compare operat...

Page 409: ...rupt causes TM4 to be cleared 0 at the next count timing This function enables timer 4 to be used as an interval timer CM4 can also be set to 0 In this case when an overflow occurs and TM4 becomes 0 a match is detected and INTCM4 is generated Although the TM4 value is cleared 0 at the next count timing INTCM4 is not generated according to this match Figure 9 98 TM4 Compare Operation Example 1 2 a ...

Page 410: ...LSE UNIT 410 User s Manual U14492EJ3V0UD Figure 9 98 TM4 Compare Operation Example 2 2 b When CM4 is set to 0 1 0 0 0 FFFFH Overflow TM4 Count clock CM4 TM4 clear Match detection INTCM4 Count up Clear Remark Interval time FFFFH 2 Count clock cycle ...

Page 411: ...rnal units When a count operation begins the count cycle from 0000H to 0001H differs from subsequent count cycles 3 To initialize the TM4 register status and start counting again clear 0 the TM4CE0 bit and then set 1 the TM4CE0 bit after an interval of 4 clocks has elapsed 4 Up to 4 clocks are required until the value that was set in the CM4 register is transferred to internal units When writing c...

Page 412: ...n Function 9 6 1 Overview The V850E IA1 provides a function to connect timer 1 and timer 2 Figure 9 99 Block Diagram of Timer Connection Function Timer 2 Timer 1 CVSE10 CVPE10 CVSE20 CVPE20 Capture 0 Capture 1 TMIC0 TMIC1 TMIC2 TMIC3 TMIC0 register INTCM1 INTCM0 INTCM101 INTCM100 Timer connection selector ...

Page 413: ...nal to CVSE20 CVPE20 registers 0 Don t input INTCM101 signal to CVSE20 CVPE20 registers 1 Input INTCM101 signal to CVSE20 CVPE20 registers 2 TMIC2 Enables disables input of INTCM100 signal to CVSE20 CVPE20 registers 0 Don t input INTCM100 signal to CVSE20 CVPE20 registers 1 Input INTCM100 signal to CVSE20 CVPE20 registers 1 TMIC1 Enables disables input of INTCM101 signal to CVSE10 CVPE10 registers...

Page 414: ...oller 1 channel Remark For details about the FCAN controller refer to CHAPTER 11 FCAN CONTROLLER UART0 to UART2 whereby one byte of serial data is transmitted received following a start bit support full duplex communication In the UART1 and UART2 interfaces one higher bit is added to 8 bits of transmit receive data enabling communication using 9 bit data CSI0 and CSI1 perform data transfer accordi...

Page 415: ...rupt INTSER0 Interrupt is generated according to the logical OR of the three types of reception errors Reception completion interrupt INTSR0 Interrupt is generated when receive data is transferred from the shift register to the reception buffer register 0 after serial transfer is completed during a reception enabled state Transmission completion interrupt INTST0 Interrupt is generated when the ser...

Page 416: ...a and the transmission shift register data flag which indicates whether transmission is in progress 4 Reception control parity check The receive operation is controlled according to the contents set in the ASIM0 register A check for parity errors is also performed during a receive operation and if an error is detected a value corresponding to the error contents is set in the ASIS0 register 5 Recep...

Page 417: ...ol parity A transmit operation is controlled by adding a start bit parity bit or stop bit to the data that is written to the TXB0 register according to the contents that were set in the ASIM0 register Figure 10 1 Asynchronous Serial Interface 0 Block Diagram Parity Framing Overrun Internal bus Asynchronous serial interface mode register 0 ASIM0 Reception buffer register 0 RXB0 Reception shift regi...

Page 418: ...UART0 1 Supplies clock to UART0 Cautions 1 When UARTCAE0 0 is set UART0 is asynchronously reset 2 When UARTCAE0 0 UART0 is in a reset state To operate UART0 first set UARTCAE0 1 3 When the UARTCAE0 bit is changed from 1 to 0 all the registers of UART0 are initialized When setting UARTCAE0 1 again be sure to re set the registers of UART0 The output of the TXD0 pin goes high when transmission is dis...

Page 419: ...its with the value 1 the parity bit is set 1 If it contains an even number of bits with the value 1 the parity bit is cleared 0 This controls the number of bits with the value 1 contained in the transmit data and the parity bit so that it is an even number During reception the number of bits with the value 1 contained in the receive data and the parity bit is counted and if the number is odd a par...

Page 420: ...L bit first clear 0 the TXE0 and RXE0 bits 1 SL Specifies stop bit length of transmit data 0 1 bit 1 2 bits Cautions 1 To overwrite the SL bit first clear 0 the TXE0 bit 2 Since reception is always done with a stop bit length of 1 the SL bit setting does not affect receive operations 0 ISRM Enables disables generation of reception completion interrupt requests when an error occurs 0 Generate a rec...

Page 421: ... Address Initial value ASIS0 0 0 0 0 0 PE FE OVE FFFFFA03H 00H Bit Position Bit Name Function 2 PE This is a status flag that indicates a parity error 0 When the ASIM0 register s UARTCAE0 and RXE0 bits are both set to 0 or when the ASIS0 register has been read 1 When reception was completed the transmit data parity did not match the parity bit Caution The operation of the PE bit differs according ...

Page 422: ... ASIM0 register s UARTCAE0 or TXE0 bit is 0 or when data has been transferred to the transmission shift register 1 Data to be transferred next exists in TXB0 register Data exists in TXB0 register when the TXB0 register has been written to Caution When transmission is performed continuously data should be written to the TXB0 register after confirming that this flag is 0 If writing to TXB0 register ...

Page 423: ...t 0 in the ASIM0 register the contents of the RXB0 register are retained and no processing is performed for transferring data to the RXB0 register even when the shift in processing of one frame is completed Also no reception completion interrupt is generated When 7 bits is specified for the data length bits 6 to 0 of the RXB0 register are transferred for the receive data and the MSB bit 7 is alway...

Page 424: ...ister data is transferred to the transmission shift register and a transmission completion interrupt request INTST0 is generated synchronized with the completion of the transmission of one frame from the transmission shift register For information about the timing for generating this interrupt request refer to 10 2 5 2 Transmission operation When TXBF0 bit 1 in the ASIF0 register writing must not ...

Page 425: ...ained for the ASIS0 register Whether a reception error interrupt INTSER0 or a reception completion interrupt INTSR0 is generated when an error occurs can be specified according to the ISRM bit of the ASIM0 register When reception is disabled no reception error interrupt is generated 2 Reception completion interrupt INTSR0 When reception is enabled a reception completion interrupt is generated when...

Page 426: ...igure 10 2 The character bit length within one data frame the type of parity and the stop bit length are specified according to the asynchronous serial interface mode register 0 ASIM0 Also data is transferred with LSB first Figure 10 2 Asynchronous Serial Interface Transmit Receive Data Format 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bits Character bits Start bit 1 bit Charac...

Page 427: ...er 0 TXB0 When a transmit operation is started the data in TXB0 is transferred to transmission shift register Then the transmission shift register outputs data to the TXD0 pin the transmit data is transferred sequentially starting with the start bit The start bit parity bit and stop bits are added automatically c Transmission interrupt request When the transmission shift register becomes empty a t...

Page 428: ...492EJ3V0UD 428 Figure 10 3 Asynchronous Serial Interface Transmission Completion Interrupt Timing Start Stop D0 D1 D2 D6 D7 Parity Parity TXD0 output INTST0 output Start D0 D1 D2 D6 D7 TXD0 output INTST0 output a Stop bit length 1 b Stop bit length 2 Stop ...

Page 429: ... that the TXBF0 bit is 0 and then write the next transmit data second byte to TXB0 register If writing to the TXB0 register is performed when the TXBF0 bit is 1 transmit data cannot be guaranteed While transmission is being performed continuously whether writing to the TXB0 register later is enabled can be judged by confirming the TXSF0 bit after the occurrence of a transmission completion interru...

Page 430: ...egisters Interrupt occurrence Wait for interrupt Required number of transfers performed Write transmit data to TXB0 register Write transmit data to TXB0 register When reading ASIF0 register TXBF0 0 When reading ASIF0 register TXSF0 1 When reading ASIF0 register TXSF0 0 No No No No Yes Yes Yes Yes End of transmission processing ...

Page 431: ...F0 register simultaneously 11 or 00 may be read Thus whether writing to the TXB0 register is enabled or not should be judged only for the TXBF0 bit ASIF0 Register Transmission Starting Procedure Internal Operation TXBF0 TXSF0 Set transmission mode 1 Start transmission unit 0 0 Write data 1 1 0 2 Generate start bit Read ASIF0 register confirm that TXBF0 bit 0 Start data 1 transmission 1 0 0 0 1 0No...

Page 432: ...t Stop bit ASIF0 Register Transmission End Procedure Internal Operation TXBF0 TXSF0 6 Transmission of data m 2 is in progress 1 1 7 INTST0 interrupt occurs Read ASIF0 register confirm that TXBF0 bit 0 0 0 1 1 Write data m 8 Generate start bit Start data m 1 transmission Transmission in progress 1 1 9 INTST0 interrupt occurs Read ASIF0 register confirm that TXSF0 bit 1 There is no write data 10 Gen...

Page 433: ...cording to the serial clock from the baud rate generator 0 BRG0 c Reception completion interrupt When RXE0 bit 1 in the ASIM0 register and the reception of one frame of data is completed the stop bit is detected a reception completion interrupt INTSR0 is generated and the receive data within the reception shift register is transferred to RXB0 at the same time Also if an overrun error OVE occurs th...

Page 434: ...un error The data reception result is that the various flags of the ASIS0 register are set 1 and a reception error interrupt INTSER0 or a reception completion interrupt INTSR0 is generated at the same time The ISRM bit of the ASIM0 register specifies whether INTSER0 or INTSR0 is generated The type of error that occurred during reception can be detected by reading the contents of the ASIS0 register...

Page 435: ...eception b An error occurs during reception INTSR0 output Reception completion interrupt INTSER0 output Reception error interrupt INTSR0 output Reception completion interrupt INTSER0 output Reception error interrupt INTSR0 does not occur Figure 10 9 When Reception Error Interrupt Is Included in INTSR0 Interrupt ISRM Bit 1 a No error occurs during reception b An error occurs during reception INTSR0...

Page 436: ... is odd b Odd parity i During transmission In contrast to even parity the parity bit is controlled so that the number of bits with the value 1 within the transmit data including the parity bit is odd The parity bit value is as follows If the number of bits with the value 1 within the transmit data is odd 0 If the number of bits with the value 1 within the transmit data is even 1 ii During receptio...

Page 437: ...ot delivered to the internal circuit see Figure 10 11 Refer to 10 2 6 1 a Base clock regarding the base clock Also since the circuit is configured as shown in Figure 10 10 internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status Figure 10 10 Noise Filter Circuit RXD0 Q Base clock In LD_EN Q In Internal signal A Internal signal B Match dete...

Page 438: ... generator 0 BRG0 configuration Figure 10 12 Baud Rate Generator 0 BRG0 Configuration fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 fXX 1024 fXX 2048 Base clock fCLK Selector UARTCAE0 8 bit counter Match detector Baud rate BRGC0 MDL7 to MDL0 1 2 UARTCAE0 and TXE0 or RXE0 CKSR0 TPS3 to TPS0 fXX Remark fXX Internal system clock a Base clock When UARTCAE0 bit 1 in the ASIM0 register ...

Page 439: ... be read written in 8 bit units Cautions 1 The maximum allowable frequency of the base clock fCLK is 25 MHz Therefore when the system clock s frequency is 50 MHz bits TPS3 to TPS0 cannot be set to 0000B To use 50 MHz set the TPS3 to TPS0 bits to a value other than 0000B and set the UARTCAE0 bit of the ASIM0 register to 1 2 If the TPS3 to TPS0 bits are to be overwritten the UARTCAE0 bit of the ASIM...

Page 440: ... Bit Position Bit Name Function Specifies the 8 bit counter s division value MDL7 MDL6 MDL5 MDL4 MDL3 MDL2 MDL1 MDL0 Set Value k Serial Clock 0 0 0 0 0 x x x Setting prohibited 0 0 0 0 1 0 0 0 8 fCLK 8 0 0 0 0 1 0 0 1 9 fCLK 9 0 0 0 0 1 0 1 0 10 fCLK 10 1 1 1 1 1 0 1 0 250 fCLK 250 1 1 1 1 1 0 1 1 251 fCLK 251 1 1 1 1 1 1 0 0 252 fCLK 252 1 1 1 1 1 1 0 1 253 fCLK 253 1 1 1 1 1 1 1 0 254 fCLK 254 1...

Page 441: ... rate baud normal rate baud Desired error with rate baud rate baud Actual Error Cautions 1 Make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination 2 Make sure that the baud rate error during reception is within the allowable baud rate range during reception which is described in 4 Allowable baud rate range during reception Example Bas...

Page 442: ... 163 0 15 fXX 25 65 0 16 fXX 23 215 0 07 fXX 22 130 0 16 19200 fXX 23 163 0 15 fXX 24 80 0 16 fXX 22 215 0 07 fXX 21 130 0 16 31250 fXX 23 100 0 fXX 23 65 0 fXX 22 132 0 fXX 21 80 0 38400 fXX 22 163 0 15 fXX 23 65 0 16 fXX 21 215 0 07 fXX 20 130 0 16 76800 fXX 22 81 0 47 fXX 22 65 0 16 fXX 21 107 0 39 fXX 20 65 0 16 153600 fXX 21 81 0 47 fXX 21 65 0 16 fXX 21 54 0 54 fXX 20 33 1 36 312500 fXX 21 4...

Page 443: ...Parity bit Minimum allowable transfer rate Maximum allowable transfer rate Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 10 13 after the start bit is detected the receive data latch timing is determined according to the counter that was set by the BRGC0 register If all data up to the final data stop bit is in time for th...

Page 444: ... allowable baud rate error of UART0 and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values Table 10 4 Maximum and Minimum Allowable Baud Rate Error Division Ratio k Maximum Allowable Baud Rate Error Minimum Allowable Baud Rate Error 8 3 53 3 61 20 4 26 4 31 50 4 56 4 58 100 4 66 4 67 255 4 72 4 73 Remarks ...

Page 445: ...elow 1 When the supply of clocks to UART0 is stopped for example IDLE or STOP mode operation stops with each register retaining the value it had immediately before the supply of clocks was stopped The TXD0 pin output also holds and outputs the value it had immediately before the supply of clocks was stopped However operation is not guaranteed after the supply of clocks is restarted Therefore after...

Page 446: ...rror Interrupt sources 2 types Reception completion interrupt INTSRn Interrupt is generated when receive data is transferred from the shift register to the reception buffer register n RXBn after serial transfer is completed during a reception enabled state Transmission completion interrupt INTSTn Interrupt is generated when the serial transmission of trans mit data 8 7 bits from the shift register...

Page 447: ... registers 4 2 frame continuous reception buffer registers RXB1 RXB2 reception buffer registers RXBL1 RXBL2 RXBn is a 16 bit during 2 frame continuous reception 9 bit extension data reception buffer register that holds receive data During 7 8 bit character reception 0 is stored in the MSB For 16 bit access to this register specify RXB1 RXB2 and for access to the lower 8 bits specify RXBL1 RXBL2 In...

Page 448: ...chronous serial interface mode registers n0 n1 ASIMn0 ASIMn1 Asynchronous serial interface status register n ASISn Transmission control parity addition Reception buffers n Ln RXBn RXBLn PEn FEn OVEn Reception shift register RXDn TXDn MOD bit ASCKn Reception control parity check Selector Selector Selector INTSTn INTSRn SOTn flag BRGn SIRn flag Internal bus 1 16 1 16 Remark n 1 2 ...

Page 449: ...n 8 bit or 1 bit units Cautions 1 If the contents of the ASIMn0 register are changed during UARTn transmission or reception the UARTn operation cannot be guaranteed n 1 2 2 Set the ASIMn0 register when the UARTn operation is stopped when RXEn bit 0 and transmission is completed Do not change port 3 mode control register PMC3 after setting the ASIMn0 register 3 In the case of serial clock output in...

Page 450: ...Specifies parity bit length PS1 PS0 Operation 0 0 No parity extension bit operation 0 1 0 parity Transmit side Transmission with parity bit 0 Receive side No parity error generated during reception 1 0 Odd parity 5 4 PS1 PS0 1 1 Even parity 3 CL Specifies character length of transmit receive data 1 frame 0 7 bits 1 8 bits 2 SL Specifies stop bit length of transmit data 0 1 bit 1 2 bits Specifies s...

Page 451: ...a transmission 1 UMSR Specifies number of continuous frame receptions 0 1 frame data reception 1 2 frame continuous data reception 0 EBS Specifies extension bit operation for transmit receive data when no parity is specified PS0 PS1 0 0 Disable extension bit addition 1 Enable extension bit addition When the extension bit is specified 1 data bit is added on top of the 8 bits of transmit receive dat...

Page 452: ...tion end n 1 2 The status flag that indicates reception errors always indicates the most recent error status In other words if the same error occurs several times before receive data is read this flag holds only the status of the error that occurred last Each time the ASISn register is read after a receive completion interrupt INTSRn read the reception buffer RXBn or RXBLn The error flag is cleare...

Page 453: ...ntil stop bit detection from the start bit detection timing 4 RB8 Indicates contents of receive data extension bit 1 bit when 9 bit extended format is specified EBS bit of ASIMn1 register 1 2 PEn Status flag indicating parity error 0 Processing to read data from reception buffer 1 When transmit parity and receive parity don t match Caution No parity error is generated if no parity is specified or ...

Page 454: ...eive enabled status receive data is transferred from the reception shift register to the reception buffer in synchronization with the end of shift in processing for 1 frame of data The reception completion interrupt request INTSRn is generated upon transfer of data to the reception buffer when 2 frame continuous reception is specified reception buffer transfer of the second frame In the reception ...

Page 455: ...Position Bit Name Function 15 to 0 RXB15 to RXB0 Stores receive data 0 can be read for the RXBn register when 7 8 bit character data is received When an extension bit is set during 9 bit character data reception the extension bit RXB8 is stored in RB8 of the ASISn register simultaneously with saving to the reception buffer 0 can be read for the RXB7 bit of the RXBLn register during 7 bit character...

Page 456: ... reception of 2nd frame no error RXDn Frame 1 Frame 2 Reception completion interrupt not generated upon end of reception of 3rd frame occurrence of error RXDn Frame 3 Frame 3 Value of OVEn bit of ASISn register becomes 1 Reception completion interrupt INTSRn generated upon end of reception of 4th frame no error RXDn Frame 3 Frame 4 Value of OVEn bit of ASISn register remains 1 Start of reception o...

Page 457: ... can be read but since shifting is done in synchronization with the shift clock the data that is read cannot be guaranteed 14 TXS14 13 TXS13 12 TXS12 2 TXS2 3 TXS3 4 TXS4 5 TXS5 6 TXS6 7 TXS7 8 TXS8 9 TXS9 10 TXS10 11 TXS11 15 TXS15 1 TXS1 0 TXS0 TXS1 2 frame continuous transmission shift register 1 Address FFFFFA24H Initial value Undefined 2 TXS2 3 TXS3 4 TXS4 5 TXS5 6 TXS6 7 TXS7 1 TXS1 0 TXS0 T...

Page 458: ... data in the reception shift register undergoes shift in processing and is transferred to the reception buffer The reception completion interrupt request INTSRn is generated following stop bit sampling The reception completion interrupt INTSRn is generated upon occurrence of an error In the reception disabled state no reception completion interrupt is generated Caution A reception completion inter...

Page 459: ...0 20 ASIM10 ASIM20 Specification of the number of frames and specification of the extension bit is done with asynchronous serial interface mode registers 11 21 ASIM11 ASIM21 Data is transmitted LSB first Figure 10 16 Asynchronous Serial Interface Transmit Receive Data Format a 1 frame format 1 frame Data Stop bit Start bit Parity extension bit D0 D1 D2 D3 D4 D5 D6 D7 b 2 frame format Higher frame ...

Page 460: ... DATA Parity bit Stop bit 0 0 0 DATA Stop bit Stop bit 0 Other than PS1 PS0 0 DATA Parity bit Stop bit Stop bit 1 0 0 DATA DATA Stop bit Stop bit 1 Other than PS1 PS0 0 1 0 DATA DATA Parity bit Stop bit Stop bit 0 0 0 DATA Stop bit 0 Other than PS1 PS0 0 DATA Parity bit Stop bit 1 0 0 DATA DATA DATA Stop bit 1 Other than PS1 PS0 0 0 1 DATA DATA Parity bit Stop bit 0 0 0 DATA Stop bit Stop bit 0 Ot...

Page 461: ...utomatically added b Transmission interrupt request When the transmission shift register becomes empty upon completion of the transmission of 1 or 2 frames of data a transmission completion interrupt request INTSTn is generated The INTSTn interrupt generation timing differs depending on the specified stop bit length The INTSTn interrupt is generated at the same time that the last stop bit is outpu...

Page 462: ...bit Start Parity Stop D0 TXDn output INTSTn interrupt Flag in transmission SOTn D1 D2 D6 D7 b When stop bit length 2 bits Start Parity Stop D0 TXDn output INTSTn interrupt Flag in transmission SOTn D1 D2 D6 D7 c In 2 frame continuous transmission mode Start Start Stop Parity Stop D0 TXDn output INTSTn interrupt Flag in transmission SOTn D1 1st frame 2nd frame D1 D5 D6 D7 Parity ...

Page 463: ...Time of one stop bit 2 2 fXX 4 2 fXX fXX Internal system clock Caution 4 2 fXX has a margin of double the clock that can actually be used for operation Example Count clock frequency 32 MHz 32 000 000 Hz Target baud rate in synchronous mode 9 600 bps t 1 9615 385 4 8 32 000 000 104 000 0 375 103 625 µs Therefore be sure to write transmit data to TXSn TXSLn within 103 µs of the generation of the INT...

Page 464: ...ud rate generator After 8 serial clocks have been output following detection of the falling edge of the RXDn pin the RXDn pin is again sampled If a low level is detected at this time the falling edge of the RXDn pin is interpreted as a start bit the operation shifts to reception processing and the RXDn pin input is sampled from this point on in units of 16 serial clock output If the high level is ...

Page 465: ...n bit of the ASIMn0 register 1 the receive data in the shift register is transferred to RXBn RXBLn and a reception completion interrupt request INTSRn is generated after 1 frame or 2 frames of data have been transferred to RXBn RXBLn A reception completion interrupt is also generated upon detection of an error When the RXEn bit 0 reception disabled no reception completion interrupt is generated ...

Page 466: ... D6 D7 c In 2 frame continuous transmission mode Start Start Parity Stop Parity Stop D0 RXDn input INTSRn interrupt Flag in reception SIRn D1 1st frame 2nd frame D1 D5 D6 D7 Cautions 1 Even if a reception error occurs be sure to read 2 frame continuous reception buffer register n RXBn reception buffer register n RXBLn If the RXBn or RXBLn register is not read an overrun error will occur at the nex...

Page 467: ...eption Error Causes PEn Parity error The parity specification during transmission did not match the parity of the reception data FEn Framing error No stop bit was detected OVEn Overrun error The reception of the next data was completed before data was read from the reception buffer 6 Parity types and corresponding operation A parity bit is used to detect a bit error in communication data Normally ...

Page 468: ...e transmit data is even 1 2 During reception The number of bits with the value 1 within the receive data including the parity bit is counted and a parity error is generated if this number is even c 0 parity During transmission the parity bit is set to 0 regardless of the transmit data During reception no parity bit check is performed Therefore no parity error is generated regardless of whether the...

Page 469: ...outputs between connection nodes do not conflict In the synchronous mode the falling edge of the serial clock is used as the transmission timing and the rising edge as the reception timing but transmit data is output with a delay of 1 system clock serial clock in the external clock synchronous mode the maximum delay is 2 5 system clocks Figure 10 20 Transmission Reception Timing in Synchronous Mod...

Page 470: ...e transmission reception mode Serial clock Transmission register write signal Flag in transmission SOTn Transmission completion interrupt INTSTn Reception completion interrupt INTSRn Reception buffer RXBn Reception buffer RXBLn Flag in reception SIRn Transmit data Stop bit Undefined hold previous value Undefined hold previous value 005AH 5AH Remark n 1 2 ...

Page 471: ...ansmission reception mode Serial clock Transmission register write signal Flag in transmission SOTn Transmission completion interrupt INTSTn Reception completion interrupt INTSRn Reception buffer RXBn Reception buffer RXBLn Flag in reception SIRn Transmit data Stop bit Stop bit Undefined hold previous value Undefined hold previous value 5A5AH 5AH 5A15H 15H Remark n 1 2 ...

Page 472: ...ng Note The transmit data is delayed by 1 system clock in relation to the serial clock d Transmission reception timing and transmit data timing using external serial clock Note External serial clock System clock Transmit data Transmission timing Reception timing Note Since during external serial clock synchronization synchronization is done with the internal system clock when feeding the external ...

Page 473: ...in reception SIRn Reception completion interrupt INTSRn Error interrupt STOP STOP 1 2 3 Explanation 1 If the start bit of the second frame is not detected no reception completion interrupt is generated 2 If an error occurs in the first frame an error interrupt is generated following detection of the stop bit of the first frame at the calculated position 3 If an error occurs in the second frame an ...

Page 474: ...nel The serial clock source is specified with registers ASIM10 and ASIM20 If dedicated baud rate generator output is specified BRG1 and BRG2 are selected as the clock sources Since the same serial clock can be shared for transmission and reception for one channel baud rate is the same for the transmission reception Figure 10 23 Block Diagram of Baud Rate Generators 1 2 BRG1 BRG2 BGCS1 BGCS0 PRSCMn...

Page 475: ... in 8 bit or 1 bit units Cautions 1 Do not change the values of the BGCS1 and BGCS0 bits during transmission reception operations 2 Set PRSMn register other than the UARTCEn bit prior to setting the UARTCEn bit to 1 n 1 2 7 UARTCE1 PRSM1 6 0 5 0 4 0 3 0 2 0 1 BGCS1 0 BGCS0 Address FFFFFA2EH Initial value 00H 7 UARTCE2 PRSM2 6 0 5 0 4 0 3 0 2 0 1 BGCS1 0 BGCS0 Address FFFFFA4EH Initial value 00H Bi...

Page 476: ...CM3 2 PRSCM2 1 PRSCM1 0 PRSCM0 Address FFFFFA50H Initial value 00H d Baud rate generation First when the UARTCEn bit of the PRSMn register is overwritten with 1 the 8 bit timer counter for baud rate signal generation starts counting up with the clock selected with bits BGCS1 and BGCS0 of the PRSMn register The count value of the 8 bit timer counter is compared with the value of the PRSCMn register...

Page 477: ...of PRSMn register k 0 1 2 3 Note The setting of m 256 is performed by writing 00H to the PRSCMn register 2 Formula for calculating the baud rate in synchronous mode Baud rate bps fXX Internal system clock frequency Hz CPU clock 2 Hz m Setting value of PRSCMn register 1 m 256 Note k Value set with bits BGCS1 BGCS0 of PRSMn register k 0 1 2 3 Note The setting of m 256 is performed by writing 00H to ...

Page 478: ... 692 3 13 0 16 153600 9600 153846 2 9615 385 2 13 0 16 166400 10400 166666 7 10416 67 1 24 0 16 307200 19200 307692 3 19230 77 1 13 0 16 614400 38400 615384 6 38461 54 0 13 0 16 1228800 76800 1142857 71428 57 0 7 6 99 2457600 153600 2666667 166666 7 0 3 8 51 b When fXX 40 MHz Desired Baud Rate Actual Baud Rate Synchronous Mode Asynchronous Mode Synchronous Mode Asynchronous Mode BGCSm Bit m 0 1 PR...

Page 479: ...e BGCSm Bit m 0 1 PRSCMn Register Setting Value n 1 2 Error 9600 600 9585 89 599 1181 3 163 0 15 19200 1200 19171 78 1198 236 2 163 0 15 38400 2400 38343 56 2396 472 1 163 0 15 76800 4800 76687 12 4792 945 0 163 0 15 153600 9600 154321 9645 062 0 81 0 47 166400 10400 166666 7 10416 67 0 75 0 16 307200 19200 312500 19531 25 0 40 1 73 614400 38400 625000 39062 5 0 20 1 73 1228800 76800 1250000 78125...

Page 480: ...llowable transfer rate Maximum allowable transfer rate Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 10 24 after the start bit is detected the receive data latch timing is determined according to the counter that was set by the PRSCMn register If all data up to the final data stop bit is in time for this latch timing the...

Page 481: ... FLmax can be obtained as follows FL k 2 2 k 21 FL k 2 2 k FL 11 max FL 11 10 11 FL k 20 2 k 21 max FL Therefore the transfer destination s minimum receivable baud rate BRmin is as follows BRmin FLmax 11 1 Brate 4 Transfer rate in 2 frame continuous reception In 2 frame continuous reception the timing is initialized by detecting the start bit of the second frame so the transfer results are not aff...

Page 482: ...SB first and LSB first Eight clock signals can be selected 7 master clocks and 1 slave clock 3 wire type SOn Serial transmit data output SIn Serial receive data input SCKn Serial clock I O Interrupt sources 1 type Transmission reception completion interrupt INTCSIn Transmission reception mode and reception only mode can be specified Two transmission buffers SOTBFn SOTBFLn SOTBn SOTBLn and two rece...

Page 483: ...he actual transmission reception operations are started up by accessing the buffer register 5 Clocked serial interface reception buffer registers 0 1 SIRB0 SIRB1 The SIRBn register is a 16 bit buffer register that stores receive data 6 Clocked serial interface reception buffer registers L0 L1 SIRBL0 SIRBL1 The SIRBLn register is an 8 bit buffer register that stores receive data 7 Clocked serial in...

Page 484: ... Selector The selector selects the serial clock to be used 14 Serial clock controller Controls the serial clock supply to the shift register Also controls the clock output to the SCKn pin when the internal clock is used 15 Serial clock counter Counts the serial clock output or input during transmission reception operation and checks whether 8 bit or 16 bit data transmission reception has been perf...

Page 485: ...uffer register SOTBn SOTBLn Reception buffer register SIRBn SIRBLn Shift register SIOn SIOLn Initial transmission buffer register SOTBFn SOTBFLn Interrupt controller Clock start stop control clock phase control Serial clock controller SCKn INTCSIn SOn SIn Control signal Transmission data control fXX 27 fXX 26 fXX 25 fXX 24 fXX 23 fXX 22 BRG3 SCKn Remarks 1 n 0 1 2 fXX Internal system clock ...

Page 486: ... CSIM1 The CSIMn register controls the CSIn operation n 0 1 These registers can be read written in 8 bit or 1 bit units however bit 0 is read only Caution Overwriting the TRMDn CCL DIRn CSIT and AUTO bits of the CSIMn register can be done only when the CSOTn bit 0 If these bits are overwritten at any other time the operation cannot be guaranteed ...

Page 487: ...pin output is fixed to low level Data reception is started by reading the SIRBn register When the TRMDn bit 1 transmission reception is started by writing data to the SOTBn register 5 CCL Specifies data length 0 8 bits 1 16 bits 4 DIRn Specifies transfer direction mode MSB LSB 0 First bit of transfer data is MSB 1 First bit of transfer data is LSB 3 CSIT Controls delay of interrupt request signal ...

Page 488: ...rface clock selection registers 0 1 CSIC0 CSIC1 The CSICn register is an 8 bit register that controls the CSIn transfer operation n 0 1 These registers can be read written in 8 bit or 1 bit units Caution The CSICn register can be overwritten only when the CSICAEn bit of the CSIMn register 0 ...

Page 489: ...0 1 fXX 26 Master mode 0 1 0 fXX 25 Master mode 0 1 1 fXX 24 Master mode 1 0 0 fXX 23 Master mode 1 0 1 fXX 22 Master mode 1 1 0 Clock generated by BRG3 Master mode 1 1 1 External clock SCKn Slave mode 2 to 0 CKS2 to CKS0 Remark fXX Internal system clock frequency n 0 1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 SOn output SCKn I O SIn input DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7...

Page 490: ...he 16 bit data length has been set CCL bit of CSIMn register 1 2 When the single transfer mode has been set AUTO bit of CSIMn register 0 perform read operation only in the idle state CSOTn bit of CSIMn register 0 If the SIRBn register is read during data transfer the data cannot be guaranteed 14 SIRB 14 13 SIRB 13 12 SIRB 12 2 SIRB 2 3 SIRB 3 4 SIRB 4 5 SIRB 5 6 SIRB 6 7 SIRB 7 8 SIRB 8 9 SIRB 9 1...

Page 491: ...f the CSIMn register The SIRBLn register is the same as the lower bytes of the SIRBn register Cautions 1 Read the SIRBLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform read operation only in the idle state CSOTn bit of CSIMn register 0 If the SIRBLn register is read during data transfer t...

Page 492: ...autions 1 The receive operation is not started even if data is read from the SIRBEn register 2 The SIRBEn register can be read only if the 16 bit data length is set CCL bit of CSIMn register 1 14 SIRBE 14 13 SIRBE 13 12 SIRBE 12 2 SIRBE 2 3 SIRBE 3 4 SIRBE 4 5 SIRBE 5 6 SIRBE 6 7 SIRBE 7 8 SIRBE 8 9 SIRBE 9 10 SIRBE 10 11 SIRBE 11 15 SIRBE 15 1 SIRBE 1 0 SIRBE 0 14 SIRBE 14 13 SIRBE 13 12 SIRBE 12...

Page 493: ...IRBELn register is the same as the SIRBLn register It is used to read the contents of the SIRBLn register Cautions 1 The receive operation is not started even if data is read from the SIRBELn register 2 The SIRBELn register can be read only if the 8 bit data length has been set CCL bit of CSIMn register 0 7 SIRBE7 SIRBEL0 6 SIRBE6 5 SIRBE5 4 SIRBE4 3 SIRBE3 2 SIRBE2 1 SIRBE1 0 SIRBE0 Address FFFFF...

Page 494: ...CSIMn register 1 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform access only in the idle state CSOTn bit of CSIMn register 0 If the SOTBn register is accessed during data transfer the data cannot be guaranteed 14 SOTB 14 13 SOTB 13 12 SOTB 12 2 SOTB 2 3 SOTB 3 4 SOTB 4 5 SOTB 5 6 SOTB 6 7 SOTB 7 8 SOTB 8 9 SOTB 9 10 SOTB 10 11 SOTB 11 15 SOTB 15 1 SOTB 1 0 SOTB 0 SOTB0 ...

Page 495: ...same as the lower bytes of the SOTBn register Cautions 1 Access the SOTBLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 2 When the single transfer mode is set AUTO bit of CSIMn register 0 perform access only in the idle state CSOTn bit of CSIMn register 0 If the SOTBLn register is accessed during data transfer the data cannot be guaranteed 7 SOTB7 SOTBL0 6 SOTB...

Page 496: ...CSIMn register 1 and only in the idle state CSOTn bit of CSIMn register 0 If the SOTBFn register is accessed during data transfer the data cannot be guaranteed 14 SOTBF 14 13 SOTBF 13 12 SOTBF 12 2 SOTBF 2 3 SOTBF 3 4 SOTBF 4 5 SOTBF 5 6 SOTBF 6 7 SOTBF 7 8 SOTBF 8 9 SOTBF 9 10 SOTBF 10 11 SOTBF 11 15 SOTBF 15 1 SOTBF 1 0 SOTBF 0 14 SOTBF 14 13 SOTBF 13 12 SOTBF 12 2 SOTBF 2 3 SOTBF 3 4 SOTBF 4 5 ...

Page 497: ...is the same as the lower bytes of the SOTBFn register Caution Access the SOTBFLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 and only in the idle state CSOTn bit of CSIMn register 0 If the SOTBFLn register is accessed during data transfer the data cannot be guaranteed 7 SOTBF7 SOTBFL0 6 SOTBF6 5 SOTBF5 4 SOTBF4 3 SOTBF3 2 SOTBF2 1 SOTBF1 0 SOTBF0 Address FFFFF...

Page 498: ...nly when the 16 bit data length has been set CCL bit of CSIMn register 1 and only in the idle state CSOTn bit of CSIMn register 0 If the SIOn register is read during data transfer the data cannot be guaranteed 14 SIO14 13 SIO13 12 SIO12 2 SIO2 3 SIO3 4 SIO4 5 SIO5 6 SIO6 7 SIO7 8 SIO8 9 SIO9 10 SIO10 11 SIO11 15 SIO15 1 SIO1 0 SIO0 SIO0 Address FFFFF90AH Initial value 0000H 14 SIO14 13 SIO13 12 SI...

Page 499: ...register The SIOLn register is the same as the lower bytes of the SIOn register Caution Read the SIOLn register only when the 8 bit data length has been set CCL bit of CSIMn register 0 and only in the idle state CSOTn bit of CSIMn register 0 If the SIOLn register is read during data transfer the data cannot be guaranteed 7 SIO7 SIOL0 6 SIO6 5 SIO5 4 SIO4 3 SIO3 2 SIO2 1 SIO1 0 SIO0 7 SIO7 6 SIO6 5...

Page 500: ...e value of the CSOTn bit of the CSIMn register becomes 1 transmission execution status Upon transfer completion the transmission reception completion interrupt INTCSIn is set 1 and the CSOTn bit is cleared 0 The next data transfer request is then waited for Notes 1 When the 16 bit data length CCL bit of CSIMn register 1 has been set read the SIRBn register When the 8 bit data length CCL bit of CSI...

Page 501: ...ration mode CKP bit 0 DAP bit 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 55H AAH AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCKn I O SOn output SIn input Reg_R W SOTBLn register SIOLn register SIRBLn register CSOTn bit INTCSIn interrupt 55H transmit data Write 55H to SOTBLn register Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data...

Page 502: ...ration mode CKP bit 0 DAP bit 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 AAH AAH ABH 56H ADH 5AH B5H 6AH D5H SCKn I O SOn output SIn input Reg_R W SOTBLn register SIOLn register SIRBLn register CSOTn bit INTCSIn interrupt 55H AAH 55H transmit data Write 55H to SOTBLn register Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data...

Page 503: ...st signal delay control CSIT bit of CSIMn register 0 Figure 10 27 Timing Chart According to Clock Phase Selection 1 2 a When CKP bit 0 DAP bit 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit DI0 DO0 b When CKP bit 1 DAP bit 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCKn I O SIn input SOn output Reg_R W INTC...

Page 504: ...O1 SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit DI0 DO0 d When CKP bit 1 DAP bit 1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DO7 DO6 DO5 DO4 DO3 DO2 DO1 SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit DI0 DO0 Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn writ...

Page 505: ...not 111B The delay mode cannot be set when the slave mode is set bits CKS2 to CKS0 111B Figure 10 28 Timing Chart of Interrupt Request Signal Output in Delay Mode 1 2 a When CKP bit 0 DAP bit 0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Input clock SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit Delay Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indi...

Page 506: ...hen CKP bit 1 DAP bit 1 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Input clock SCKn I O SIn input SOn output Reg_R W INTCSIn interrupt CSOTn bit Delay Remarks 1 n 0 1 2 Reg_R W Internal signal This signal indicates that receive data buffer register SIRBn SIRBLn read or transmit data buffer register SOTBn SOTBLn write was performed ...

Page 507: ...ission reception completion interrupt request INTCSIn has been set 1 read the SIRBn register Note reserve next transfer 5 Repeat steps 3 and 4 N 2 times N Number of transfer data 6 Following output of the last transmission reception completion interrupt request INTCSIn read the SIRBEn register and the SIOn register Note Note When transferring N number of data receive data is loaded by reading the ...

Page 508: ... indicates that the receive data buffer register SIRBn SIRBLn has been read rq_clr Internal signal Transfer request clear signal trans_rq Internal signal Transfer request signal In the case of the repeat transfer mode two transfer requests are set at the start of the first transfer Following the transmission reception completion interrupt request INTCSIn transfer is continued if the SIRBn register...

Page 509: ...terrupt request INTCSIn 5 When the transmission reception completion interrupt request INTCSIn has been set 1 write the next data to the SOTBn register reserve next transfer and read the SIRBn register to load the receive data 6 Repeat steps 4 and 5 as long as data to be sent remains 7 Wait for the INTCSIn interrupt When the interrupt request signal is set 1 read the SIRBn register to load the N 1...

Page 510: ...al This signal indicates that the transmit data buffer register SOTBn SOTBLn has been written Reg_RD Internal signal This signal indicates that the receive data buffer register SIRBn SIRBLn has been read rq_clr Internal signal Transfer request clear signal trans_rq Internal signal Transfer request signal In the case of the repeat transfer mode two transfer requests are set at the start of the firs...

Page 511: ...red with the period shown in Figure 10 31 Figure 10 31 Timing Chart of Next Transfer Reservation Period 1 2 a When data length 8 bits operation mode CKP bit 0 DAP bit 0 SCKn I O INTCSIn interrupt Reservation period 7 SCKn cycles b When data length 16 bits operation mode CKP bit 0 DAP bit 0 SCKn I O INTCSIn interrupt Reservation period 15 SCKn cycles Remark n 0 1 ...

Page 512: ... Next Transfer Reservation Period 2 2 c When data length 8 bits operation mode CKP bit 0 DAP bit 1 SCKn I O INTCSIn interrupt Reservation period 6 5 SCKn cycles d When data length 16 bits operation mode CKP bit 0 DAP bit 1 SCKn I O INTCSIn interrupt Reservation period 14 5 SCKn cycles Remark n 0 1 ...

Page 513: ...etween transfer request clear and register access Since request cancellation has higher priority the next transfer request is ignored Therefore transfer is interrupted and normal data transfer cannot be performed Figure 10 32 Transfer Request Clear and Register Access Contention SCKn I O INTCSIn interrupt rq_clr Reg_R W Transfer reservation period Remarks 1 n 0 1 2 rq_clr Internal signal Transfer ...

Page 514: ... 10 33 In the transmission reception mode the value of the SOTBFn register is retransmitted and illegal data is sent Figure 10 33 Interrupt Request and Register Access Contention SCKn I O INTCSIn interrupt rq_clr Reg_R W Transfer reservation period 0 1 2 3 4 Remarks 1 n 0 1 2 rq_clr Internal signal Transfer request clear signal Reg_R W Internal signal This signal indicates that receive data buffer...

Page 515: ...output changes 2 SOn pin When the CSIn operation is disabled CSICAEn bit of CSIMn register 0 the SOn pin output status is as follows n 0 1 Table 10 10 SOn Pin Output Status TRMDn DAP AUTO CCL DIRn SOn Pin Output 0 Don t care Don t care Don t care Don t care Fixed to low level 0 Don t care Don t care Don t care SO latch value low level 0 SOTB7 value 0 1 SOTB0 value 0 SOTB15 value 0 1 1 SOTB0 value ...

Page 516: ...XX The serial clock source is specified with registers CSIC0 and CSIC1 If dedicated baud rate generator output is specified BRG3 is selected as the clock source Since the same serial clock can be shared for transmission and reception baud rate is the same for the transmission reception Figure 10 34 Block Diagram of Baud Rate Generator 3 BRG3 BGCS1 BGCS0 PRSCM3 Match detector 1 2 CSIn 8 bit timer c...

Page 517: ...e signals This register can be read written in 8 bit or 1 bit units Cautions 1 Do not change the values of the BGCS1 and BGCS0 bits during transmission reception operation 2 Set the PRSM3 register prior to setting the CSICAEn bit of the CSIMn register to 1 n 0 1 7 0 PRSM3 6 0 5 0 4 CE 3 0 2 0 1 BGCS1 0 BGCS0 Address FFFFF920H Initial value 00H Bit Position Bit Name Function 4 CE Enables baud rate ...

Page 518: ...ting the CSICAEn bit of the CSIMn register to 1 If the contents of the PRSCM3 register are overwritten when the value of the CSICAEn bit is 1 the cycle of the baud rate signal is not guaranteed 7 PRSCM7 PRSCM3 6 PRSCM6 5 PRSCM5 4 PRSCM4 3 PRSCM3 2 PRSCM2 1 PRSCM1 0 PRSCM0 Address FFFFF922H Initial value 00H d Baud rate signal cycle The baud rate signal cycle is calculated as follows When setting v...

Page 519: ...When fXX 40 MHz BGCS1 BGCS0 PRSCM Register Value Clock Hz 0 0 2 2500000 0 0 5 1000000 0 0 10 500000 0 0 20 250000 0 0 50 100000 0 0 100 50000 0 0 200 25000 0 1 250 10000 1 0 250 5000 c When fXX 50 MHz BGCS1 BGCS0 PRSCM Register Value Clock Hz 0 0 2 3125000 0 0 4 1562500 0 0 5 1250000 0 0 10 625000 0 0 25 250000 0 0 50 125000 0 0 125 50000 0 0 250 25000 0 1 250 12500 1 0 250 6250 Caution Set the tr...

Page 520: ... Storage to reception buffer corresponding to ID Storage to buffer specified by receive mask function Remote reception Remote frames can be received in either the receive message buffer or the transmit message buffer If a remote frame is received by a transmit message buffer there is a choice between having the remote request processed by the CPU or starting the auto transmit function Remote trans...

Page 521: ...us interface as a means of transmitting and receiving signals 2 MAC Memory Access Controller This functional block controls access to the CAN module and to the CAN RAM within the FCAN 3 CAN module This functional block is involved in the operation of the CAN protocol layer and its related settings 4 CAN RAM This is the CAN memory functional block which is used to store message IDs message data etc...

Page 522: ...troller CAN RAM NPB NEC peripheral I O bus MAC Memory Access Controller NPB interface CAN module Interrupt request INTCREC INTCTRX INTCERR INTCMAC Message buffer 0 Message buffer 1 Message buffer 2 Message buffer 3 Message buffer 31 CMASK0 CMASK1 CMASK2 CMASK3 CTXD CRXD CAN_H CAN_L CAN transceiver CAN bus ...

Page 523: ... field xxxxm9E0H to xxxxm9FFH Message buffer 15 field xxxxmA00H to xxxxmA1FH Message buffer 16 field xxxxmA20H to xxxxmA3FH Message buffer 17 field xxxxmA40H to xxxxmA5FH Message buffer 18 field xxxxmA60H to xxxxmA7FH Message buffer 19 field xxxxmA80H to xxxxmA9FH Message buffer 20 field xxxxmAA0H to xxxxmABFH Message buffer 21 field xxxxmAC0H to xxxxmADFH Message buffer 22 field xxxxmAE0H to xxxx...

Page 524: ...d after the SOF is detected on the CAN bus see Figure 11 2 and when the TMR bit is 1 the time stamp counter value is captured after the EOF is detected on the CAN bus a valid message is confirmed see Figure 11 3 Figure 11 2 Time Stamp Function Setting for Message Reception When C1CTRL Register s TMR Bit 0 Message ACK field EOF SOF 2 1 Time stamp counter Temporary buffer M_TIMEn CAN message buffer ...

Page 525: ...must be captured using the SOF In addition the ability to capture the time stamp counter value when message is stored in CAN message buffer n is useful for evaluating the FCAN controller s performance The captured time stamp counter value is stored in CAN message buffer n so CAN message buffer n has its own time stamp function n 00 to 31 When the SOF is detected on the CAN bus while transmitting a...

Page 526: ...r value 2 Note 2 Note 3 3 M_DATAn0 register value Note 2 Note 3 4 M_DATAn0 register value M_DATAn1 register value Note 2 Note 3 5 M_DATAn0 register value M_DATAn1 register value M_DATAn2 register value Note 2 Note 3 6 M_DATAn0 register value M_DATAn1 register value M_DATAn2 register value M_DATAn3 register value Note 2 Note 3 7 M_DATAn0 register value M_DATAn1 register value M_DATAn2 register valu...

Page 527: ...ty among messages is determined based on the locations of the messages in memory the message that has the lowest message number among the messages in the message buffer has the highest priority When several messages have been received in the CAN module s message buffers priority control for storing received messages is as follows Priority rank 1 Remote frame reception in the transmit message buffe...

Page 528: ...se value is defined as 1 by masking is not subject to the abovementioned comparison between the received message s identifier and the message buffer s identifier However this comparison is performed for any bit whose value is defined as 0 by masking For example let us assume that all messages that have a standard format ID in which bits ID27 to ID25 0 and bits ID24 and ID22 1 are to be stored in m...

Page 529: ...MID23 CMID22 CMID21 CMID20 CMID19 CMID18 1 0 0 0 0 1 0 1 1 1 1 CMID17 CMID16 CMID15 CMID14 CMID13 CMID12 CMID11 CMID10 CMID9 CMID8 CMID7 1 1 1 1 1 1 1 1 1 1 1 CMID6 CMID5 CMID4 CMID3 CMID2 CMID1 CMID0 1 1 1 1 1 1 1 Remark 1 Do not compare mask 0 Compare Values are written to mask 1 see 11 10 19 bits CMID27 to CMID24 and CMID22 are set to 0 and bits CMID28 CMID23 and CMID21 to CMID0 are set to 1 ...

Page 530: ...evel and bit expression rules Higher Lower 11 7 1 Protocol mode function 1 Standard format mode 2032 different identifiers can be set in this mode The standard format mode uses 11 bit identifiers which means that it can handle up to 2032 messages 2 Extended format mode This mode is used to extend the number of identifiers that can be set While the standard format mode uses 11 bit identifiers the e...

Page 531: ...at is output when an error has been detected Overload frame Frame that is output when receiving side is not ready Remark Dominant D Dominant in wired OR Recessive R Recessive in wired OR In the figure shown below D 0 and R 1 1 Data frame and remote frame 1 Data frame A data frame is the frame used for transmit data This frame is composed of seven fields Figure 11 7 Data Frame R D Interframe space ...

Page 532: ...art of frame SOF Remote frame 1 2 3 5 6 7 8 Remark The data field is not transferred even if the control field s data length code is not 0000B 2 Description of fields 1 Start of frame SOF The start of frame field is a 1 bit dominant D field that is located at the start of a data frame or remote frame Figure 11 9 Start of Frame SOF R D 1 bit Start of frame Interframe space or bus idle Arbitration f...

Page 533: ...n Field In Extended Format Mode R D r1 r0 RTR IDE SRR IdentifierNote Identifier Arbitration field Control field 11 bits 18 bits ID28 ID18 ID17 ID0 1 bit 1 bit 1 bit Note Setting the higher 7 bits of the identifier as 1111111B is prohibited Cautions 1 ID28 to ID0 are identifier bits 2 Identifier bits are transferred in MSB first order Table 11 4 RTR Bit Settings Frame Type RTR Bit Data frame Domina...

Page 534: ...ontrol Field R D r1 IDE r0 RTR DLC2 DLC3 DLC1 DLC0 Control field Data field Arbitration field In standard format mode the arbitration field s IDE bit is the same bit as the r1 bit Table 11 6 Data Length Code Settings Data Length Code DLC3 DLC2 DLC1 DLC0 Data Byte Count 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0...

Page 535: ...sequence and a 1 bit CRC delimiter Figure 11 14 CRC Field R D CRC sequence CRC delimiter 1 bit 15 bits CRC field ACK field Data field control field The polynomial P X used to generate the 15 bit CRC sequence is expressed as X 15 X 14 X 10 X 8 X 7 X 4 X 3 1 Transmitting node No bit stuffing in start of frame arbitration field control field or data field The transferred CRC sequence is calculated en...

Page 536: ...ng depending on whether or not an error is detected between the start of frame field and the CRC field If an error is detected ACK slot Recessive R If no error is detected ACK slot Dominant D The transmitting node outputs two recessive R bits and confirms the receiving node s receive status 7 End of frame EOF The end of frame field indicates the end of transmission or reception It includes 7 reces...

Page 537: ...ode is set if a transmission starts from a different node in bus idle mode The error passive node is composed of an intermission field suspend transmission field and bus idle field Figure 11 17 Interframe Space a Error active R D Interframe space Intermission 3 or 2 bits Bus idle 0 or more bits Frame Frame b Error passive R D Interframe space Intermission 3 or 2 bits Suspend transmission 8 bits Bu...

Page 538: ...frame ends when the next recessive R bit is detected Figure 11 18 Error Frame 1 R D 2 3 6 bits 0 to 6 bits 8 bits 4 5 Interframe space or overload frame Error delimiter Error flag Error flag Error bit Error frame No Name Bit Count Definition Error active node Consecutive output of 6 dominant D bits 1 Error flag 6 Error passive node Consecutive output of 6 recessive R bits 2 Error flag 0 to 6 A nod...

Page 539: ...n Overload flag node m Frame Overload frame No Name Bit count Definition 1 Overload flag starting from node m 6 Consecutive output of 6 dominant D bits Output when node m is not ready to receive 2 Overload flag starting from node n 0 to 6 Node n which has received an overload flag in the interframe space outputs an overload flag 3 Overload delimiter 8 8 consecutive recessive R bits are output If a...

Page 540: ...etween a data frame and a remote frame the data frame takes priority because its last bit RTR is dominant D 11 8 2 Bit stuffing Bit stuffing is when one bit of inverted data is added for resynchronization to prevent burst errors when the same level is maintained for five consecutive bits Table 11 9 Bit Stuffing Transmit When transmitting data frames and remote frames if the same level is maintaine...

Page 541: ...t of frame to end of frame error frame or overload frame Stuff error Use stuff bits to check receive data Six consecutive bits of same level data Transmitting receiving nodes Start of frame to CRC sequence CRC error Comparison of CRC generated from receive data and received CRC sequence CRC mismatch Receiving node Start of frame to data field Form error Check fixed format field frame Detection of ...

Page 542: ...During startup if only one node is active the error frame and data are repeatedly resent because no ACK is returned even data has been transmitted In such cases bus off mode cannot be set Even if the node that is sending the transmit message repeatedly experiences an error status bus off mode cannot be set Table 11 12 Types of Error Statuses Error Status Type Operation Error Counter Value Type of ...

Page 543: ...uring output of active error flag or overload flag transmitting node with error active status 8 No change Detection of bit error during output of active error flag or overload flag receiving node with error active status No change 8 14 consecutive dominant D bits were detected from the start of each node s active error flag or overload flag followed by detection of eight consecutive dominant bits ...

Page 544: ...hase segment 1 Sample point Prop segment Sync segment Segment Name Segment Length Description Sync segment Synchronization Segment 1 This segment begins when resynchronization occurs Prop segment Propagation Segment 1 to 8 programmable This segment is used to absorb the delays caused by the output buffer CAN bus and input buffer It is set to return an ACK signal until phase segment 1 begins Prop s...

Page 545: ...n bus idle mode When a falling edge is detected on the bus the current bit is assigned to the sync segment and the next bit is assigned to the prop segment In such cases synchronization is performed regardless of the SJW Since bit synchronization must be established after a reset or after a wake up hardware synchronization is performed only at the first level change that occurs on the bus for the ...

Page 546: ...it timing specified by the SJW synchronization is performed in the same way as hardware synchronization When the edge is detected as extending beyond the bit timing specified by the SJW synchronization is performed on the following basis When phase error is positive Phase segment 1 is lengthened to equal the SJW When phase error is negative Phase segment 2 is shortened to equal the SJW A shifting ...

Page 547: ...he usual method Use the procedure described in Figure 11 23 below to set or clear the lower 8 bits in these registers Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits see Figure 11 24 Figure 11 23 shows how the values of set bits or clear bits relate to set clear no change operations in the corresponding register Figure 11 23 Example of ...

Page 548: ... During Write Operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n Bit Status After Bit Set Clear Operation 0 0 No change 0 1 0 1 0 1 1 1 No change Remark n 0 to 7 ...

Page 549: ... register can be read written in 8 bit or 1 bit units Caution Set this register before using FCAN 7 0 PRM04 6 0 5 0 4 0 3 0 2 0 1 PRM5 0 PRM4 Address FFFFF930H Initial value 00H Bit Position Bit Name Function Specifies FCAN base clock fMEM1 PRM5 PRM4 Input Clock Specification 0 0 fXX 4 when fXX 48 MHz 0 1 fXX 2 when 16 MHz fXX 32 MHz 1 0 fXX 3 when 32 MHz fXX 48 MHz 1 1 fXX when fXX 16 MHz 1 0 PRM...

Page 550: ...ffer the values of DLC3 to DLC0 in the message buffer are cleared to 0 regardless of the values of DLC3 to DLC0 on the CAN bus 7 0 M_DLCn n 00 to 31 6 0 5 0 4 0 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Address See Table 11 14 Initial value Undefined Bit Position Bit Name Function Control field data for setting the number of bytes in the data field DLC3 DLC2 DLC1 DLC0 Data Length Code of Transmit Receive Messag...

Page 551: ...m8A4H M_DLC21 xxxxmAA4H M_DLC06 xxxxm8C4H M_DLC22 xxxxmAC4H M_DLC07 xxxxm8E4H M_DLC23 xxxxmAE4H M_DLC08 xxxxm904H M_DLC24 xxxxmB04H M_DLC09 xxxxm924H M_DLC25 xxxxmB24H M_DLC10 xxxxm944H M_DLC26 xxxxmB44H M_DLC11 xxxxm964H M_DLC27 xxxxmB64H M_DLC12 xxxxm984H M_DLC28 xxxxmB84H M_DLC13 xxxxm9A4H M_DLC29 xxxxmBA4H M_DLC14 xxxxm9C4H M_DLC30 xxxxmBC4H M_DLC15 xxxxm9E4H M_DLC31 xxxxmBE4H Note CAN message...

Page 552: ... frame is received 1 DN flag set when remote frame is received 7 RMDE1 Cautions 1 When the RMDE1 bit is set the setting of the RMDE0 bit is irrelevant 2 If a remote frame arrives at the transmit message buffer when the RMDE1 bit has not been set the CPU is not notified nor are other operations performed Specifies setting clearing status of remote frame auto acknowledge function 0 Remote frame auto...

Page 553: ...ved by the transmit message buffer when the auto acknowledge function has not been set RMDE0 bit 0 2 An interrupt request is not generated when interrupts are enabled under the following conditions When a remote frame is received by the transmit message buffer when the auto acknowledge function has been set RMDE0 bit 1 3 An interrupt request is generated under the following conditions even if inte...

Page 554: ... M_CTRL21 xxxxmAA5H M_CTRL06 xxxxm8C5H M_CTRL22 xxxxmAC5H M_CTRL07 xxxxm8E5H M_CTRL23 xxxxmAE5H M_CTRL08 xxxxm905H M_CTRL24 xxxxmB05H M_CTRL09 xxxxm925H M_CTRL25 xxxxmB25H M_CTRL10 xxxxm945H M_CTRL26 xxxxmB45H M_CTRL11 xxxxm965H M_CTRL27 xxxxmB65H M_CTRL12 xxxxm985H M_CTRL28 xxxxmB85H M_CTRL13 xxxxm9A5H M_CTRL29 xxxxmBA5H M_CTRL14 xxxxm9C5H M_CTRL30 xxxxmBC5H M_CTRL15 xxxxm9E5H M_CTRL31 xxxxmBE5H ...

Page 555: ... according to the FCAN s time stamp setting which is either the time stamp counter value that was captured when the SOF was sent via the bus or the value captured when the CAN module writes data to the message buffer Table 11 16 Addresses of M_TIMEn n 00 to 31 Register Name AddressNote m 2 6 A E Register Name AddressNote m 2 6 A E M_TIME00 xxxxm806H M_TIME16 xxxxmA06H M_TIME01 xxxxm826H M_TIME17 x...

Page 556: ..._4 3 D5_3 2 D5_2 1 D5_1 0 D5_0 Address See Table 11 17 Initial value Undefined 7 D6_7 M_DATAn6 n 00 to 31 6 D6_6 5 D6_5 4 D6_4 3 D6_3 2 D6_2 1 D6_1 0 D6_0 Address See Table 11 17 Initial value Undefined 7 D7_7 M_DATAn7 n 00 to 31 6 D7_6 5 D7_5 4 D7_4 3 D7_3 2 D7_2 1 D7_1 0 D7_0 Address See Table 11 17 Initial value Undefined Bit Position Bit Name Function Indicates the contents of the message data...

Page 557: ... 14 xxxxm9C8H xxxxm9C9H xxxxm9CAH xxxxm9CBH xxxxm9CCH xxxxm9CDH xxxxm9CEH xxxxm9CFH 15 xxxxm9E8H xxxxm9E9H xxxxm9EAH xxxxm9EBH xxxxm9ECH xxxxm9EDH xxxxm9EEH xxxxm9EFH 16 xxxxmA08H xxxxmA09H xxxxmA0AH xxxxmA0BH xxxxmA0CH xxxxmA0DH xxxxmA0EH xxxxmA0FH 17 xxxxmA28H xxxxmA29H xxxxmA2AH xxxxmA2BH xxxxmA2CH xxxxmA2DH xxxxmA2EH xxxxmA2FH 18 xxxxmA48H xxxxmA49H xxxxmA4AH xxxxmA4BH xxxxmA4CH xxxxmA4DH xxxx...

Page 558: ...1 ID0 Third byte higher two bits of receive data Note is stored Note See 11 10 5 CAN message data registers n0 to n7 M_DATAn0 to M_DATAn7 n 00 to 31 14 0 13 0 12 ID28 2 ID18 3 ID19 4 ID20 5 ID21 6 ID22 7 ID23 8 ID24 9 ID25 10 ID26 11 ID27 15 IDE 1 ID17 0 ID16 M_IDHn n 00 to 31 Address See Table 11 19 Initial value Undefined 14 ID14 13 ID13 12 ID12 2 ID2 3 ID3 4 ID4 5 ID5 6 ID6 7 ID7 8 ID8 9 ID9 10...

Page 559: ...the addresses xxxx as programmable peripheral I O registers Note however that the xxxx addresses cannot be changed after being set Table 11 19 Addresses of M_IDHn n 00 to 31 Register Name AddressNote m 2 6 A E Register Name AddressNote m 2 6 A E M_IDH00 xxxxm812H M_IDH16 xxxxmA12H M_IDH01 xxxxm832H M_IDH17 xxxxmA32H M_IDH02 xxxxm852H M_IDH18 xxxxmA52H M_IDH03 xxxxm872H M_IDH19 xxxxmA72H M_IDH04 xx...

Page 560: ...ive message mask 1 is set 1 0 0 Receive message mask 2 is set 1 0 1 Receive message mask 3 is set 1 1 0 Setting prohibited 1 1 1 Receive message used in diagnostic processing mode 5 to 3 MT2 to MT0 When bits MT2 to MT0 have been set as 111 processing can be performed only when the FCAN has been set to diagnostic processing mode In such cases all messages received are stored regardless of the follo...

Page 561: ... M_CONF21 xxxxmAB4H M_CONF06 xxxxm8D4H M_CONF22 xxxxmAD4H M_CONF07 xxxxm8F4H M_CONF23 xxxxmAF4H M_CONF08 xxxxm914H M_CONF24 xxxxmB14H M_CONF09 xxxxm934H M_CONF25 xxxxmB34H M_CONF10 xxxxm954H M_CONF26 xxxxmB54H M_CONF11 xxxxm974H M_CONF27 xxxxmB74H M_CONF12 xxxxm994H M_CONF28 xxxxmB94H M_CONF13 xxxxm9B4H M_CONF29 xxxxmBB4H M_CONF14 xxxxm9D4H M_CONF30 xxxxmBD4H M_CONF15 xxxxm9F4H M_CONF31 xxxxmBF4H ...

Page 562: ...ftware compatibility Bit Position Bit Name Function 2 DN This is the message update flag 0 No message was received after DN bit was cleared 1 At least one message was received after DN bit was cleared When the DN bit has been set to 1 by the transmit message buffer it indicates that the message buffer has received a remote frame When this message is sent the DN bit is automatically cleared to 0 Wh...

Page 563: ... M_STAT21 xxxxmAB5H M_STAT06 xxxxm8D5H M_STAT22 xxxxmAD5H M_STAT07 xxxxm8F5H M_STAT23 xxxxmAF5H M_STAT08 xxxxm915H M_STAT24 xxxxmB15H M_STAT09 xxxxm935H M_STAT25 xxxxmB35H M_STAT10 xxxxm955H M_STAT26 xxxxmB55H M_STAT11 xxxxm975H M_STAT27 xxxxmB75H M_STAT12 xxxxm995H M_STAT28 xxxxmB95H M_STAT13 xxxxm9B5H M_STAT29 xxxxmBB5H M_STAT14 xxxxm9D5H M_STAT30 xxxxmBD5H M_STAT15 xxxxm9F5H M_STAT31 xxxxmBF5H ...

Page 564: ...the message update flag set DN clear DN Operation 0 1 Cleared DN bit cleared 1 0 Set DN bit set Other than above No change in DN bit value 10 2 set DN clear DN Specifies setting clearing of the transmit request flag set TRQ clear TRQ Operation 0 1 Cleared TRQ bit cleared 1 0 Set TRQ bit set Other than above No change in TRQ bit value 9 1 set TRQ clear TRQ Specifies setting of the message ready fla...

Page 565: ...STAT21 xxxxmAB6H SC_STAT06 xxxxm8D6H SC_STAT22 xxxxmAD6H SC_STAT07 xxxxm8F6H SC_STAT23 xxxxmAF6H SC_STAT08 xxxxm916H SC_STAT24 xxxxmB16H SC_STAT09 xxxxm936H SC_STAT25 xxxxmB36H SC_STAT10 xxxxm956H SC_STAT26 xxxxmB56H SC_STAT11 xxxxm976H SC_STAT27 xxxxmB76H SC_STAT12 xxxxm996H SC_STAT28 xxxxmB96H SC_STAT13 xxxxm9B6H SC_STAT29 xxxxmBB6H SC_STAT14 xxxxm9D6H SC_STAT30 xxxxmBD6H SC_STAT15 xxxxm9F6H SC_...

Page 566: ... set m 2 6 A E Bit Position Bit Name Function 14 INTMAC Indicates an MAC errorNote interrupt GINT2 GINT1 is pending 0 Not pending 1 Pending 2 CAN1ERR Indicates a CAN access error interrupt C1INT6 to C1INT2 is pending 0 Not pending 1 Pending 1 CAN1REC Indicates a CAN receive completion interrupt C1INT1 is pending 0 Not pending 1 Pending 0 CAN1TRX Indicates a CAN transmit completion interrupt C1INT0...

Page 567: ...en the interrupt enable bit has been set to 1 However the interrupt pending bit is not automatically cleared to 0 just because the interrupt enable bit has been cleared to 0 Use software processing to clear the interrupt pending bit to 0 Remark For details of invalid write access error interrupts and unavailable memory address access error interrupts see 11 15 2 Interrupts that are generated for g...

Page 568: ...cleared to 0 just because the interrupt enable bit has been cleared to 0 Use software processing to clear the interrupt pending bit to 0 7 0 C1INTP 6 C1INT6 5 C1INT5 4 C1INT4 3 C1INT3 2 C1INT2 1 C1INT1 0 C1INT0 Address xxxxmC04HNote Initial value 00H Note xxxx CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I O registers Note however that the xxxx add...

Page 569: ...he CSTP bit has not been set to 1 3 When a change occurs on the CAN bus via a CSTP bit setting while the clock supply to the CPU or peripheral functions is stopped CPU can be woken up 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 15 CSTP 1 0 0 0 CSTOP Address xxxxmC0CHNote Initial value 0000H Note xxxx CAN message buffer registers can be allocated to the xxxx addresses as programmable p...

Page 570: ...tions on Bit Set Clear Function 2 When writing to the CGST register set or clear bits according to the register configuration shown in part b Write 1 3 Address xxxxmC10HNote Initial value 0100H 14 0 13 0 12 0 2 TSM 3 EFSD 4 0 5 0 6 0 7 MERR 8 1 9 0 10 0 11 0 15 0 1 0 0 GOM CGST Read 14 0 13 0 12 0 2 clear TSM 3 clear EFSD 4 0 5 0 6 0 7 clear MERR 8 set GOM 9 0 10 set TSM 11 set EFSD 15 0 1 0 0 cle...

Page 571: ...ote See 11 10 17 CAN time stamp count register CGTSC 0 GOM Indicates the status of the global operation mode 0 Access to CAN module registerNote is prohibited 1 Access to CAN module registerNote is enabled Note Register starting with C1 Cautions 1 The GOM bit controls the memory access method by the MAC When GOM bit 0 Access to the CAN module register is prohibited if accessed a MAC error interrup...

Page 572: ... value 11 3 set EFSD clear EFSD Sets clears the TSM bit set TSM clear TSM Operation 0 1 TSM bit cleared to 0 1 0 TSM bit set to 1 Other than above No change in TSM bit value 10 2 set TSM clear TSM Sets clears the GOM bit set GOM clear GOM Operation 0 1 GOM bit cleared to 0 1 0 GOM bit set to 1 Other than above No change in GOM bit value 8 0 set GOM clear GOM 7 clear MERR Clears the MERR bit 0 No c...

Page 573: ... 4 0 5 0 6 0 7 0 8 0 9 set G_IE1 10 set G_IE2 11 0 15 0 1 clear G_IE1 0 0 CGIE Write 14 0 13 0 12 0 2 G_IE2 3 0 4 0 5 0 6 0 7 0 8 0 9 1 10 0 11 1 15 0 1 G_IE1 0 0 Note xxxx CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I O registers Note however that the xxxx addresses cannot be changed after being set m 2 6 A E a Read Bit Position Bit Name Function...

Page 574: ... A E Bit Position Bit Name Function Indicates global timer system clock fGTS see Figure 11 25 n CGTS 7 CGTS 6 CGTS 5 CGTS 4 CGTS 3 CGTS 2 CGTS 1 CGTS 0 System Timer Prescaler Selection fGTS fGTS1 n 1 0 0 0 0 0 0 0 0 0 fGTS fGTS1 1 1 0 0 0 0 0 0 0 1 fGTS fGTS1 2 fGTS fGTS1 n 1 127 0 1 1 1 1 1 1 1 fGTS fGTS1 128 after reset fGTS fGTS1 n 1 254 1 1 1 1 1 1 1 0 fGTS fGTS1 255 255 1 1 1 1 1 1 1 1 fGTS f...

Page 575: ...GTCS0 MCP3 MCP2 Prescaler Data bit time CAN1 bit rate prescaler register C1BRP CAN main clock selection register CGCS Global timer clock prescaler Baud rate generator Global timer system clock CAN1 synchronization control register C1SYNC Time stamp counter MCP1 MCP0 BRP0 BRP1 BRP2 BRP3 BRP4 BRP5 BTYPE fMEM1 PRM04 fXX fXX 2 fXX 3 fXX 4 fMEM fGTS1 fBTL fGTS FCAN Selector BRP7Note BRP6Note Note Only ...

Page 576: ...ar function writes 0 to all bits in the CGTSC register This register is read only in 16 bit units 14 TSC14 13 TSC13 12 TSC12 2 TSC2 3 TSC3 4 TSC4 5 TSC5 6 TSC6 7 TSC7 8 TSC8 9 TSC9 10 TSC10 11 TSC11 15 TSC15 1 TSC1 0 TSC0 CGTSC Address xxxxmC18HNote Initial value 0000H Note xxxx CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I O registers Note howeve...

Page 577: ...ddresses as programmable peripheral I O registers Note however that the xxxx addresses cannot be changed after being set m 2 6 A E a Read Bit Position Bit Name Function 9 MM Confirms multiple hits from message search 0 No messages or only one message meets the search criteria 1 Several messages meet the search criteria If several message buffers that meet search criteria are detected the MM bit is...

Page 578: ...f the DN flag of M_STATn register not checked 1 Status of the DN flag of M_STATn register checked 8 SMNO Sets search module 0 No search module setting 1 CAN module set as search target 4 to 0 STRT4 to STRT0 Indicates message search start position 0 to 31 Message search start position message number Search starts from the message number defined by bits STRT4 to STRT0 Search continues until it reach...

Page 579: ...to compare the lower 18 bits i e to mask the lower 18 bits set the CMID17 to CMID0 bits to 1 a 0 to 3 Address See Table 11 23 Initial value Undefined 14 0 13 0 12 CMID 28 2 CMID 18 3 CMID 19 4 CMID 20 5 CMID 21 6 CMID 22 7 CMID 23 8 CMID 24 9 CMID 25 10 CMID 26 11 CMID 27 15 CMIDE 1 CMID 17 0 CMID 16 C1MASKHa a 0 to 3 Address See Table 11 23 Initial value Undefined 14 CMID 14 13 CMID 13 12 CMID 12...

Page 580: ...2 6 A E C1MASKL0 xxxxmC40H C1MASKH0 xxxxmC42H C1MASKL1 xxxxmC44H C1MASKH1 xxxxmC46H C1MASKL2 xxxxmC48H C1MASKH2 xxxxmC4AH C1MASKL3 xxxxmC4CH C1MASKH3 xxxxmC4EH Note CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I O registers Note however that the xxxx addresses cannot be changed after being set ...

Page 581: ...LEVT 6 clear DLEVR 7 0 8 set INIT 9 set SLEEP 10 set STOP 11 set TMR 15 0 1 clear SLEEP 0 clear INIT C1CTRL Write 14 TECS0 13 RECS1 12 RECS0 2 STOP 3 TMR 4 OVM 5 DLEVT 6 DLEVR 7 0 8 ISTAT 9 RSTAT 10 TSTAT 11 BOFF 15 TECS1 1 SLEEP 0 INIT Note xxxx CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I O registers Note however that the xxxx addresses cannot ...

Page 582: ...1 is reset 6 DLEVR This is the dominant level control bit for receive pins 0 A low level to a receive pin is acknowledged as dominant 1 A high level to a receive pin is acknowledged as dominant 5 DLEVT This is the dominant level control bit for transmit pins 0 A low level is transmitted from a transmit pin as dominant 1 A high level is transmitted from a transmit pin as dominant 4 OVM This is the ...

Page 583: ...module 0 Normal operation mode 1 Initialization mode Cautions 1 Be sure to confirm that the CAN module has entered the initialization mode using the ISTAT bit ISTAT bit 1 after setting the INIT bit to 1 When the ISTAT bit 0 set the INIT bit to 1 again 2 If the INIT bit is set to 1 when the CAN module is in the bus off status BOFF bit 1 the CAN module enters initialization mode ISTAT bit 1 after re...

Page 584: ...Other than above TMR bit not changed 11 3 set TMR clear TMR Sets clears the STOP bit set STOP clear STOP Operation 0 1 STOP bit cleared to 0 1 0 STOP bit set to 1 Other than above STOP bit not changed 10 2 set STOP clear STOP Sets clears the SLEEP bit set SLEEP clear SLEEP Operation 0 1 SLEEP bit cleared to 0 1 0 SLEEP bit set to 1 Other than above SLEEP bit not changed 9 1 set SLEEP clear SLEEP S...

Page 585: ...ite 14 0 13 0 12 0 2 VALID 3 BERR 4 PBB 5 SSHT 6 MOM 7 DGM 8 0 9 0 10 0 11 0 15 0 1 WAKE 0 OVR Note xxxx CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I O registers Note however that the xxxx addresses cannot be changed after being set m 2 6 A E a Read 1 3 Bit Position Bit Name Function 7 DGM Specifies diagnostic processing mode 0 Only when receivin...

Page 586: ...rred due to a transmission it is handled as an incomplete transmission Cautions 1 In single shot mode even if the CAN lost in arbitration it is handled as a completed message transmission When in this mode the BERR bit is set to 1 but the error counter value refer to 11 10 23 CAN1 error count register C1ERC does not change since there are no CAN bus errors 2 During the time when the CAN module is ...

Page 587: ...0 Normal operation 1 CAN sleep mode canceled 0 OVR Indicates overrun error status 0 Normal operation 1 Overrun occurred during RAM access Caution When an overrun error has occurred the OVR bit is set to 1 and an error interrupt occurs at the same time The source of the overrun error may be that the RAM access clock is slower than the selected CAN baud rate ...

Page 588: ...e SSHT bit set SSHT clear SSHT Operation 0 1 SSHT bit cleared to 0 1 0 SSHT bit set to 1 Other than above SSHT bit not changed 13 5 set SSHT clear SSHT Sets clears the PBB bit set PBB clear PBB Operation 0 1 PBB bit cleared to 0 1 0 PBB bit set to 1 Other than above PBB bit not changed 12 4 set PBB clear PBB 3 clear BERR Clears the BERR bit 0 No change in BERR bit 1 BERR bit cleared to 0 2 clear V...

Page 589: ...however that the xxxx addresses cannot be changed after being set m 2 6 A E Bit Position Bit Name Function Indicates the last error information LERR3 LERR2 LERR1 LERR0 Last Error Information 0 0 0 0 Error not detected 0 0 0 1 Bit error 0 0 1 0 Stuff error 0 0 1 1 CRC error 0 1 0 0 Form error 0 1 0 1 ACK error 0 1 1 0 Arbitration lost only in single shot mode C1DEF register s SSHT bit 1 0 1 1 1 CAN...

Page 590: ...ters can be allocated to the xxxx addresses as programmable peripheral I O registers Note however that the xxxx addresses cannot be changed after being set m 2 6 A E Bit Position Bit Name Function 15 to 8 REC7 to REC0 Indicates the reception error count 0 to 255 The number of reception errors This reflects the current status of the reception error counter The number of counts is defined by the CAN...

Page 591: ... 12 0 2 E_INT2 3 E_INT3 4 E_INT4 5 E_INT5 6 E_INT6 7 0 8 1 9 0 10 0 11 1 15 0 1 E_INT1 0 E_INT0 Note xxxx CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I O registers Note however that the xxxx addresses cannot be changed after being set m 2 6 A E a Read Bit Position Bit Name Function 6 E_INT6 This is the CAN module error interrupt enable flag 0 Inte...

Page 592: ..._INT4 Operation 0 1 E_INT4 interrupt cleared to 0 1 0 E_INT4 interrupt set to 1 Other than above E_INT4 interrupt not changed 12 4 set E_INT4 clear E_INT4 Sets clears the E_INT3 bit set E_INT3 clear E_INT3 Operation 0 1 E_INT3 interrupt cleared to 0 1 0 E_INT3 interrupt set to 1 Other than above E_INT3 interrupt not changed 11 3 set E_INT3 clear E_INT3 Sets clears the E_INT2 bit set E_INT2 clear E...

Page 593: ...EJ3V0UD 3 3 b Write 2 2 Bit Position Bit Name Function Sets clears the E_INT0 bit set E_INT0 clear E_INT0 Operation 0 1 E_INT0 interrupt cleared to 0 1 0 E_INT0 interrupt set to 1 Other than above E_INT0 interrupt not changed 8 0 set E_INT0 clear E_INT0 ...

Page 594: ...ction Indicates CAN module status CACT4 CACT3 CACT2 CACT1 CACT0 CAN Module Status 0 0 0 0 0 Reset state 0 0 0 0 1 Bus idle wait 0 0 0 1 0 Bus idle state 0 0 0 1 1 Start of frame 0 0 1 0 0 Standard identifier area 0 0 1 0 1 Data length code area 0 0 1 1 0 Data field area 0 0 1 1 1 CRC field area 0 1 0 0 0 CRC delimiter 0 1 0 0 1 ACK slot 0 1 0 1 0 ACK delimiter 0 1 0 1 1 End of frame area 0 1 1 0 0...

Page 595: ...by the value set to the C1SYNC register While in normal operation mode C1DEF register s MOM bit 0 the C1BRP register can only be accessed when the initialization mode has been set C1CTRL register s INIT bit 1 This register can be read written in 16 bit units Caution While in diagnostic processing mode C1DEF register s MOM bit 1 the C1BRP register can only be accessed when the initialization mode h...

Page 596: ...t be changed after being set m 2 6 A E a When TLM 0 Bit Position Bit Name Function 15 TLM Specifies transfer layer mode 0 6 bit prescaler mode 6 BTYPE Specifies CAN bus type 0 Low speed 125 kbps 1 High speed 125 kbps Specifies CAN protocol layer base system clock fBTL for CAN module n BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN Protocol Layer Base System Clock fBTL 0 0 0 0 0 0 0 fMEM 2 1 0 0 0 0 0 1 fMEM 4 ...

Page 597: ... clock fBTL for CAN module n BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN Protocol Layer Base System Clock fBTL 0 0 0 0 0 0 0 0 0 Setting prohibited 1 0 0 0 0 0 0 0 1 fMEM 2 2 0 0 0 0 0 0 1 0 fMEM 3 3 0 0 0 0 0 0 1 1 fMEM 4 fMEM n 1 252 1 1 1 1 1 1 0 0 fMEM 253 253 1 1 1 1 1 1 0 1 fMEM 254 254 1 1 1 1 1 1 1 0 fMEM 255 255 1 1 1 1 1 1 1 1 fMEM 256 7 to 0 BRP7 to BRP0 Remark fBTL fMEM n 1 CAN protoco...

Page 598: ... 0 this register cannot be accessed 2 Storage of the last 8 bits is automatically stopped if an error or a valid message ACK delimiter is detected on the CAN bus Reset is automatically performed each time when the SOF is detected on the CAN bus 14 DINF14 13 DINF13 12 DINF12 2 DINF2 3 DINF3 4 DINF4 5 DINF5 6 DINF6 7 DINF7 8 DINF8 9 DINF9 10 DINF10 11 DINF11 15 DINF15 1 DINF1 0 DINF0 C1DINF Address ...

Page 599: ...ystem clock 1 2 14 0 13 0 12 SAMP 2 DBT2 3 DBT3 4 DBT4 5 SPT0 6 SPT1 7 SPT2 8 SPT3 9 SPT4 10 SJW0 11 SJW1 15 0 1 DBT1 0 DBT0 C1SYNC Address xxxxmC5EHNote Initial value 0218H Note xxxx CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I O registers Note however that the xxxx addresses cannot be changed after being set m 2 6 A E Bit Position Bit Name Func...

Page 600: ...ve Setting prohibited 9 to 5 SPT4 to SPT0 Remark Sampling point within bit timing is selected Sets data bit time DBT4 DBT3 DBT2 DBT1 DBT0 Data Bit Time 0 0 1 1 1 BTL 8 0 1 0 0 0 BTL 9 0 1 0 0 1 BTL 10 0 1 0 1 0 BTL 11 0 1 0 1 1 BTL 12 0 1 1 0 0 BTL 13 0 1 1 0 1 BTL 14 0 1 1 1 0 BTL 15 0 1 1 1 1 BTL 16 1 0 0 0 0 BTL 17 1 0 0 0 1 BTL 18 1 0 0 1 0 BTL 19 1 0 0 1 1 BTL 20 1 0 1 0 0 BTL 21 1 0 1 0 1 BT...

Page 601: ...ontrol Register C1SYNC Settings See Figure 11 32 CAN1 Interrupt Enable Register C1IE Settings See Figure 11 33 CAN1 Definition Register C1DEF Settings See Figure 11 34 CAN1 Control Register C1CTRL Settings See Figure 11 35 CAN1 Address Mask a Registers L and H C1MASKLa and C1MASKHa a 0 to 3 Settings See Figure 11 36 Message Buffer Settings Set CAN global interrupt enable register CGIE Set CAN glob...

Page 602: ...ler Figure 11 28 CAN Global Interrupt Enable Register CGIE Settings START No Enable interrupt for G_IE1 bit Yes set G_IE1 1 clear G_IE1 0 No Enable interrupt for G_IE2 bit An interrupt occurs if a memory address in the undefined area is accessed An interrupt occurs if the GOM bit is not cleared 0 under the following conditions When shutdown is disabled EFSD bit 0 When a CAN module not in the initi...

Page 603: ... 0 Figure 11 30 CAN1 Bit Rate Prescaler Register C1BRP Settings START No Transfer speed is 125 kbps or less Yes BTYPE 0 low speed fBTL setting When TLM 0 BRP5 to BRP0 When TLM 1 BRP7 to BRP0 When TLM 0 When TLM 1 fBTL fMEM n 1 2 n 0 to 63 set using bits BRP5 to BRP0 fBTL fMEM n 1 n 0 to 255 set using bits BRP7 to BRP0 fBTL BTYPE 1 high speed Remark fBTL CAN protocol layer base system clock fMEM CA...

Page 604: ...me BTL m 1 m 7 to 24 set using bits DBT4 to DBT0 Sampling point BTL m 1 m 4 to 16 set using bits SPT4 to SPT0 Set sampling point SPT4 to SPT0 Set SJW SJW1 SJW0 SAMP 1 Yes Set once only single shot sampling Set sampling for one location only Set sampling for three locations SJW BTL m 1 m 0 to 3 set using bits SJW1 and SJW0 Remark BTL 1 fBTL fBTL CAN protocol layer base system clock ...

Page 605: ... No clear E_INT2 1 set E_INT2 0 Enable interrupt for E_INT2 Interrupt enable flag for error passive or bus off by TEC set E_INT3 1 clear E_INT3 0 No clear E_INT3 1 set E_INT3 0 Enable interrupt for E_INT3 Interrupt enable flag for error passive by REC set E_INT4 1 clear E_INT4 0 No clear E_INT4 1 set E_INT4 0 Enable interrupt for E_INT4 Interrupt enable flag for wake up from CAN sleep mode set E_I...

Page 606: ...mbers Diagnostic processing mode Transmit priority is determined based on identifiers Single shot mode Transmit only once Do not retransmit clear DGM 1 set DGM 0 No set DGM 1 clear DGM 0 Store to bufferNote used for diagnostic processing mode clear PBB 1 set PBB 0 No set PBB 1 clear PBB 0 Determine transmit priority based on identifiers set SSHT 1 clear SSHT 0 No clear SSHT 1 set SSHT 0 Set single...

Page 607: ... pins Set dominant level for receive pins Store timer value when EOF occurs Do not overwrite message in DN flag delete new message Set dominant level to high level Set dominant level to high level set OVM 1 clear OVM 0 Yes clear OVM 1 set OVM 0 Store message of DN flag set DLEVT 1 clear DLEVT 0 Yes clear DLEVT 1 set DLEVT 0 Set dominant level to low level set DLEVR 1 clear DLEVR 0 Yes No No No No ...

Page 608: ...C1MASKLa and C1MASKHa a 0 to 3 Settings START Standard frame Mask setting for standard frame x 18 to 28 Mask setting for extended frame x 0 to 28 Mask setting for message ID format No CMIDx 0 CMIDx 1 Mask ID bit Yes Yes No Yes CMIDE 0 CMIDE 1 Check ID type No No CMIDx 0 CMIDx 1 Mask ID bit Yes CMIDy 1 y 0 to 17 ...

Page 609: ... IIDE 0 standard M_IDHn Set message configuration See Figure 11 37 CAN Message Configuration Registers 00 to 31 M_CONF00 to M_CONF31 Settings See Figure 11 38 CAN Message Control Registers 00 to 31 M_CTRL00 to M_CTRL31 Settings IDE 1 extended M_IDHn Set identifier standard extended Set message control byte Set message length Remark n 00 to 31 ...

Page 610: ...essage buffer Yes Yes MA 0 MA 1 Yes No No No No No No No MT2 to MT0 111 used in diagnostic processing mode MT2 to MT0 000 MT2 to MT0 001 MT2 to MT0 010 MT2 to MT0 011 MT2 to MT0 100 MT2 to MT0 101 Yes Yes Yes Yes Transmit message Receive message no mask setting Receive message set mask 0 Receive message set mask 1 Receive message set mask 2 Receive message set mask 3 Remark n 00 to 31 ...

Page 611: ...START Yes No No RTR 0 RTR 1 Transmit receive remote frame Transmit receive data frame Set remote frame auto acknowledge function Yes No IE 0 IE 1 Enable interrupt Disable interrupt Yes No RMDE0 1 RMDE0 0 Remote frame auto acknowledge Yes No RMDE1 1 RMDE1 0 ATS 1 ATS 0 Set DN flag Yes Apply time stamp Set DN flag when remote frame is received ...

Page 612: ...it messages are output from the target message buffer Figure 11 39 Transmit Setting START End of transmit operation Set RDY flag set RDY 1 clear RDY 0 SC_STATn Set data M_DATAnm Select transmit message buffer Set transmit request flag set TRQ 1 clear TRQ 0 SC_STATn Remark n 00 to 31 m 0 to 7 ...

Page 613: ... interrupt pending flag Set RDY flag set RDY 1 clear RDY 0 SC_STATn End of receive operation Yes Receive data frame No Yes Receive data frame Receive remote frame Detection methods 1 Detect using CAN1 information register C1LAST 2 Detect using CAN message search start result register CGMSS CGMSR No DN 0 M_STATn Detect target message buffer Clear DN flag clear DN 1 set DN 0 SC_STATn Get data length...

Page 614: ...ake up occurs when there is a bus operation Figure 11 41 CAN Sleep Mode Settings START End of CAN sleep mode settings No Yes SLEEP 1 C1CTRL set SLEEP 1 clear SLEEP 0 C1CTRL Figure 11 42 Clearing of CAN Sleep Mode by CAN Bus Active Status START CAN bus active SLEEP 0 C1CTRL WAKE 1 C1DEF Wake up interrupt occurs End of CAN sleep mode clearing operation ...

Page 615: ...AN sleep mode clearing operation 11 11 5 CAN stop mode In CAN stop mode the FCAN controller can be set to standby mode No wake up occurs when there is a bus operation stop mode is controlled by CPU access only Figure 11 44 CAN Stop Mode Settings START End of CAN stop mode settings Yes SLEEP 1 C1CTRL No set STOP 1 clear STOP 0 C1CTRL Set CAN sleep mode see Figure 11 41 ...

Page 616: ...CHAPTER 11 FCAN CONTROLLER 616 User s Manual U14492EJ3V0UD Figure 11 45 Clearing of CAN Stop Mode START End of CAN stop mode clearing operation clear STOP 1 set STOP 0 clear SLEEP 1 set SLEEP 0 C1CTRL ...

Page 617: ...r C1SYNC 1 Example of FCAN baud rate setting when C1BRP register s TLM bit 0 The following is an example of how correct settings for the C1BRP register and C1SYNC register can be calculated Conditions from CAN bus 1 CAN module frequency fMEM 16 MHz 2 CAN bus baud rate 83 kbps 3 Sampling point 75 or more 4 Synchronization jump width 3 BTL First calculate the ratio between the CAN module frequency a...

Page 618: ...4 10 The settings that can actually be made for the V850E IA1 are in the range from 5 to 7 above the section enclosed in broken lines Among these options in the range from 5 to 7 above option 6 is the ideal setting for used when actually setting the register i Prescaler CAN protocol layer base system clock fBTL setting fBTL is calculated as below fBTL fMEM a 1 2 0 a 63 Value a is set using bits 5 ...

Page 619: ...s baud rate iii SPT sampling point setting Given SJW 3 SJW DBT SPT 3 15 SPT SPT 12 Therefore SPT is set as 11 max SPT is calculated as below SPT BTL a 1 4 a 16 Value a is set using bits 9 to 5 SPT4 to SPT0 of the C1SYNC register SPT BTL 12 BTL 11 1 thus a 11 iv SJW synchronization jump width setting SJW is calculated as below SJW BTL a 1 0 a 3 Value a is set using bits11 and 10 SJW1 SJW0 of the C1...

Page 620: ... the message buffer having the lowest message number is selected 2 Receive messages can be stored in receive message buffers when the receive messages meet the following conditions 1 Messages are not linked to masks 2 M_STATn register s DN bit has been set to 1 n 00 to 31 If several messages have met the above conditions the message buffer having the lowest message number is selected 3 Low Receive...

Page 621: ...an be stored in receive message buffers when the receive messages meet the following conditions Messages are not linked to masks M_STATn register s DN bit has been set to 1 n 00 to 31 If several receive message buffers have met the above conditions the message buffer having the lowest message number is selected 4 Low Receive messages can be stored in receive message buffers that are linked to mask...

Page 622: ...ead When the CPU performs sequential access of a CAN message buffer data is read from the buffer in the order shown in Figure 11 47 below Only the FCAN can set the M_STATn register s DN bit to 1 and only the CPU can clear it to 0 so during the read operation the CPU must be able to check whether or not any new data has been stored in the message buffer Figure 11 47 Sequential Data Read Read CPU En...

Page 623: ...incrementing 1 the read address when data is read in the following order M_DLCn register M_CTRLn register M_TIMEn register M_DATAn0 to M_DATAn7 registers M_IDLn M_IDHn register If these linear address rules are not followed or if access is attempted to an address that is lower than the M_IDHn register s address such as the M_CONFn register or M_STATn register burst read mode becomes invalid Cautio...

Page 624: ... bus error has been detected Bit error Bit stuff error Form error CRC error ACK error 3 When the CAN bus mode has been changed Error passive status elapsed while FCAN was transmitting Bus off status was set while FCAN was transmitting Error passive status elapsed while FCAN was receiving 4 Internal error Overrun error 11 15 2 Interrupts that are generated for global CAN interface Interrupts are ge...

Page 625: ...stamp counter Set TSM bit 0 in CGST register set TSM bit 0 clear TSM bit 1 3 Stop CAN interface Set GOM bit 0 in CGST register set GOM bit 0 clear GOM bit 1 Stop CAN clock Cautions 1 If the above procedure is not performed correctly the CAN interface in active status can cause operation faults 2 Perform only steps 1 and 2 above when setting the CPU itself to low power mode and operating the CAN in...

Page 626: ... When receiving a remote frame with an extended ID and storing it in the receive message buffer the values of DLC3 to DLC0 in the message buffer are cleared to 0 regardless of the values of DLC3 to DLC0 on the CAN bus 4 Be sure to properly clear to 0 all interrupt request flags Note in the interrupt routine If these flags are not cleared to 0 subsequent interrupt requests may not be generated Note...

Page 627: ...r 24 bit address setting for match detection on chip at a single point this function outputs a match trigger falling edge to the NBD tool when the address match detection shown below is performed The lower 2 bits are masked Execution PC address match detection Internal RAM area address write timing match detection Detection range ROM X0000000H to X003FFFFH RAM XFFFC000H to XFFFE7FFH Table 12 1 NBD...

Page 628: ...pace of the CPU but exists independently as NBD space Because of this NBD space is space that cannot be read or written from within the CPU but can only be read or written from the NBD dedicated interface refer to Figure 12 1 Table 12 2 NBD Space Map Address Register Name Symbol R W After Reset 000H Chip ID register 0 TID0 4EH 001H Chip ID register 1 TID1 01H 002H Chip ID register 2 TID2 R 01H 800...

Page 629: ...nction is shown below 1 Basic protocol Figure 12 2 Basic Protocol 1 On a read CLK_DBG SYNC AD0_DBG to AD3_DBG N Address section Command packet Flag sense Control section N R Data packet 2 On a write CLK_DBG SYNC AD0_DBG to AD3_DBG N N R Address section Data section Command packet Flag sense Control section Remark N Not ready R Ready ...

Page 630: ... D21 D20 15th D27 D26 D25 D24 16th D31 D30 D29 D28 Caution Values are for command packet maximum setup Access to NBD space Address 12 bits A0 to A11 Fixed Data 8 bits D0 to D7 Access to target space Address 24 bits A0 to A23 Fixed Data 32 bits D0 to D31 a aux0 to aux3 Expansion bits aux0 aux1 aux2 aux3 Remarks 0 0 0 0 Fixed Other than 0000 For future expansion b I T Access address space mode speci...

Page 631: ...ite RAM data will be destroyed 2 A write is invalid and read data is undefined in cases where Setting prohibited is specified 3 Flag sense packet NBD Bus Line AD3_DBG AD2_DBG AD1_DBG AD0_DBG 1st 0 0 0 RFLG RFLG 0 Not Ready 1 Ready 4 Data packet The data packet data size is the data size specified by SIZ1 and SIZ0 in a command packet 8 16 or 32 bits NBD Bus Line AD3_DBG AD2_DBG AD1_DBG AD0_DBG 1st ...

Page 632: ...ommand SYNC inactive confirmation Table 12 3 Command Packet On a Write ADn_DBG AD3_DBG AD2_DBG AD1_DBG AD0_DBG 1st 0 0 0 0 2nd SIZ1 SIZ0 1 1 3rd to 8th Target space write address specification 24 bits 9th to 16th Write data data specified by SIZ0 and SIZ1 b Read command The target address real address of target lower 24 bits at which a read of internal RAM is to be made is received from the NBD to...

Page 633: ...et On a Write to NBD Space ADn_DBG AD3_DBG AD2_DBG AD1_DBG AD0_DBG 1st 0 0 0 0 2nd 0 0 1 0 3rd A3 A2 A1 A0 4th A7 A6 A5 A4 5th A11 A10 A9 A8 6th D3 D2 D1 D0 7th D7 D6 D5 D4 Caution An NBD space write address is 12 bit fixed length The write data is 8 bit fixed length b Read command The target address real address of target 12 bits at which to read from internal RAM is received as a command packet ...

Page 634: ...ith the system clock of the target CPU The active width is one cycle of the internal system clock of the CPU 1 Event detection conditions Execution PC address match Match detection range for timing of a write to a set address in the internal RAM area XFFFC000H to XFFFE7FFH 2 Event detection function control register a NBD event condition setting register EVTU_C 7 0 EVTU_C7 to EVTU_C0 6 0 5 0 4 0 3...

Page 635: ...11 EVAU11 10 EVAU10 9 EVAU9 8 EVAU8 NBD space address 801H Initial value Undefined 23 EVAU23 EVTU_A23 to EVTU_A16 22 EVAU22 21 EVAU21 20 EVAU20 19 EVAU19 18 EVAU18 17 EVAU17 16 EVAU16 NBD space address 802H Initial value Undefined 31 Undefined EVTU_A27 to EVTU_A24 30 Undefined 29 Undefined 28 Undefined 27 EVAU27Note 26 EVAU26Note 25 EVAU25Note 24 EVAU24Note NBD space address 803H Initial value Und...

Page 636: ... The chip ID registers have fixed values for each product The chip ID registers TID0 to TID2 are read only registers 7 MC7 TID0 6 MC6 MC7 to MC0 Semiconductor manufacturer classification code NEC Electronics 4EH 5 MC5 4 MC4 3 MC3 2 MC2 1 MC1 0 MC0 NBD space address 000H 7 FC7 TID1 6 FC6 5 FC5 4 FC4 3 FC3 2 FC2 1 FC1 0 FC0 NBD space address 001H FC7 to FC0 CPU classification code V850E1 CPU 01H SC7...

Page 637: ...access of RAM Remark Register values written from the NBD tool can be read by DMA CPU and values written by DMA CPU can be read by the NBD tool 2 RAM access data buffer register H NBDH NBDH register operates as buffer between DMA and the NBD tool when reading or writing RAM via DMA from the NBD tool NBDH register can be read written in 16 bit units When the higher 8 bits of the NBDH register are u...

Page 638: ...value can be read from the NBDMSL register by DMA CPU 4 DMA source address setting register SH NBDMSH NBDMSH register specifies a DMA source address It can be written from the NBD tool and read by DMA CPU It can be read only in 16 bit units 14 0 13 0 12 0 2 AD18 3 AD19 4 AD20 5 AD21 6 AD22 7 AD23 8 AD24 9 AD25 10 AD26 11 AD27 15 IR 1 AD17 0 AD16 NBDMSH Address FFFFFA66H Initial value Undefined Bit...

Page 639: ...value can be read from the NBDMDL register by DMA CPU 6 DMA destination address setting register DH NBDMDH NBDMDH register specifies a DMA destination address It can be written from the NBD tool and read by DMA CPU It can be read only in 16 bit units 14 0 13 0 12 0 2 AD18 3 AD19 4 AD20 5 AD21 6 AD22 7 AD23 8 AD24 9 AD25 10 AD26 11 AD27 15 IR 1 AD17 0 AD16 NBDMDH Address FFFFFA6AH Initial value Und...

Page 640: ...fterwards Reset again 12 6 3 Restrictions related to NBD event trigger function 1 If a ROM execution address event trigger is set to the address after a branch instruction an event is generated due to pipeline processing even if it is not executed The trigger must be set to an address at least 32 bits 3 words after a branch instruction 2 Since an event trigger is cleared by a reset it must be set ...

Page 641: ...3 Note DMA registers are 16 bit access only 4 Set DMA addressing control register n DADCn of the DMA channel assigned to the NBDREW interrupt for 32 bit transfer bit transfer settings of 8 bits 4 16 bits 2 and 32 bits 1 Note n 0 to 3 In addition set the counter direction of the DMA transfer source address and DMA transfer destination address to increment mode SADm bit of DADCn register 0 DADm bit ...

Page 642: ...0x0000F088 r24 DMACH0 Destination Address st h r24 DDAL0 r0 mov 0x00000FFF r24 DMACH0 Destination Address st h r24 DDAH0 r0 mov 0x0000400c r24 DMACH0 Block MODE 16Bit MODE st h r24 DADC0 r0 mov 0x0000800c r24 DMACH1 Block MODE 32Bit MODE st h r24 DADC1 r0 mov 0x00000003 r24 DMACH0 Block MODE 16Bit 4 st h r24 DBC0 r0 mov 0x00000000 r24 DMACH1 Block MODE 32Bit 1 st h r24 DBC1 r0 mov 0x00000009 r24 D...

Page 643: ... DDAL0 r0 mov 0x00000FFF r24 DMACH0 Destination Address st h r24 DDAH0 r0 mov 0x0000400c r24 DMACH0 Block MODE 16Bit MODE st h r24 DADC0 r0 mov 0x0000400c r24 DMACH1 Block MODE 16Bit MODE st h r24 DADC1 r0 mov 0x00000003 r24 DMACH0 Block MODE 16Bit 4 st h r24 DBC0 r0 mov 0x00000001 r24 DMACH1 Block MODE 16Bit 2 st h r24 DBC1 r0 mov 0x00000009 r24 DMACH0 1 DMA ready st b r24 DCHC0 r0 st b r24 DCHC1...

Page 644: ... DDAL0 r0 mov 0x00000FFF r24 DMACH0 Destination Address st h r24 DDAH0 r0 mov 0x0000400c r24 DMACH0 Block MODE 16Bit MODE st h r24 DADC0 r0 mov 0x0000000c r24 DMACH1 Block MODE 8Bit MODE st h r24 DADC1 r0 mov 0x00000003 r24 DMACH0 Block MODE 16Bit 4 st h r24 DBC0 r0 mov 0x00000003 r24 DMACH1 Block MODE 8Bit 4 st h r24 DBC1 r0 mov 0x00000009 r24 DMACH0 1 DMA ready st b r24 DCHC0 r0 st b r24 DCHC1 r...

Page 645: ...r ADSCM10 register and sends it to the sample and hold circuit n 0 to 7 2 Sample and hold circuit The sample and hold circuit individually samples analog inputs sent sequentially from the input circuit and sends them to the comparator It holds sampled analog inputs during A D conversion 3 Voltage comparator The voltage comparator compares the analog input voltage that was input with the output vol...

Page 646: ...es to ANI0n and ANI1n that are within the range of the ratings In particular if a voltage including noise higher than AVDD or lower than AVSS even one within the range of absolute maximum ratings is input the conversion value of that channel is invalid and the conversion values of other channels also may be affected 9 AVREF0 AVREF1 pins The AVREF0 and AVREF1 pins are used to input reference voltag...

Page 647: ...n AVREF0 AVREF1 may give rise to an invalid conversion result Software processing is needed in order to prevent this invalid conversion result from adversely affecting the system The following are examples of software processing Use the average value of the results of multiple A D conversions as the A D conversion result Perform A D conversion multiple consecutive times and use conversion results ...

Page 648: ...ger Mode ITRG0 A D converter 0 ADTRG0 INTCM003 INTCM013 ITRG0 A D converter 1 ADTRG1 INTTM00 INTTM01 0 ITRG0 ITRG22 ITRG21 ITRG20 0 ITRG12 ITRG11 ITRG10 Internal bus Selector Selector Selector Selector Caution For the selection of the trigger source in timer trigger mode refer to 13 3 5 A D internal trigger selection register ITRG0 ...

Page 649: ...gister they can be read written in 8 bit or 1 bit units However writing to an ADSCMn0 register during A D conversion operation initializes conversion operation and starts the conversion over from the beginning At this time overwrite the ADSCMn0 register with the same value If writing a different value be sure to clear the ADCEn bit to 0 first before overwriting Caution Before changing the trigger ...

Page 650: ...able 1 Enable 14 ADCSn Shows status of A D converter 0 or 1 This bit is read only 0 Stopped 1 Operating The ADCSn bit is 0 for the duration of 6 fXX 2 immediately after the start of A D conversion and is then set to 1 In the scan mode this operation is performed each time the analog input pin to be A D converted is switched 12 ADMSn Specifies operation mode of A D converter 0 or 1 0 Scan mode 1 Se...

Page 651: ...nput pin number that is set by bits SANI3 to SANI0 to a smaller pin number than the conversion termination analog input pin number that is set by bits ANIS3 to ANIS0 7 to 4 SANI3 to SANI0 Specifies analog input pin in select mode In scan mode specifies conversion termination analog input pin ANIS3 ANIS2 ANIS1 ANIS0 In Select Mode In Scan Mode 0 0 0 0 ANIn0 ANIn0 0 0 0 1 ANIn1 SANI ANIn1 0 0 1 0 AN...

Page 652: ...peration is suspended and subsequently terminates 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 FR0 9 FR1 10 FR2 11 0 15 0 1 0 0 0 14 0 13 0 12 0 2 0 3 0 4 0 5 0 6 0 7 0 8 FR0 9 FR1 10 FR2 11 0 15 0 1 0 0 0 ADSCM01 Address FFFFF202H Initial value 0000H ADSCM11 Address FFFFF242H Initial value 0000H Bit Position Bit Name Function Specifies conversion time Conversion Time µs Note FR2 FR1 FR0 Conversion Cl...

Page 653: ...T CMP9 10 DET ANI0 11 DET ANI1 15 ADET EN0 1 DET CMP1 0 DET CMP0 ADETM0 Address FFFFF244H Initial value 0000H 14 ADET LH1 13 DET ANI3 12 DET ANI2 2 DET CMP2 3 DET CMP3 4 DET CMP4 5 DET CMP5 6 DET CMP6 7 DET CMP7 8 DET CMP8 9 DET CMP9 10 DET ANI0 11 DET ANI1 15 ADET EN1 1 DET CMP1 0 DET CMP0 ADETM1 Bit Position Bit Name Function 15 ADETENn Specifies voltage detection mode 0 Operate in normal mode 1...

Page 654: ...13 0 12 0 2 ADCRn2 3 ADCRn3 4 ADCRn4 5 ADCRn5 6 ADCRn6 7 ADCRn7 8 ADCRn8 9 ADCRn9 10 0 11 0 15 0 1 ADCRn1 0 ADCRn0 ADCR0n Address See Table 13 1 Initial value 0000H ADCR1n Address See Table 13 2 Initial value 0000H 14 0 13 0 12 0 2 ADCRn2 3 ADCRn3 4 ADCRn4 5 ADCRn5 6 ADCRn6 7 ADCRn7 8 ADCRn8 9 ADCRn9 10 0 11 0 15 0 1 ADCRn1 0 ADCRn0 Table 13 1 Correspondence Between ADCR0n n 0 to 7 Register Names ...

Page 655: ...espondence Between Each Analog Input Pin and ADCR0n and ADCR1n Registers A D Converter Analog Input Pin A D Conversion Result Register ANI00 ADCR00 ANI01 ADCR01 ANI02 ADCR02 ANI03 ADCR03 ANI04 ADCR04 ANI05 ADCR05 ANI06 ADCR06 A D converter 0 ANI07 ADCR07 ANI10 ADCR10 ANI11 ADCR11 ANI12 ADCR12 ANI13 ADCR13 ANI14 ADCR14 ANI15 ADCR15 ANI16 ADCR16 A D converter 1 ANI17 ADCR17 ...

Page 656: ...ger source of A D converter 1 ITRG22 ITRG21 ITRG20 ITRG10 Trigger Source 0 0 0 Select INTCM003 0 0 1 Select INTCM013 0 1 0 Select INTTM00 0 1 1 Select INTTM01 1 0 0 Select INTCM003 and INTTM00 1 0 1 Select INTCM013 and INTTM00 1 1 0 Select INTCM003 and INTTM01 1 1 1 Select INTCM013 and INTTM01 6 to 4 ITRG22 to ITRG20 Remark Arbitrary Specifies timer trigger source of A D converter 0 ITRG12 ITRG11 ...

Page 657: ... returns integer of value in VIN Analog input voltage AVREF AVREF0 or AVREF1 pin voltage ADCR Value of A D conversion result register ADCR0n or ADCR1n Figure 13 3 illustrates the relationship between the analog input voltages and A D conversion results Figure 13 3 Relationship Between Analog Input Voltages and A D Conversion Results 1023 1022 1021 3 2 1 0 Input voltage AVREFm 1 2048 1 1024 3 2048 ...

Page 658: ...nated A D Converter A D Conversion Termination Interrupt Signal 0 Generate INTAD0 1 Generate INTAD1 2 Voltage detection interrupts INTDET0 INTDET1 In voltage detection mode ADETEN0 or ADETEN1 bit of ADETM0 or ADETM1 1 the value of the ADCR0n or ADCR1n register of the relevant analog input pin is compared to the reference voltage set in the DETCMP9 to DETCMP0 bits of the ADETM0 or ADETM1 register a...

Page 659: ...es store the conversion result in the ADCR0n or ADCR1n register When the specified number of A D conversions have terminated generate an A D conversion termination interrupt INTAD0 INTAD1 n 0 to 7 Notes 1 If the ADSCM00 or ADSCM10 register is overwritten with the same value during A D conversion the A D conversion operation preceding the overwrite stops and the conversion result is not stored in t...

Page 660: ...the conversion timing of the analog input set for the ANI0n or ANI1n pin n 0 to 7 is a mode that starts A D conversion by setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1 In this mode it is necessary to set the ADCE0 or ADCE1 bit to 1 as an A D conversion restart operation after an INTAD0 or INTAD1 interrupt ADCS0 or ADCS1 0 b A D trigger polling mode A D trigger polling mode...

Page 661: ...I1n or ANI0n n 0 to 7 Figure 13 4 Example of Select Mode Operation Timing ANI01 For A D Converter 0 ANI01 input A D conversion Data 1 ANI01 Data 2 ANI01 Data 3 ANI01 Data 4 ANI01 Data 5 ANI01 Data 6 ANI01 Data 7 ANI01 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 1 ANI01 Data 2 ANI01 Data 3 ANI01 Data 4 ANI01 Data 6 ANI01 ADCR01 register INTAD0 interrupt Conversion start ADSCM0 register se...

Page 662: ... interrupt INTAD0 or INTAD1 Figure 13 5 Example of Scan Mode Operation Timing For A D Converter 0 4 Channel Scan ANI00 to ANI03 ANI00 input ANI01 input ANI02 input ANI03 input A D conversion Data 1 ANI00 Data 2 ANI01 Data 3 ANI02 Data 4 ANI03 Data 5 ANI00 Data 6 ANI01 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 1 ANI00 ADCR00 Data 2 ANI01 ADCR01 Data 3 ANI02 ADCR02 Data 4 ANI03 ADCR03 Data 5 AN...

Page 663: ...s generated for each A D conversion termination which terminates A D conversion ADCS0 or ADCS1 bit 0 Analog Input A D Conversion Result Register ANIx ADCRx Remark x 00 to 07 10 to 17 To restart A D conversion write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register This is optimal for an application that reads a result for each A D conversion Figure 13 6 Example of Select Mode A D Trig...

Page 664: ...of ADSCM00 or ADSCM10 register Be sure to set a pin number that is smaller than the conversion termination analog input pin number set according to Note 2 2 Set using ANIS3 to ANIS0 bits of ADSCM00 or ADSCM10 register Remark x 00 to 07 10 to 17 To restart A D conversion write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register This is optimal for an application that regularly monitors m...

Page 665: ...r each A D conversion termination A D conversion operation is repeated until the ADCE0 or ADCE1 bit 0 ADCS0 or ADCS1 bit 1 Analog Input A D Conversion Result Register ANIx ADCRx Remark x 00 to 07 10 to 17 In A D trigger polling mode it is not necessary to write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register as an A D conversion restart operation Note This is optimal for application...

Page 666: ...M00 or ADSCM10 register Remark x 00 to 07 10 to 17 It is not necessary to write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register as an A D conversion restart operation in A D trigger polling mode Note This is optimal for applications that regularly read A D conversion values Note In A D trigger polling mode the fact that the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register is 0 ...

Page 667: ...ADCR1n register corresponding to the analog input n 0 to 7 An A D conversion termination interrupt INTAD0 or INTAD1 is generated for each A D conversion which terminates A D conversion ADCS0 or ADCS1 0 This is optimal for applications that read A D conversion values synchronized to a timer trigger Trigger Analog Input A D Conversion Result Register Interrupt specified by ITRG0 register ANIx ADCRx ...

Page 668: ... Register ANIn0 ADCRn0 ANIn1 ADCRn1 ANIn2 ADCRn2 ANIn3 ADCRn3 ANIn4 ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 Interrupt specified by ITRG0 register ANIn7 ADCRn7 Remark n 0 1 After all of the specified A D conversions terminate the A D converter changes to trigger wait status ADCE0 or ADCE1 1 It performs A D conversion operation again when the interrupt signal specified in the ITRG0 register occurs Figure 1...

Page 669: ... is A D converted and the result is stored in one ADCR0n or ADCR1n register Analog inputs correspond one to one with A D conversion result registers For each A D conversion an A D conversion termination interrupt INTAD0 or INTAD1 is generated which terminates A D conversion ADCS0 or ADCS1 bit 0 Trigger Analog Input A D Conversion Result Register ADTRGm signal ANImn ADCRmn Remark m 0 1 n 0 to 7 To ...

Page 670: ... ADCRn4 ANIn5 ADCRn5 ANIn6 ADCRn6 ADTRGn signal ANIn7 ADCRn7 Remark n 0 1 After all specified A D conversions terminate A D conversion is restarted when an external trigger signal occurs This is optimal for applications that regularly monitor multiple analog inputs in synchronization with an external trigger Figure 13 13 Example of Scan Mode External Trigger Scan Operation For A D Converter 0 a Wh...

Page 671: ...l or timer trigger is input during A D conversion operation that trigger input is ignored 3 When interval conversion time If an external or timer trigger is input at the same time as A D conversion termination comparison termination signal and trigger contention interrupt generation and ADCR0n or ADCR1n register storage of the value with which conversion terminated are performed correctly n 0 to 7...

Page 672: ...he timing of the stop of operation of the A D converter conflict the A D conversion value may be undefined Because of this be sure to read the A D conversion result while the A D converter is in operation Furthermore when reading an A D conversion result after the A D converter operation has stopped be sure to have done so by the time the next conversion result is complete The conversion result re...

Page 673: ...ng formula regardless of the resolution 1 FSR Max value of analog input voltage that can be converted Min value of analog input voltage that can be converted 100 AVREFn 0 100 AVREFn 100 Remark n 0 1 1LSB is as follows when the resolution is 10 bits 1LSB 1 2 10 1 1024 0 098 FSR Accuracy has no relation to resolution but is determined by overall error 2 Overall error This shows the maximum error val...

Page 674: ...ro scale error full scale error integral linearity error and differential linearity error in the characteristics table Figure 13 17 Quantization Error 0 0 1 1 Digital output Quantization error 1 2LSB 1 2LSB Analog input 0 AVREFn n 0 1 4 Zero scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value 1 2LSB when the digital outpu...

Page 675: ... 111 Figure 13 19 Full Scale Error 100 011 010 000 0 AVREFn AVREFn 1 AVREFn 2 AVREFn 3 Digital output Lower 3 bits Analog input LSB Full scale error 111 n 0 1 6 Differential linearity error While the ideal width of code output is 1LSB this indicates the difference between the actual measurement value and the ideal value Figure 13 20 Differential Linearity Error 0 AVREFn n 0 1 Digital output Analog...

Page 676: ...e error are 0 Figure 13 21 Integral Linearity Error 0 AVREFn n 0 1 Digital output Analog input Integral linearity error Ideal line 1 1 0 0 8 Conversion time This expresses the time from when the analog input voltage was applied to the time when the digital output was obtained The sampling time is included in the conversion time in the characteristics table 9 Sampling time This is the time the anal...

Page 677: ...ly ports The port configuration is shown below Port DH P00 P07 P10 P15 P20 P27 P30 P37 P40 P47 PDH0 PDH7 PDL0 PDL15 PCS0 PCS7 PCT0 PCT7 PCM0 PCM4 Port DL Port CS Port CT Port CM Port 0 Port 1 Port 2 Port 3 Port 4 1 Functions of each port The V850E IA1 has the ports shown below Any port can operate in 8 bit or 1 bit units and can provide a variety of controls Moreover besides its function as a port...

Page 678: ...level for the signal output in the control mode in the corresponding bits of port n n 0 to 4 CM CS CT DH and DL 2 Switch to the control mode using the port n mode control register PMCn If 1 above is not performed the contents of port n may be output for a moment when switching from the port mode to the control mode 2 When port manipulation is performed by a bit manipulation instruction SET1 CLR1 o...

Page 679: ...TO10 P10 Input mode PMC1 PFC1 P11 TCUD10 INTP100 P11 Input mode P12 TCLR10 INTP101 P12 Input mode PMC1 P13 TIUD11 TO11 P13 Input mode PMC1 PFC1 P14 TCUD11 INTP110 P14 Input mode Port 1 P15 TCLR11 INTP111 P15 Input mode PMC1 P20 TI2 INTP20 P20 Input mode PMC2 P21 TO21 INTP21 P21 Input mode P22 TO22 INTP22 P22 Input mode P23 TO23 INTP23 P23 Input mode P24 TO24 INTP24 P24 Input mode PMC2 PFC2 P25 TCL...

Page 680: ...AIT PCM0 Input mode WAIT PCM1 CLKOUT PCM1 Input mode CLKOUT PCM2 HLDAK PCM2 Input mode HLDAK PCM3 HLDRQ PCM3 Input mode HLDRQ PMCCM Port CM PCM4 PCM4 Input mode PCT0 LWR PCT0 Input mode LWR PCT1 UWR PCT1 Input mode UWR PMCCT PCT2 PCT2 Input mode PCT3 PCT3 Input mode PCT4 RD PCT4 Input mode RD PMCCT PCT5 PCT5 Input mode PCT6 ASTB PCT6 Input mode ASTB PMCCT Port CT PCT7 PCT7 Input mode Port CS PCS0 ...

Page 681: ...er s Manual U14492EJ3V0UD 3 Port block diagrams Figure 14 1 Type A Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Output signal in control mode Pmn Address Internal bus Selector Selector Selector Remark m Port number n Bit number ...

Page 682: ...r s Manual U14492EJ3V0UD Figure 14 2 Type B Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Noise elimination Edge detection Input signal in control mode Internal bus Selector Selector Remark m Port number n Bit number ...

Page 683: ...FUNCTIONS 683 User s Manual U14492EJ3V0UD Figure 14 3 Type C Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Input signal in control mode Internal bus Selector Selector Remark m Port number n Bit number ...

Page 684: ...RPM WRPORT RDIN PMmn WRPMC PMCmn Pmn Pmn MODE0 to MODE2 Address Input signal in control mode Selector Selector Internal bus Remark m Port number n Bit number Figure 14 5 Type E Block Diagram WRPORT RDIN WRPM Pmn Pmn PMmn Address Selector Selector Internal bus Remark m Port number n Bit number ...

Page 685: ...m RDIN Pmn Address Noise elimination Edge detection 1 Input signal in control mode Internal bus Selector Figure 14 7 Type G Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Output signal in control mode Pmn Address Internal bus Selector Selector Selector Remark m Port number n Bit number ...

Page 686: ...FUNCTIONS 686 User s Manual U14492EJ3V0UD Figure 14 8 Type H Block Diagram Internal bus Selector Selector WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Input signal in control mode Remark m Port number n Bit number ...

Page 687: ... User s Manual U14492EJ3V0UD Figure 14 9 Type J Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Output signal in control mode Pmn Address Internal bus Selector Selector Selector MODE0 to MODE2 Remark m Port number n Bit number ...

Page 688: ...e M Block Diagram WRPMC WRPM WRPORT RDIN PMCmn PMmn Pmn Pmn Address Input signal in control mode Output signal in control mode SCKx ASCKy output enable signal Internal bus Selector Selector Selector Remark mn 34 37 42 45 x 0 When mn 42 1 When mn 45 y 1 When mn 34 2 When mn 37 ...

Page 689: ...igure 14 11 Type N Block Diagram WRPFC WRPMC WRPM WRPORT RDIN PFCmn PMCmn PMmn Pmn Pmn Address Input signal in control mode Output signal in control mode Noise elimination Edge detection Internal bus Selector Selector Selector Remark m Port number n Bit number ...

Page 690: ...D Figure 14 12 Type O Block Diagram WRPM WRPORT RDIN PMmn WRPMC PMCmn Pmn Pmn Output signal in control mode MODE0 to MODE2 I O control I O control Address Input signal in control mode Selector Selector Internal bus Selector Remark m Port number n Bit number ...

Page 691: ...s Manual U14492EJ3V0UD Figure 14 13 Type P Block Diagram WRPM WRPORT RDIN PMmn WRPMC PMCmn Pmn Pmn MODE0 to MODE2 Output signal in control mode I O control Address Selector Selector Internal bus Selector Remark m Port number n Bit number ...

Page 692: ...input Although this port also serves as NMI ESO0 INTP0 ESO1 INTP1 ADTRG0 INTP2 ADTRG1 INTP3 and INTP4 to INTP6 NMI ESO0 INTP0 ESO1 INTP1 ADTRG0 INTP2 ADTRG1 INTP3 and INTP4 to INTP6 cannot be switched with input port The status of each pin is read by reading the port 1 Operation in control mode Port Alternate Pin Name Remarks Block Type P00 NMI Non maskable interrupt request input P01 ESO0 INTP0 P...

Page 693: ...1 Real time pulse unit RPU input or external interrupt request input B P13 TIUD11 TO11 Real time pulse unit RPU I O N P14 TCUD11 INTP110 Port 1 P15 TCLR11 INTP111 Real time pulse unit RPU input or external interrupt request input B 2 Setting in I O mode and control mode Port 1 is set in I O mode using the port 1 mode register PM1 In control mode it is set using the port 1 mode control register PMC...

Page 694: ... Function 5 PMC15 Specifies operation mode of P15 pin 0 I O port mode 1 TCLR11 input mode or external interrupt request INTP111 input mode 4 PMC14 Specifies operation mode of P14 pin 0 I O port mode 1 TCUD11 input mode or external interrupt request INTP110 input mode 3 PMC13 Specifies operation mode of P13 pin 0 I O port mode 1 TIUD11 input mode or TO11 output mode 2 PMC12 Specifies operation mode...

Page 695: ... mode is specified by the port 1 mode control register PMC1 the setting of this register is invalid 7 0 PFC1 6 0 5 0 4 0 3 PFC13 2 0 1 0 0 PFC10 Address FFFFF462H Initial value 00H Bit Position Bit Name Function 3 PFC13 Specifies operation mode of P13 pin in control mode 0 TIUD11 input mode 1 TO11 output mode 0 PFC10 Specifies operation mode of P10 pin in control mode 0 TIUD10 input mode 1 TO10 ou...

Page 696: ...to TO24 INTP24 Real time pulse unit RPU output or external interrupt request input N P25 TCLR2 INTP25 P26 TI3 TCLR3 INTP30 Real time pulse unit RPU input or external interrupt request input B Port 2 P27 TO3 INTP31 Real time pulse unit RPU output or external interrupt request input N 2 Setting in I O mode and control mode Port 2 is set in I O mode using the port 2 mode register PM2 In control mode ...

Page 697: ...ame Function 7 PMC27 Specifies operation mode of P27 pin 0 I O port mode 1 TO3 output mode or external interrupt request INTP31 input mode 6 PMC26 Specifies operation mode of P26 pin 0 I O port mode 1 RPU TI3 TCLR3 input mode or external interrupt request INTP30 input mode 5 PMC25 Specifies operation mode of P25 pin 0 I O port mode 1 TCLR2 input mode or external interrupt request INTP25 input mode...

Page 698: ...MC2 the setting of this register is invalid 7 PFC27 PFC2 6 0 5 0 4 PFC24 3 PFC23 2 PFC22 1 PFC21 0 0 Address FFFFF464H Initial value 00H Bit Position Bit Name Function 7 PFC27 Specifies operation mode of P27 pin in control mode 0 External interrupt request INTP31 input mode 1 TO3 output mode 4 to 1 PFC24 to PFC21 Specify operation mode of P24 to P21 pins in control mode 0 External interrupt reques...

Page 699: ...Pin Name Remarks Block Type P30 RXD0 H P31 TXD0 G P32 RXD1 C P33 TXD1 A P34 ASCK1 M P35 RXD2 C P36 TXD2 A Port 3 P37 ASCK2 Serial interface UART0 to UART2 I O M 2 Setting in I O mode and control mode Port 3 is set in I O mode using the port 3 mode register PM3 In control mode it is set using the port 3 mode control register PMC3 a Port 3 mode register PM3 This register can be read written in 8 bit...

Page 700: ... I O mode 6 PMC36 Specifies operation mode of P36 pin 0 I O port mode 1 TXD2 output mode 5 PMC35 Specifies operation mode of P35 pin 0 I O port mode 1 RXD2 input mode 4 PMC34 Specifies operation mode of P34 pin 0 I O port mode 1 ASCK1 I O mode 3 PMC33 Specifies operation mode of P33 pin 0 I O port mode 1 TXD1 output mode 2 PMC32 Specifies operation mode of P32 pin 0 I O port mode 1 RXD1 input mode...

Page 701: ...te Pin Name Remarks Block Type P40 SI0 C P41 SO0 A P42 SCK0 M P43 SI1 C P44 SO1 A P45 SCK1 M P46 CRXD C Port 4 P47 CTXD Serial interface CSI0 CSI1 FCAN I O A 2 Setting in I O mode and control mode Port 4 is set in I O mode using the port 4 mode register PM4 In control mode it is set using the port 4 mode control register PMC4 a Port 4 mode register PM4 This register can be read written in 8 bit or...

Page 702: ...XD output mode 6 PMC46 Specifies operation mode of P46 pin 0 I O port mode 1 CRXD input mode 5 PMC45 Specifies operation mode of P45 pin 0 I O port mode 1 SCK1 I O mode 4 PMC44 Specifies operation mode of P44 pin 0 I O port mode 1 SO1 output mode 3 PMC43 Specifies operation mode of P43 pin 0 I O port mode 1 SI1 input mode 2 PMC42 Specifies operation mode of P42 pin 0 I O port mode 1 SCK0 I O mode ...

Page 703: ...ion in control mode Port Alternate Pin Name Remarks Block Type Port DH PDH7 to PDH0 A23 to A16 Memory expansion address bus P 2 Setting in I O mode and control mode Port DH is set in I O mode using the port DH mode register PMDH In control mode it is set using the port DH mode control register PMCDH a Port DH mode register PMDH This register can be read written in 8 bit or 1 bit units 7 PMDH7 PMDH...

Page 704: ... or 1 bit units 7 PMCDH7 PMCDH 6 PMCDH6 5 PMCDH5 4 PMCDH4 3 PMCDH3 2 PMCDH2 1 PMCDH1 0 PMCDH0 Address FFFFF046H Initial valueNote 00H FFH Note 00H Single chip mode 0 FFH Single chip mode 1 ROMless mode 0 or 1 Bit Position Bit Name Function 7 to 0 PMCDHn n 7 to 0 Specifies operation mode of PDHn pin 0 I O port mode 1 A23 to A16 output mode ...

Page 705: ... PDL6 5 PDL5 4 PDL4 3 PDL3 2 PDL2 1 PDL1 0 PDL0 Address FFFFF005H Initial value Undefined Address FFFFF004H Bit Position Bit Name Function 15 to 0 PDLn n 15 to 0 I O port Besides functioning as a port in control mode this can operate as an address data bus when memory is expanded externally 1 Operation in control mode Port Alternate Pin Name Remarks Block Type Port DL PDL15 to PDL0 AD15 to AD0 Mem...

Page 706: ...utput mode of PDLn pin 0 Output mode output buffer on 1 Input mode output buffer off b Port DL mode control register PMCDL The PMCDL register can be read written in 16 bit units When using the higher 8 bits of the PMCDL register as the PMCDLH register and the lower 8 bits as the PMCDLL register it can be read written in 8 bit or 1 bit units 15 PMCDL15 PMCDL 14 PMCDL14 13 PMCDL13 12 PMCDL12 11 PMCD...

Page 707: ...3 PCS3 2 PCS2 1 PCS1 0 PCS0 Address FFFFF008H Initial value Undefined Bit Position Bit Name Function 7 to 0 PCSn n 7 to 0 I O port Besides functioning as a port in control mode this can operate as the chip select signal output when memory is expanded externally 1 Operation in control mode Port Alternate Pin Name Remarks Block Type Port CS PCS7 to PCS0 CS0 to CS7 Chip select signal output J ...

Page 708: ...FFF028H Initial value FFH Bit Position Bit Name Function 7 to 0 PMCSn n 7 to 0 Specifies input output mode of PCSn pin 0 Output mode output buffer on 1 Input mode output buffer off b Port CS mode control register PMCCS This register can be read written in 8 bit or 1 bit units 7 PMCCS7 PMCCS 6 PMCCS6 5 PMCCS5 4 PMCCS4 3 PMCCS3 2 PMCCS2 1 PMCCS1 0 PMCCS0 Address FFFFF048H Initial valueNote 00H FFH N...

Page 709: ...PCT1 UWR Write strobe signal output J PCT2 PCT3 Fixed in port mode E PCT4 RD Read strobe signal output J PCT5 Fixed in port mode E PCT6 ASTB Address strobe signal output J Port CT PCT7 Fixed in port mode E 2 Setting in I O mode and control mode Port CT is set in I O mode using the port CT mode register PMCT In control mode it is set using the port CT mode control register PMCCT a Port CT mode regi...

Page 710: ...valueNote 00H 53H Note 00H Single chip mode 0 53H Single chip mode 1 ROMless mode 0 or 1 Bit Position Bit Name Function 6 PMCCT6 Specifies operation mode of PCT6 pin 0 I O port mode 1 ASTB output mode 4 PMCCT4 Specifies operation mode of PCT4 pin 0 I O port mode 1 RD output mode 1 PMCCT1 Specifies operation mode of PCT1 pin 0 I O port mode 1 UWR output mode 0 PMCCT0 Specifies operation mode of PCT...

Page 711: ... Block Type PCM0 WAIT Wait insertion signal input D PCM1 CLKOUT Internal system clock output J PCM2 HLDAK Bus hold acknowledge signal output J PCM3 HLDRQ Bus hold request signal input D Port CM PCM4 Fixed in port mode E 2 Setting in I O mode and control mode Port CM is set in I O mode using the port CM mode register PMCM In control mode it is set using the port CM mode control register PMCCM a Por...

Page 712: ...ueNote 00H 0FH Note 00H Single chip mode 0 0FH Single chip mode 1 ROMless mode 0 or 1 Bit Position Bit Name Function 3 PMCCM3 Specifies operation mode of PCM3 pin 0 I O port mode 1 HLDRQ input mode 2 PMCCM2 Specifies operation mode of PCM2 pin 0 I O port mode 1 HLDAK output mode 1 PMCCM1 Specifies operation mode of PCM1 pin 0 I O port mode 1 CLKOUT output mode 0 PMCCM0 Specifies operation mode of ...

Page 713: ...t that changes in less than these elimination times is not accepted internally Pin Noise Elimination Time P00 NMI P01 ESO0 INTP0 P02 ESO1 INTP1 P03 ADTRG0 INTP2 P04 ADTRG1 INTP3 P05 INTP4 to P07 INTP6 Analog delay Approx 10 ns Cautions 1 The above non maskable maskable interrupt pins are used to release standby mode A clock control timing circuit is not used since the internal system clock is stop...

Page 714: ...10 INTP100 P12 TCLR10 INTP101 Timer 11 P13 TIUD11 TO11 P14 TCUD11 INTP110 P15 TCLR11 INTP111 Select from fXXTM10 11 fXXTM10 11 2 fXXTM10 11 4 fXXTM10 11 8 P26 TI3 INTP30 TCLR3 Select from fXXTM3 2 fXXTM3 4 fXXTM3 8 fXXTM3 16 Timer 3 P27 TO3 INTP31 4 to 5 clocks Select from fXXTM3 32 fXXTM3 64 fXXTM3 128 fXXTM3 256 Cautions 1 Since the above pin noise filtering uses clock sampling input signals are...

Page 715: ...o 3 rising edge detection Timers 1 to 3 falling edge detection 2 clocks 2 clocks 5 clocks 5 clocks 4 clocks 4 clocks 3 clocks 3 clocks Caution If there are three or less noise elimination clocks while the timers 1 to 3 input signals are high level or low level the input pulse is eliminated as noise If it is sampled at least four times the edge is detected as valid input ...

Page 716: ...k 0 0 fXXTM10 8 0 1 fXXTM10 4 1 0 fXXTM10 2 1 1 fXXTM10 1 0 NRC101 NRC100 Remark fXXTM10 Clock of TM10 selected by PRM02 register 2 Timer 11 noise elimination time selection register NRC11 The NRC11 register is used to set the clock source of timer 11 input pin noise elimination times This register can be read written in 8 bit or 1 bit units 7 0 NRC11 6 0 5 0 4 0 3 0 2 0 1 NRC111 0 NRC110 Address ...

Page 717: ...C32 1 NRC31 0 NRC30 Address FFFFF698H Initial value 00H Bit Position Bit Name Function Selects the TO3 INTP31 pin noise elimination clock NRC33 NRC32 Noise elimination clock 0 0 fXXTM3 256 0 1 fXXTM3 128 1 0 fXXTM3 64 1 1 fXXTM3 32 3 2 NRC33 NRC32 Remark fXXTM3 Clock selected by PRM03 register Selects the TI3 INTP30 TCLR3 pin noise elimination clock NRC31 NRC30 Noise elimination clock 0 0 fXXTM3 1...

Page 718: ...tal Filter Pin Analog Filter Noise Elimination Time Noise Elimination Time Sampling Clock P20 TI2 INTP20 P21 TO21 INTP21 to P24 TO24 INTP24 P25 TCLR2 INTP25 10 to 100 ns 4 to 5 clocks fXXTM2 Cautions 1 Since digital filtering uses clock sampling if it is selected input signals are not received when the CPU clock is stopped 2 The noise eliminator is valid only in control mode 3 Refer to Figure 14 1...

Page 719: ...occur as soon as the PMC2 register is set n 0 to 5 1 2 7 DFEN00 FEM0 6 0 5 0 4 0 3 EDGE010 2 EDGE000 1 TMS010 0 TMS000 Address FFFFF630H Initial value 00H Address FFFFF631H Initial value 00H Address FFFFF632H Initial value 00H Address FFFFF633H Initial value 00H Address FFFFF634H Initial value 00H Address FFFFF635H Initial value 00H INTP20 7 DFEN01 6 0 5 0 4 0 3 EDGE011 2 EDGE001 1 TMS011 0 TMS001...

Page 720: ...eliminator specification 1 0 Capture to sub channel 1 according to timer 1 1 Capture to sub channel 2 according to timer 1 0 TMS01n TMS00n Note Capture input according to INTCM100 and INTCM101 can be selected only for the FEM1 and FEM2 registers Set the values of the TMS01m and TMS00m bits in the FEMm register to 00B or 01B Settings other than these are prohibited m 1 3 to 5 Capture according to I...

Page 721: ...pull down resistor must be attached to each pin of ports DH DL CS CT and CM If there are no resistors the external memory that is connected may be destroyed when these pins become high impedance Similarly perform pin processing so that on chip peripheral I O function signal output and output ports are not affected Note In ROMless mode 0 or 1 and single chip mode 1 CLKOUT signals also are output du...

Page 722: ...ternal system reset signal continues in active status for a period of at least 4 system clocks after the timing of a reset release by the RESET pin 2 Reset at power on A reset operation at power on power supply application must guarantee oscillation stabilization time from power on until reset acknowledgment due to the low level width of the RESET signal RESET input VDD3 VDD5 Reset release Analog ...

Page 723: ...2C11H Peripheral area selection control register BPC 0000H Bus size configuration register BSC 0000H 5555H Bus control function System wait control register VSWC 77H Bus cycle type configuration register n BCTn n 0 1 CCCCH Data wait control register n DWCn n 0 1 3333H Address wait control register AWC 0000H Memory control function Bus cycle control register BCC AAAAH DMA source address register nL...

Page 724: ...PHS 00H Dead time timer reload register n DTRRn n 0 1 0FFFH Buffer registers CM0n CM1n BFCM0n BFCM1n n 0 to 3 FFFFH Timer control register 0n TMC0n n 0 1 0508H Timer control register 0nL TMC0nL n 0 1 08H Timer control register 0nH TMC0nH n 0 1 05H Timer unit control register 0n TUC0n n 0 1 01H Timer output mode register n TOMRn n 0 1 00H PWM software timing output register n PSTOn n 0 1 00H PWM ou...

Page 725: ...0H Timer 2 output control register 0H OCTLE0H 00H Timer 2 sub channel 0 5 capture compare control register CMSE050 0000H Timer 2 sub channel 1 2 capture compare control register CMSE120 0000H Timer 2 sub channel 3 4 capture compare control register CMSE340 0000H Timer 2 sub channel n sub capture compare register CVSEn0 n 1 to 4 0000H Timer 2 sub channel n main capture compare register CVPEn0 n 1 t...

Page 726: ... SIRBELn n 0 1 00H Clocked serial interface initial transmission buffer register n SOTBFn n 0 1 0000H Clocked serial interface initial transmission buffer register Ln SOTBFLn n 0 1 00H Serial I O shift register n SIOn n 0 1 0000H Serial I O shift register Ln SIOLn n 0 1 00H Prescaler mode register PRSM3 00H Serial interface function CSI0 CSI1 Prescaler compare register PRSCM3 00H Asynchronous seri...

Page 727: ...er CGINTP 00H CAN1 interrupt pending register C1INTP 00H CAN stop register CSTOP 0000H CAN global status register CGST 0100H CAN global interrupt enable register CGIE 0A00H CAN main clock selection register CGCS 7F05H CAN time stamp count register CGTSC 0000H CAN message search start result register CGMSS on write CGMSR on read 0000H CAN1 address mask n register L H C1MASKLn C1MASKHn n 0 to 3 Unde...

Page 728: ...MCDL 0000H FFFFH Mode control register PMCDLL 00H FFH Mode control register PMCDLH 00H FFH Mode control register PMCCT 00H 53H Mode control register PMCCM 00H 0FH Port function Function control registers PFC1 PFC2 00H RAM access data buffer register L NBDL 0000H RAM access data buffer register LL NBDLL 00H RAM access data buffer register LU NBDLU 00H RAM access data buffer register H NBDH 0000H RA...

Page 729: ...arget system Small scale production of various models is made easier by differentiating software Data adjustment in starting mass production is made easier 16 1 Features All area batch erase or erase in area units 128 KB Communication through serial interface from the dedicated flash programmer Erase write voltage VPP 7 8 V On board programming Flash memory programming is possible by the self prog...

Page 730: ... VDD3 53 128 VDD3 53 128 LVDDNote 3 CVDD 21 CVDD 21 VDD5 56 91 125 VDD5 56 91 125 AVREF0 137 AVREF0 137 AVREF1 4 AVREF1 4 MODE1 27 MODE1 27 VDD AVDD 2 135 AVDD 2 135 VSS3 54 127 VSS3 54 127 VSS5 55 90 126 VSS5 55 90 126 AVSS 3 136 AVSS 3 136 CVSS 22 CVSS 22 MODE0 26 MODE0 26 MODE2 28 MODE2 28 GND NMI P00 111 NMI P00 111 Note 4 CKSEL 25 CKSEL 25 Notes 1 Configure the oscillator on the FA 144GJ 8EU ...

Page 731: ...nterface between the dedicated flash programmer and the V850E IA1 to perform writing erasing etc A dedicated program adapter FA Series is required for off board writing Supply the operating clock of the V850E IA1 via the oscillator configured on the V850E IA1 board using a resonator and a capacitor 16 4 Communication Mode 1 UART0 Transfer rate 4 800 bps to 76 800 bps LSB first Figure 16 2 Communic...

Page 732: ...the V850E IA1 board using a resonator and a capacitor The dedicated flash programmer outputs transfer clocks and the V850E IA1 operates as a slave 3 Handshake supported CSI communication Transfer rate up to 2 MHz MSB first Figure 16 4 Communication with Dedicated Flash Programmer Handshake Supported CSI Communication V850E IA1 Dedicated flash programmer RESET RESET SO SI SO0 SI0 PDH0 SCK SCK0 HS V...

Page 733: ...gramming mode 7 8 V writing voltage is supplied to the VPP pin The following shows an example of the connection of the VPP pin Figure 16 5 Connection Example of VPP Pin V850E IA1 VPP Pull down resistor RVPP 4 7 to 47 kΩ Dedicated flash programmer connection pin 16 5 2 Serial interface pin The following shows the pins used by each serial interface Table 16 2 Pins Used by Each Serial Interface Seria...

Page 734: ... input or output connected to another device input the signal output to the other device may cause the device to malfunction To avoid this isolate the connection to the other device or make the setting so that the input signal to the other device is ignored Figure 16 7 Malfunction of Other Device V850E IA1 Pin Input pin Other device Dedicated flash programmer connection pin In the flash memory pro...

Page 735: ...he signal the dedicated flash programmer outputs Therefore isolate the signals on the reset signal generator side 16 5 4 NMI pin Do not change the input signal to the NMI pin in flash memory programming mode If it is changed in flash memory programming mode programming may not be performed correctly 16 5 5 MODE0 to MODE2 pins To shift to the flash memory programming mode set MODE0 to high level or...

Page 736: ...S3 VDD5 and VSS5 VDD of the dedicated flash programmer is provided with a power supply monitoring function Note Connect VDD after converting the power supply to 3 3 V using a regulator 16 6 Programming Method 16 6 1 Flash memory control The following shows the procedure for manipulating the flash memory Figure 16 9 Flash Memory Manipulating Procedure Start Switch to flash memory programming mode S...

Page 737: ...ash Memory Programming Mode n 1 Flash memory programming mode MODE0 to MODE2 010 011 7 8 V VPP 3 3 V 0 V RESET 2 16 6 3 Selection of communication mode In the V850E IA1 a communication mode is selected by inputting pulses 16 pulses max to VPP pin after switching to the flash memory programming mode The VPP pulse is generated by the dedicated flash programmer The following shows the relationship be...

Page 738: ...erify command Compares the contents of the specified area and the input data Batch erase command Erases the contents of the entire memory Area erase command Erases the contents of the specified area Erase Write back command Writes back the contents which were erased Batch blank check command Checks the erase state of the entire memory Blank check Area blank check command Checks the erase state of ...

Page 739: ...self programming Self programming implements erasure and writing of the flash memory by calling the self programming function device s internal processing on the program placed in the block 0 space 000000H to 1FFFFFH and areas other than internal ROM area To place the program in the block 0 space and internal ROM area copy the program to areas other than 000000H to 1FFFFFH e g internal RAM area an...

Page 740: ...mory area in which an over erase occurred Acquire information Flash memory information read Reads out information about flash memory 16 7 3 Outline of self programming interface To execute self programming using the self programming interface the environmental conditions of the hardware and software for manipulating the flash memory must be satisfied It is assumed that the self programming interfa...

Page 741: ... flash memory a high voltage must be applied to the VPP pin To execute self programming a circuit that can generate a write voltage VPP and that can be controlled by software is necessary on the application system An example of a circuit that can select a voltage to be applied to the VPP pin by manipulating a port is shown below Figure 16 14 Example of Self Programming Circuit Configuration VDD 3 ...

Page 742: ...sh memory starts until manipulation is complete Cautions 1 Apply 0 V to the VPP pin when reset is released 2 Implement self programming in single chip mode 0 or 1 3 Apply the voltage to the VPP pin in the entry program 4 If both writing and erasing are executed by using the self programming function and flash memory programmer on the target board be sure to communicate with the programmer using CS...

Page 743: ...l timer while the flash memory is being manipulated Because the internal timer is initialized after the flash memory has been used initialize the timer with the application program to use the timer again Stopping reset signal input Do not input the reset signal while the flash memory is being manipulated If the reset signal is input while the flash memory is being manipulated the contents of the f...

Page 744: ...e function numbers are used as parameters when the device internal processing is called Table 16 8 Self Programming Function Number Function No Function Name 0 Acquiring flash information 1 Erasing area 2 to 4 RFU 5 Area write back 6 to 8 RFU 9 Erase byte verify 10 Erase verify 11 to 15 RFU 16 Continuous write in word units 17 to 19 RFU 20 Pre write 21 Internal verify Other Prohibited Remark RFU R...

Page 745: ...Verify start address Number of bytes to be verified 0 Normal completion Other than 0 Error Erase verify 10 None acts on erase manipulation area immediately before 0 Normal completion Other than 0 Error Continuous write in word unitsNote 2 16 Write start addressNote 3 Start address of write source dataNote 3 Number of words to be written word units 0 Normal completion Other than 0 Error Pre write 2...

Page 746: ...xample If write back time is 1 ms 1 1 000 100 10 integer operation ep 0x10 2 bytes Input Timer set value for creating internal operation unit time unsigned 2 bytes Write a set value that makes the value of timer 4 the internal operation unit time 100 µs Set value Operating frequency Hz 1 000 000 Internal operation unit time µs Timer division ratio 4 1Note 4 Example If the operating frequency is 50...

Page 747: ...ormation For the flash information acquisition function function No 0 the option number r7 to be specified and the contents of the return value r10 are as follows To acquire all flash information call the function as many times as required in accordance with the format shown below Table 16 12 Flash Information Option No r7 Return Value r10 0 Specification prohibited 1 Specification prohibited 2 Bi...

Page 748: ...rea number The area numbers and memory map of the µPD70F3116 are shown below Figure 16 16 Area Configuration Area 1 128 KB Area 0 128 KB 0 x 3 F F F F End address of area 1 0 x 0 0 0 0 0 Start address of area 0 0 x 2 0 0 0 0 Start address of area 1 0 x 1 F F F F End address of area 0 ...

Page 749: ...bles disables writing erasing on chip flash memory When this bit is 1 writing erasing on chip flash memory is disabled even if a high voltage is applied to the VPP pin 0 Enables writing erasing flash memory 1 Disables writing erasing flash memory 2 VPP Indicates the voltage applied to the VPP pin reaches the writing enabled level read only This bit is used to check whether writing is possible or n...

Page 750: ...0 FLPMC r0 5 NOP 6 NOP 7 NOP 8 NOP 9 NOP 10 LDSR rY 5 Remark rX Value written to the PSW rY Value returned to the PSW No special sequence is required for reading a specific register Cautions 1 If an interrupt is acknowledged between when PHCMD is issued 3 and writing to a specific register 4 immediately after issuing PHCMD writing to the specific register may not be performed and a protection erro...

Page 751: ...ng flash memory FLSPM bit 0 to select normal operation mode 7 Wait for the internal manipulation setup time see 16 7 13 5 Internal manipulation setup parameter 1 Parameter r6 First argument sets a self programming function number r7 Second argument r8 Third argument r9 Fourth argument ep First address of RAM parameter 2 Return value r10 Return value return value from device internal processing of ...

Page 752: ... manipulation setup parameter EntryProgram add 4 sp Prepare st w lp 0 sp Save return address movea lo 0x00a0 r0 r10 ldsr r10 5 PSW NP ID mov lo 0x0002 r10 st b r10 PHCMD r0 PHCMD 2 st b r10 FLPMC r0 VPPDIS 0 FLSPM 1 nop nop nop nop nop movea lo 0x0020 r0 r10 ldsr r10 5 PSW ID trap 0x1f Device Internal Process movea lo 0x00a0 r0 r6 ldsr r6 5 PSW NP ID mov lo 0x08 r6 st b r6 PHCMD r0 PRCMD 8 st b r6...

Page 753: ... flash memory In the program example in 4 above the elapse of this wait time is ensured by setting ISETUP to 130 50 MHz operation The total number of execution clocks in this example is 39 clocks divh instruction 35 clocks add instruction 1 clock jne instruction 3 clocks Ensure that a wait time of 100 µs elapses by using the following expression 39 clocks total number of execution clocks 20 ns 50 ...

Page 754: ...or Set RAM parameter Mask interrupts Pre write Erase area Erase byte verify Erase verify Area write back Erase verify Clear number of times write back is repeated Erase byte verify Write error Undererase Maximum number of times of repeating erasure is exceeded Maximum number of times of repeating write back is exceeded Overerase Overerase Undererase Set VPP voltage Clear VPP voltage Unmask interru...

Page 755: ...rite data in word units is illustrated below The processing of each function number must be executed in accordance with the specified calling procedure Figure 16 18 Continuous Writing Flow Function No 16 Yes No Continuous writing Mask interrupts Set VPP voltage Continuous writing Error Clear VPP voltage Unmask interrupts Write error Clear VPP voltage Unmask interrupts Normal completion Set RAM par...

Page 756: ... The processing of each function number must be executed in accordance with the specified calling procedure Figure 16 19 Internal Verify Flow Function No 21 Yes No Internal verify Mask interrupts Set VPP voltage Internal verify Error Clear VPP voltage Unmask interrupts Internal verify error Clear VPP voltage Unmask interrupts Normal completion Set RAM parameter ...

Page 757: ...sh information is illustrated below The processing of each function number must be executed in accordance with the specified calling procedure Figure 16 20 Acquiring Flash Information Flow Function No 0 Acquiring flash information Mask interrupts Set VPP voltage Acquiring flash information Clear VPP voltage Unmask interrupts End Set RAM parameter ...

Page 758: ...ng module is located in area 0 and the data in area 1 is rewritten or erased The rewriting module is a user program to rewrite the flash memory The other areas can be also rewritten by using the flash functions included in this self programming library The flash functions expand the entry program in the external memory or internal RAM and call the device internal processing When using the self pro...

Page 759: ... of the self programming library is outlined below Figure 16 22 Outline of Self Programming Library Configuration Application program Entry program RAM parameter Device internal processing Flash memory Self programming interface Self programming library Flash memory manipulation C interface ...

Page 760: ... NOP 8 NOP 9 LDSR rY 5 10 TST1 3 FLPMC r0 BNZ Start address of self programming routine BR Routine when writing is not performed Remark rX Value written to the PSW rY Value returned to the PSW Cautions 1 If an interrupt is acknowledged between when PHCMD is issued 2 and writing to a specific register 3 immediately after issuing PHCMD writing to a specific register may not be performed and a protec...

Page 761: ... AVDD pins at 0 V until the voltage on the VDD3 pin rises to the level at which the operation is guaranteed 3 0 to 3 6 V To turn OFF Keep the voltage on the VDD3 pin at the level at which the operation is guaranteed 3 0 to 3 6 V until the voltage on the VDD5 and AVDD pins has dropped to 0 V When releasing reset status by RESET pin Release the reset status by the RESET pin after both the 3 3 V powe...

Page 762: ...If the voltage on the VDD3 pin drops below the level at which the operation is guaranteed 3 0 to 3 6 V before the voltage on the VDD5 and AVDD pins drops to 0 V the status of the I O pin is undefined Note Note This means that the input or output mode of an I O pin or the output level of an output pin is not determined Figure 17 2 Other Timing Depends on program setting Undefined I O pin VDD3 VDD5 ...

Page 763: ...in when VDD3 is supplied 0 5 to 6 0 V Clock input voltage VK X1 pin 0 5 to VDD3 1 0Note 1 V AVDD VDD5 0 5 to VDD5 0 5Note 1 V Analog input voltage VIAN ANI00 to ANI07 pins ANI10 to ANI17 pins VDD5 AVDD 0 5 to AVDD 0 5Note 1 V AVDD VDD5 0 5 to VDD5 0 5Note 1 V Analog reference input voltage AVREF AVREF0 pin AVREF1 pin VDD5 AVDD 0 5 to AVDD 0 5Note 1 V Per pin for TO000 to TO005 and TO010 to TO015 p...

Page 764: ...0 V 4 5 V 4 5 V VPP VDD3 VDD5 VPP 0 V 3 0 V 3 0 V a a b b Cautions 1 Do not directly connect output or I O pins of IC products to each other or to VDD VCC and GND Open drain pins or open collector pins however can be directly connected to each other Direct connection of the output pins between an IC product and an external circuit is possible if the output pins can be set to the high impedance sta...

Page 765: ...ernal System Clock Frequency fXX Operating Ambient Temperature TA VDD3 VDD5 µPD703116 703116 A 70F3116 70F3116 A 4 to 25 MHz 40 to 85 C 3 3 V 0 3 V 5 0 V 0 5 V Direct mode µPD703116 A1 70F3116 A1 4 to 16 MHz 40 to 110 C 3 3 V 0 3 V 5 0 V 0 5 V µPD703116 703116 A 70F3116 70F3116 A 4 to 50 MHz 40 to 85 C 3 3 V 0 3 V 5 0 V 0 5 V PLL mode µPD703116 A1 70F3116 A1 4 to 32 MHz 40 to 110 C 3 3 V 0 3 V 5 0...

Page 766: ...tor as close to the X1 and X2 pins as possible 2 Do not wire any other signal lines in the area indicated by the broken lines 3 For the resonator selection and oscillator constant customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation b External clock input Cautions 1 Connect the high speed CMOS inverter as closely to the X1 pin a...

Page 767: ...n chip On chip 0 3 0 3 6 Surface mount CSTCR6M00G55 R0 6 0 On chip On chip 0 3 0 3 6 Caution This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer If optimization of oscillator characteristics is necessary in the actual application apply to the resonator manufacturer for evaluation on the implementation circuit The oscillation ...

Page 768: ...VIL6 RESET pin 0 0 2VDD3 V VOH1 Pins other than Note 4 IOH 2 5 mA VDD5 1 0 V Output voltage high VOH2 Pins for NBDNote 4 IOH 2 5 mA VDD3 1 0 V IOL 15 mA 2 0 V VOL1 PWM outputNote 5 IOL 2 5 mA 0 4 V VOL2 Pins other than Notes 4 5 IOL 2 5 mA 0 4 V Output voltage low VOL3 Pins for NBDNote 4 IOL 2 5 mA 0 4 V Input leakage current high ILIH VI VDD5 10 µA Input leakage current low ILIL VI 0 V 10 µA Outp...

Page 769: ...116 VDD5 Note 3 20 40 mA VDD3 CVDD Note 2 1 2fXX 2 3fXX mA In HALT mode IDD2 µPD70F3116 VDD5 Note 3 20 40 mA VDD3 CVDD 3 0 10 mA In IDLE mode IDD3 VDD5 Note 3 0 5 2 0 mA 40 C TA 85 C 20 1200 µA VDD3 CVDD 40 C TA 110 C 20 3500 µA Power supply currentNote 1 In STOP mode IDD4 VDD5 Note 3 10 120 µA Notes 1 Value in the PLL mode 2 Determine the value by calculating fXX from the operating conditions 3 T...

Page 770: ...e 3 0 8VDDDR VDDDR V Note 2 0 0 2HVDDDR V Data retention input voltage low VILDR Note 3 0 0 2VDDDR V Notes 1 The current of the TO000 to TO005 and TO010 to TO015 pins is not included 2 P00 NMI P01 ESO0 INTP0 P02 ESO1 INTP1 P03 ADTRG0 INTP2 P04 ADTRG1 INTP3 P05 INTP4 to P07 INTP6 P10 TIUD10 TO10 P11 TCUD10 INTP100 P12 TCLR10 INTP101 P13 TIUD11 TO11 P14 TCUD11 INTP110 P15 TCLR11 INTP111 P20 TI2 INTP...

Page 771: ...points a Other than b to d below b AD0 PDL0 to AD15 PDL15 A16 PDH0 to A23 PDH7 LWR PCT0 UWR PCT1 PCT2 PCT3 RD PCT4 PCT5 ASTB PCT6 PCT7 WAIT PCM0 CLKOUT PCM1 HLDAK PCM2 HLDRQ PCM3 PCM4 CS0 PCS0 to CS7 PCS7 pins c CLK_DBG Note SYNC Note AD0_DBG to AD3_DBG Note RESET pins Note µPD70F3116 only d X1 pin VDD5 0 V 0 8VDD5 0 2VDD5 0 8VDD5 0 2VDD5 Test points VDD3 0 V 0 8VDD3 0 2VDD3 0 8VDD3 0 2VDD3 Test p...

Page 772: ... µ µPD70F3116 only Load conditions Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration insert a buffer or other element to reduce the device s load capacitance to 50 pF or lower VDD5 0 V 0 8VDD5 0 2VDD5 0 8VDD5 0 2VDD5 Test points VDD3 0 V 0 8VDD3 0 2VDD3 0 8VDD3 0 2VDD3 Test points DUT Device under test CL 50 pF ...

Page 773: ... X1 input low level width 3 tWXL PLL mode 50 ns Direct mode 4 ns X1 input rise time 4 tXR PLL mode 10 ns Direct mode 4 ns X1 input fall time 5 tXF PLL mode 10 ns Note 2 4 50 MHz Note 1 4 32 MHz CPU operation frequency fXX CLKOUT signal usedNote 3 4 32 MHz Note 2 20 250 ns Note 1 31 25 250 ns CLKOUT output cycle 6 tCYK CLKOUT signal usedNote 3 31 25 250 ns CLKOUT high level width 7 tWKH 0 5T 9 ns C...

Page 774: ...0F3116 70F3116 A TA 40 to 110 C µ µ µ µPD703116 A1 70F3116 A1 VDD3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V VSS3 VSS5 CVSS 0 V output pin load capacitance CL 50 pF Parameter Symbol Conditions MIN MAX Unit Output rise time 12 tOR 15 ns Output fall time 13 tOF 15 ns X1 3 1 2 4 5 X1 direct mode PLL mode 5 1 2 3 4 11 11 CLKOUT output 8 9 7 10 6 13 12 Signals other than CLKOUT ...

Page 775: ...5 5 V 0 5 V VSS3 VSS5 CVSS 0 V output pin load capacitance CL 50 pF Parameter Symbol Conditions MIN MAX Unit RESET pin high level width 14 tWRSH 500 ns At power on and at STOP mode release 500 TOST ns RESET pin low level width 15 tWRSL Other than at power on and at STOP mode release 500 ns Caution Thoroughly evaluate the oscillation stabilization time Remark TOST Oscillation stabilization time RES...

Page 776: ...tWSTH 1 wAS T 15 ns Data output time from LWR UWR 28 tDWROD 10 ns Data output setup time to LWR UWR 29 tSODWR 1 w T 25 ns Data output hold time from LWR UWR 30 tHWROD T 20 ns 31 tSAWT1 w 1 1 5 wAS wAH T 40 ns WAIT setup time to address 32 tSAWT2 1 5 w wAS wAH T 40 ns 33 tHAWT1 w 1 0 5 w wAS wAH T ns WAIT hold time from address 34 tHAWT2 1 5 w wAS wAH T ns 35 tSSTWT1 w 1 1 wAH T 32 ns WAIT setup ti...

Page 777: ...om CLKOUT to ASTB 47 tDKST 3 wAHT 19 wAHT ns Delay time from CLKOUT to RD LWR UWR 48 tDKRDWR 5 19 ns Data input setup time to CLKOUT 49 tSIDK 21 ns Data input hold time from CLKOUT 50 tHKID 5 ns Delay time from CLKOUT to data output 51 tDKOD 19 ns WAIT setup time to CLKOUT 52 tSWTK 21 ns WAIT hold time from CLKOUT 53 tHKWT 5 ns HLDRQ setup time to CLKOUT 54 tSHQK 21 ns HLDRQ hold time from CLKOUT ...

Page 778: ...e CLKOUT synchronous asynchronous 1 wait Remark LWR and UWR are high level 21 CLKOUT output A16 to A23 output RD output AD0 to AD15 I O ASTB output WAIT input T1 T2 TW T3 Data Address Hi Z 45 19 46 47 16 27 48 35 37 36 38 31 33 32 34 52 52 53 20 26 18 17 49 50 47 22 48 23 25 24 53 ...

Page 779: ...Write cycle CLKOUT synchronous asynchronous 1 wait Remark RD is high level CLKOUT output AD0 to AD15 I O ASTB output LWR output UWR output A16 to A23 output WAIT input T1 T2 TW T3 Data Address 45 51 47 16 17 27 47 48 21 35 52 37 36 38 31 33 32 34 53 52 53 28 29 26 48 24 30 ...

Page 780: ...NS 780 User s Manual U14492EJ3V0UD e Bus hold CLKOUT output HLDRQ input HLDAK output A16 to A23 output AD0 to AD15 I O ASTB output RD output LWR output UWR output TH TH TH TI Hi Z Hi Z Hi Z Data Hi Z 54 55 43 56 41 57 56 44 40 42 54 39 ...

Page 781: ...g registers INTP100 INTP101 Can be selected from fXXTM10 fXXTM10 2 fXXTM10 4 and fXXTM10 8 by setting the NRC101 and NRC100 bits of the timer 10 noise elimination time selection register NRC10 fXXTM10 clock selected with the timer 1 timer 2 clock selection register PRM02 INTP110 INTP111 Can be selected from fXXTM11 fXXTM11 2 fXXTM11 4 and fXXTM11 8 by setting the NRC111 and NRC110 bits of the time...

Page 782: ...cted by setting the following registers When using TIUDn TCUDn and TCLRn n 10 11 the following cycles can be selected by setting the NRCn1 and NRCn0 bits of timer n noise elimination time selection register NRCn When fXX 2 is selected for the timer n base clock fXX 2 fXX 4 fXX 8 fXX 16 When fXX 4 is selected for the timer n base clock fXX 4 fXX 8 fXX 16 fXX 32 When using TCLR2 and TI2 the followin...

Page 783: ...CL 50 pF Parameter Symbol Conditions MIN MAX Unit SCKn cycle 66 tCYSK1 Output 200 ns SCKn high level width 67 tWSK1H Output 0 5tCYSK1 25 ns SCKn low level width 68 tWSK1L Output 0 5tCYSK1 25 ns SIn setup time to SCKn 69 tSSISK 35 ns SIn hold time from SCKn 70 tHSKSI 30 ns SOn output delay time from SCKn 71 tDSKSO 30 ns SOn output hold time from SCKn 72 tHSKSO 0 5tCYSK1 20 ns Remark n 0 1 b Slave m...

Page 784: ...5 V VSS3 VSS5 CVSS 0 V output pin load capacitance CL 50 pF Parameter Symbol Conditions MIN MAX Unit UART0 baud rate generator input frequency fBRG 25 MHz Remark fBRG UART0 baud rate generator input frequency can be selected from fXX fXX 2 fXX 4 fXX 8 fXX 16 fXX 32 fXX 64 fXX 128 fXX 256 fXX 512 fXX 1024 and fXX 2048 by setting the TPS3 to TPS0 bits of clock selection register 0 CKSR0 fXX Internal...

Page 785: ...KTX T 10 ns TXDn output hold time from ASCKn 79 tHSKTX k 1 T 20 ns Remarks 1 T 2tCYK 2 k Setting value of prescaler compare register n PRSCMn of UARTn 3 n 1 2 b Clocked slave mode TA 40 to 85 C µ µ µ µPD703116 703116 A 70F3116 70F3116 A TA 40 to 110 C µ µ µ µPD703116 A1 70F3116 A1 VDD3 CVDD 3 0 to 3 6 V VDD5 5 V 0 5 V VSS3 VSS5 CVSS 0 V output pin load capacitance CL 50 pF Parameter Symbol Conditi...

Page 786: ...CHAPTER 18 ELECTRICAL SPECIFICATIONS 786 User s Manual U14492EJ3V0UD 10 UART1 UART2 timing 2 2 Remark n 1 2 73 75 74 76 77 78 79 RXDn input TXDn output ASCKn I O Output data Input data ...

Page 787: ...Conditions MIN MAX Unit NBD cycle 80 tNDCYC 80 ns NBD cycle low level width 81 tNDL 35 ns NBD data output delay time 82 tNDD 5 tNDCYC 20 ns NBD data output hold time 83 tNDHD 2 ns NBD data input setup time 84 tNDS 20 ns NBD data input hold time 85 tNDH 5 ns SYNC input setup time 86 tNDSYS 20 ns SYNC input hold time 87 tNDSYH 5 ns CLK_DBG input AD0_DBG to AD3_DBG output AD0_DBG to AD3_DBG input SYN...

Page 788: ...LSB Quantization error 1 2 LSB Conversion time tCONV 5 10 µs Sampling time tSAMP 833 ns Zero scale errorNote 1 3 LSB Full scale errorNote 1 3 LSB Differential linearity errorNote 1 3 LSB Integral linearity errorNote 1 5 LSB Analog input voltage VIAN 0 3 AVREFn 0 3 V Analog reference voltage AVREF AVREFn AVDD 4 5 5 5 V AVREFn input currentNote 2 AIREF 1 2 mA AVDD power supply currentNote 2 AIDD 3 6...

Page 789: ...tep writing time tWT Note 5 18 20 22 µs Overall writing time per word tWTW When the step writing time 20 µs 1 word 4 bytes Note 6 20 200 µs word Number of rewrites per area CERWR 1 erase 1 write after erase 1 rewrite Note 7 100 Count area Notes 1 The recommended setting value of the step erase time is 0 4 s 2 The prewrite time prior to erasure and the erase verify time write back time are not incl...

Page 790: ...RPSR 10 µs VPP to RESET set time 89 tPSRRF 1 µs RESET to VPP count start time 90 tRFOF VPP 7 8 V 10T 1500 ns Count execution time 91 tCOUNT 15 ms VPP counter high level width 92 tCH 1 µs VPP counter low level width 93 tCL 1 µs VPP counter rise time 94 tR 1 µs VPP counter fall time 95 tF 1 µs VPP to VDD3 VDD5 reset time 96 tPFDR 10 µs Remark T tCYK 88 90 93 92 91 95 94 0 V 0 V RESET input 89 96 0 V...

Page 791: ...TE A 22 0 0 2 B 20 0 0 2 C 20 0 0 2 D F 1 25 22 0 0 2 S144GJ 50 UEN S 1 5 0 1 K 1 0 0 2 L 0 5 0 2 R 3 4 3 G 1 25 H 0 22 0 05 I 0 08 J 0 5 T P M 0 17 N 0 08 P 1 4 Q 0 10 0 05 0 03 0 07 Each lead centerline is located within 0 08 mm of its true position T P at maximum material condition S S M detail of lead end I J F G H Q R P K M L N C D S A B ...

Page 792: ...0 µ µ µ µPD70F3116GJ UEN 144 pin plastic LQFP fine pitch 20 20 µ µ µ µPD70F3116GJ A UEN 144 pin plastic LQFP fine pitch 20 20 µ µ µ µPD70F3116GJ A1 UEN 144 pin plastic LQFP fine pitch 20 20 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 230 C Time 30 seconds max at 210 C or higher Count Two times or less Exposure limit 3 daysNote after t...

Page 793: ...4 Pin Plastic LQFP Fine Pitch 20 20 Side view Target system NQPACK144SD YQPACK144SD 206 26 mm Note In circuit emulator option board Conversion connector IE 703116 MC EM1 In circuit emulator IE V850E MC YQGUIDE Note YQSOCKET144SDN sold separately can be inserted here to adjust the height height 3 2 mm Top view Target system YQPACK144SD NQPACK144SD YQGUIDE IE 703116 MC EM1 IE V850E MC Connection con...

Page 794: ...C 654 ADETM0 A D voltage detection mode register 0 ADC 653 ADETM0H A D voltage detection mode register 0H ADC 653 ADETM0L A D voltage detection mode register 0L ADC 653 ADETM1 A D voltage detection mode register 1 ADC 653 ADETM1H A D voltage detection mode register 1H ADC 653 ADETM1L A D voltage detection mode register 1L ADC 653 ADIC0 Interrupt control register INTC 179 ADIC1 Interrupt control re...

Page 795: ...ster CM11 RPU 232 BFCM12 Buffer register CM12 RPU 232 BFCM13 Buffer register CM13 RPU 233 BPC Peripheral area selection control register CPU 93 BRGC0 Baud rate generator control register 0 UART0 440 BSC Bus size configuration register BCU 117 C1BA CAN1 bus active register FCAN 594 C1BRP CAN1 bit rate prescaler register FCAN 595 C1CTRL CAN1 control register FCAN 581 C1DEF CAN1 definition register F...

Page 796: ... 381 CC31 Capture compare register 31 RPU 381 CC3IC0 Interrupt control register INTC 179 CC3IC1 Interrupt control register INTC 179 CCINTP CAN interrupt pending register FCAN 566 CCR0 Capture compare control register 0 RPU 311 CCR1 Capture compare control register 1 RPU 311 CCSTATE0 Timer 2 capture compare 1 to 4 status register 0 RPU 356 CCSTATE0H Timer 2 capture compare 1 to 4 status register 0H...

Page 797: ... capture register RPU 358 CSE0 Timer 2 count clock control edge selection register 0 RPU 344 CSE0H Timer 2 count clock control edge selection register 0H RPU 344 CSE0L Timer 2 count clock control edge selection register 0L RPU 344 CSIC0 Clocked serial interface clock selection register 0 CSI0 488 CSIC1 Clocked serial interface clock selection register 1 CSI1 488 CSIIC0 Interrupt control register I...

Page 798: ...egister 1H DMAC 142 DDA1L DMA destination address register 1L DMAC 143 DDA2H DMA destination address register 2H DMAC 142 DDA2L DMA destination address register 2L DMAC 143 DDA3H DMA destination address register 3H DMAC 142 DDA3L DMA destination address register 3L DMAC 143 DDIS DMA disable status register DMAC 149 DETIC0 Interrupt control register INTC 179 DETIC1 Interrupt control register INTC 1...

Page 799: ...t filter mode register 5 RPU 191 719 FLPMC Flash programming mode control register CPU 749 IMR0 Interrupt mask register 0 INTC 182 IMR0H Interrupt mask register 0H INTC 182 IMR0L Interrupt mask register 0L INTC 182 IMR1 Interrupt mask register 1 INTC 182 IMR1H Interrupt mask register 1H INTC 182 IMR1L Interrupt mask register 1L INTC 182 IMR2 Interrupt mask register 2 INTC 182 IMR2H Interrupt mask ...

Page 800: ...gister DH NBD 639 NBDMDL DMA destination address setting register DL NBD 639 NBDMSH DMA source address setting register SH NBD 638 NBDMSL DMA source address setting register SL NBD 638 NRC10 Timer 10 noise elimination time selection register RPU 716 NRC11 Timer 11 noise elimination time selection register RPU 716 NRC3 Timer 3 noise elimination time selection register RPU 717 OCTLE0 Timer 2 output ...

Page 801: ...e control register Port 702 PMCCM Port CM mode control register Port 712 PMCCS Port CS mode control register Port 708 PMCCT Port CT mode control register Port 710 PMCDH Port DH mode control register Port 704 PMCDL Port DL mode control register Port 706 PMCDLH Port DL mode control register H Port 706 PMCDLL Port DL mode control register L Port 706 PMCM Port CM mode register Port 711 PMCS Port CS mo...

Page 802: ...register 11 INTC RPU 187 312 SESC Valid edge selection register INTC RPU 190 388 SESE0 Timer 2 sub channel input event edge selection register 0 RPU 345 SESE0H Timer 2 sub channel input event edge selection register 0H RPU 345 SESE0L Timer 2 sub channel input event edge selection register 0L RPU 345 SIO0 Serial I O shift register 0 CSI0 498 SIO1 Serial I O shift register 1 CSI1 498 SIOL0 Serial I ...

Page 803: ...IC2 Interrupt control register INTC 179 STOPTE0 Timer 2 clock stop register 0 RPU 343 STOPTE0H Timer 2 clock stop register 0H RPU 343 STOPTE0L Timer 2 clock stop register 0L RPU 343 TBSTATE0 Timer 2 time base status register 0 RPU 355 TBSTATE0H Timer 2 time base status register 0H RPU 355 TBSTATE0L Timer 2 time base status register 0L RPU 355 TCRE0 Timer 2 time base control register 0 RPU 346 TCRE...

Page 804: ...ion selection register 0 RPU 413 TOMR0 Timer output mode register 0 RPU 242 TOMR1 Timer output mode register 1 RPU 242 TUC00 Timer unit control register 00 RPU 241 TUC01 Timer unit control register 01 RPU 241 TUM0 Timer unit mode register 0 RPU 308 TUM1 Timer unit mode register 1 RPU 308 TXB0 Transmission buffer register 0 UART0 424 TXS1 2 frame continuous transmission shift register 1 UART1 457 T...

Page 805: ...5 bit data that specifies a trap vector 00H to 1FH cccc 4 bit data that shows a condition code sp Stack pointer r3 ep Element pointer r30 list X item register list 2 Symbols used in operands Symbol Explanation R 1 bit of data of code that specifies reg1 or regID r 1 bit of data of code that specifies reg2 w 1 bit of data of code that specifies reg3 d 1 bit of data of a displacement I 1 bit of imme...

Page 806: ... If n is a computation result and n 80000000H make n 80000000H result Reflect result in flag Byte Byte 8 bits Half word Halfword 16 bits Word Word 32 bits Addition Subtraction Bit concatenation Multiplication Division Remainder of division result AND Logical product OR Logical sum XOR Exclusive logical sum NOT Logical negation logically shift left by Logical shift left logically shift right by Log...

Page 807: ... NV 1000 OV 0 No overflow C L 0001 CY 1 Carry Lower Less than NC NL 1001 CY 0 No carry No lower Greater than or equal Z E 0010 Z 1 Zero Equal NZ NE 1010 Z 0 Not zero Not equal NH 0011 CY or Z 1 Not higher Less than or equal H 1011 CY or Z 0 Higher Greater than N 0100 S 1 Negative P 1100 S 0 Positive T 0101 Always Unconditional SA 1101 SAT 1 Saturated LT 0110 S xor OV 1 Less than signed GE 1110 S x...

Page 808: ...eturn PC CTPSW PSW adr CTBP zero extend imm6 logically shift left by 1 PC CTBP zero extend Load memory adr Halfword 5 5 5 1 0 b b b 1 1 1 1 1 0 R R R R R bit 3 disp16 reg1 d d d d d d d d d d d d d d d d adr GR reg1 sign extend disp16 Z flag Not Load memory bit adr bit 3 Store memory bit adr bit 3 0 3 Note 3 3 Note 3 3 Note 3 1 0 b b b 1 1 1 1 1 0 R R R R R CLR1 reg2 reg1 d d d d d d d d d d d d d...

Page 809: ...2 GR reg1 GR reg3 GR reg2 GR reg1 34 34 34 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 EI 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 PSW ID 0 1 1 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 HALT 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 Stop 1 1 1 r r r r r 1 1 1 1 1 1 0 0 0 0 0 HSW reg2 reg3 w w w w w 0 1 1 0 1 0 0 0 1 0 0 GR reg3 GR reg2 15 0 GR reg2 31 16 1 1 1 0 r r r r r 1 1 1 1 0 d d d d d d JARL disp22 reg2 d d d d d d d d d d d d d...

Page 810: ...1 1 1 1 1 R R R R R reg1 reg2 reg3 w w w w w 0 1 0 0 0 1 0 0 0 1 0 GR reg3 GR reg2 GR reg2 GR reg1 reg1 reg2 reg3 reg3 r0 1 2 Note 14 2 r r r r r 1 1 1 1 1 1 i i i i i MULU imm9 reg2 reg3 w w w w w 0 1 0 0 1 I I I I 1 0 GR reg3 GR reg2 GR reg2 zero extend imm9 1 2 Note 14 2 NOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Passes at least 1 cycle doing nothing 1 1 1 NOT reg1 reg2 r r r r r 0 0 0 0 0 1 R R R R R...

Page 811: ...reg2 saturated GR reg1 GR reg2 1 1 1 r r r r r 1 1 1 1 1 1 0 c c c c SETF cccc reg2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 if conditions are satisfied then GR reg2 00000001H else GR reg2 00000000H 1 1 1 0 0 b b b 1 1 1 1 1 0 R R R R R bit 3 disp16 reg1 d d d d d d d d d d d d d d d d adr GR reg1 sign extend disp16 Z flag Not Load memory bit adr bit 3 Store memory bit adr bit 3 1 3 Note 3 3 Note 3 3 Note ...

Page 812: ...r r r r 0 0 1 1 0 1 R R R R R GR reg2 GR reg2 GR reg1 1 1 1 SUBR reg1 reg2 r r r r r 0 0 1 1 0 0 R R R R R GR reg2 GR reg1 GR reg2 1 1 1 SWITCH reg1 0 0 0 0 0 0 0 0 0 1 0 R R R R R adr PC 2 GR reg1 logically shift left by 1 PC PC 2 sign extend Load memory adr Halfword logically shift left by 1 5 5 5 SXB reg1 0 0 0 0 0 0 0 0 1 0 1 R R R R R GR reg1 sign extend GR reg1 7 0 1 1 1 SXH reg1 0 0 0 0 0 0...

Page 813: ...In this instruction although the source register is regarded as reg2 for convenience of the mnemonic description the reg1 field is used in the opcode Therefore the meanings of register specifications assigned in the mnemonic description and in the opcode differ from those in other instructions rrrrr regID specification RRRRR reg2 specification 13 iiiii Lower 5 bits of imm9 IIII Higher 4 bits of im...

Page 814: ...ample timer 4 411 application examples timer 3 396 applications 33 arbitration field 533 area 73 area number 748 ASCK1 ASCK2 51 ASIF0 422 ASIM0 418 ASIM10 ASIM20 449 ASIM11 ASIM21 451 ASIS0 421 ASIS1 ASIS2 452 assembler reserved register 64 ASTB 54 asynchronous serial interface 0 415 asynchronous serial interface mode register 0 418 asynchronous serial interface mode registers 10 20 449 asynchrono...

Page 815: ... to H31 558 CAN message search start result register 577 CAN message status registers 00 to 31 562 CAN message time stamp registers 00 to 31 555 CAN sleep mode 541 614 CAN status set clear registers 00 to 31 564 CAN stop mode 541 615 CAN stop register 569 CAN time stamp count register 576 CAN1 address mask 0 to 3 registers L and H 579 CAN1 bit rate prescaler register 595 CAN1 bus active register 5...

Page 816: ...0 CM110 304 CM101 CM111 304 CM10IC0 CM10IC1 179 CM11IC0 CM11IC1 179 CM4 406 CM4IC0 179 CMSE050 350 CMSE120 351 CMSE340 353 command register 215 communication commands 738 communication mode 731 compare register 4 406 compare registers 000 to 002 010 to 012 231 compare registers 003 013 232 compare registers 100 110 304 compare registers 101 111 304 continuous transmission operation 429 control fie...

Page 817: ...M02 231 DTM10 to DTM12 231 DTRR0 DTRR1 231 DWC0 DWC1 124 E ECR 65 edge detection function 171 electrical specifications 763 element pointer 64 end of frame 536 entry program 740 EP 196 error active 537 error frame 538 error passive 537 ESO0 ESO1 48 event detection function 634 EVTU_A 635 EVTU_C 634 exception status flag 196 exception trap 197 extended format mode 530 external bus cycles during DMA...

Page 818: ...st of pin functions 41 lock register 211 LOCKR 211 LWR 54 M M_CONF00 to M_CONF31 560 M_CTRL00 to M_CTRL31 552 M_DATAn0 to M_DATAn7 n 00 to 31 556 M_DLC00 to M_DLC31 550 M_IDL00 to M_IDL31 and M_IDH00 to M_IDH31 558 M_STAT00 to M_STAT31 562 M_TIME00 to M_TIME31 555 mask function 528 maskable interrupt status flag 184 maskable interrupts 172 MEMC 38 memory access control function 132 memory block fu...

Page 819: ...egister 210 PFC1 695 PFC2 698 PHCMD 207 PHS 210 pin configuration 35 pin I O circuits 61 pin status 47 PLL lockup 211 PLL mode 206 212 PM1 693 PM2 696 PM3 699 PM4 701 PMC1 694 PMC2 697 PMC3 700 PMC4 702 PMCCM 712 PMCCS 708 PMCCT 710 PMCDH 704 PMCDL 706 PMCM 711 PMCS 708 PMCT 709 PMDH 703 PMDL 706 POER0 POER1 247 port 0 692 port 1 693 port 1 function control register 695 port 1 mode control registe...

Page 820: ...PSTO1 248 PSW 66 PWM mode 0 259 PWM mode 1 267 PWM mode 2 280 PWM output enable registers 0 1 247 PWM software timing output registers 0 1 248 Q quantization error 674 R r0 to r31 64 RAM 38 RAM access data buffer registers H HL HU 637 RAM access data buffer registers L LL LU 637 RAM monitoring 632 RAM parameter 740 RD 54 real time pulse unit 39 226 reception buffer register 0 423 reception buffer ...

Page 821: ...E0L 346 TCUD10 TCUD11 49 text pointer 64 TI2 TI3 50 TID0 to TID2 636 time base counter 225 time stamp function 524 timer 0 226 timer 0 clock selection register 234 timer 1 298 timer 10 noise elimination time selection register 716 timer 11 noise elimination time selection register 716 timer 1 timer 2 clock selection register 307 343 timer 2 334 timer 2 capture compare 1 to 4 status registers 0 0H ...

Page 822: ...O015 56 TO10 TO11 49 TO21 to TO24 50 TO3 50 TOMR write enable registers 0 1 257 TOMR0 TOMR1 242 transfer mode 154 transfer object 158 transfer type and transfer object 158 transfer types 157 transmission buffer register 0 424 transmission operation UART0 427 transmission operation UART1 2 461 transmission shift registers L1 L2 457 triangular wave modulation 259 267 TRIG_DBG 58 TUC00 TUC01 241 TUM0...

Page 823: ...on in 2 4 Types of Pin I O Circuit and Connection of Unused Pins Modification of I O circuit type from 5 K to 5 AC in 2 5 Pin I O Circuits CHAPTER 2 PIN FUNCTIONS Modification of description in 3 4 5 1 a Memory map Modification of description in 3 4 5 2 Internal RAM area Addition of Note and modification of Caution in 3 4 5 3 On chip peripheral I O area Deletion of part of description in 3 4 7 1 P...

Page 824: ... and addition of bit names and bit description in 6 3 8 DMA trigger factor registers 0 to 3 DTFR0 to DTFR3 Addition of description in 6 5 1 Single transfer mode Addition of description in 6 5 2 Single step transfer mode Addition of Caution in 6 6 1 Two cycle transfer Modification of description in 6 7 1 Transfer type and transfer object Modification of description in Table 6 1 Relationship Between...

Page 825: ...ification of description and modification of timing chart in 8 6 1 1 Securing the time using an on chip time base counter Modification of timing chart in 8 6 1 2 Securing the time according to the signal level width RESET pin input Modification of description in Table 8 8 Counting Time Examples fXX 10 fX CHAPTER 8 CLOCK GENERATION FUNCTION Modification of Figure 9 1 Block Diagram of Timer 0 Mode 0...

Page 826: ... control edge selection register 0 CSE0 Modification of description on bits that can be manipulated in 9 3 4 4 Timer 2 sub channel input event edge selection register 0 SESE0 Modification of description on bits that can be manipulated addition of Caution and addition of Caution in bit description in 9 3 4 5 Timer 2 time base control register 0 TCRE0 Modification of description on bits that can be ...

Page 827: ...tion of description in table in Figure 10 5 Continuous Transmission Starting Procedure Modification of description in table in Figure 10 6 Continuous Transmission End Procedure Addition of Caution in Figure 10 7 Asynchronous Serial Interface Reception Completion Interrupt Timing Modification of description on bits that can be manipulated and addition of Caution in 10 2 6 2 a Clock selection regist...

Page 828: ... 11 8 7 1 Prescaler Modification of description in 11 8 7 2 Nominal bit time 8 to 25 time quantum Addition of Caution and modification of bit description in 11 10 2 CAN message data length registers 00 to 31 M_DLC00 to M_DLC31 Deletion of one of Notes for bits addition of Caution and modification of bit description in 11 10 3 CAN message control registers 00 to 31 M_CTRL00 to M_CTRL31 Addition of ...

Page 829: ...n 11 17 Cautions on Use CHAPTER 11 FCAN CONTROLLER Addition of description in 12 1 2 Event detection function Modification of Figure 12 1 Image of NBD Space Addition of description in 12 4 1 1 b Read command Addition of Caution in 12 4 2 2 b NBD event address register EVTU_A Addition of description for NBDLL modification of description on bits that can be manipulated and deletion of part of Remark...

Page 830: ...block type in 14 3 10 1 Operation in control mode Addition of Caution and addition of Caution in bit description in 14 4 3 1 Timer 2 input filter mode registers 0 to 5 FEM0 to FEM5 CHAPTER 14 PORT FUNCTIONS Addition and modification of description in Table 15 2 Initial Values of CPU Internal RAM and On Chip Peripheral I O After Reset CHAPTER 15 RESET FUNCTION Addition of Caution in 16 2 Writing by...

Page 831: ...MA destination address registers 0H to 3H DDA0H to DDA3H Addition of description to 6 3 3 DMA transfer count registers 0 to 3 DBC0 to DBC3 Addition of description to 6 3 4 DMA addressing control registers 0 to 3 DADC0 to DADC3 Addition of description to 6 3 5 DMA channel control registers 0 to 3 DCHC0 to DCHC3 Addition and modification of description in 6 3 6 DMA disable status register DDIS Addit...

Page 832: ...f each port Modification of description in Figure 14 14 Example of Noise Elimination Timing CHAPTER 14 PORT FUNCTIONS Addition of CHAPTER 18 ELECTRICAL SPECIFICATIONS CHAPTER 18 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 19 PACKAGE DRAWING CHAPTER 19 PACKAGE DRAWING Addition of CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS Addition of APPENDIX A NOTES O...

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