CHAPTER 10 SERIAL INTERFACE FUNCTION
User’s Manual U14492EJ3V0UD
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10.3.2 Configuration
UART1 and UART2 are controlled by asynchronous serial interface mode registers 10, 11, 20, and 21 (ASIM10,
ASIM11, ASIM20, ASIM21) and asynchronous serial interface status registers 1 and 2 (ASIS1, ASIS2). Receive data
is held in the reception buffer registers (RXB1, RXBL1, RXB2, RXBL2), and transmit data is held in the transmission
shift registers (TXS1, TXSL1, TXS2, TXSL2).
Figure 10-15 shows the configuration of asynchronous serial interfaces 1 and 2 (UART1, UART2).
(1) Asynchronous serial interface mode registers 10, 11, 20, 21 (ASIM10, ASIM11, ASIM20, ASIM21)
The ASIMn0 and ASIMn1 registers are 8-bit registers that specify the operation of the asynchronous serial
interface (n = 1, 2).
(2) Asynchronous serial interface status registers 1, 2 (ASIS1, ASIS2)
The ASIS1 and ASIS2 registers consist of a transmission status flag (SOTn), reception status flag (SIRn), a
bit (RB8) that indicates the 9th bit when extension bit addition is enabled, and 3-bit error flags (PEn, FEn,
OVEn) that indicate the error status at reception end (n = 1, 2).
(3) Reception control parity check
The receive operation is controlled according to the contents set in the ASIMn0 and ASIMn1 registers. A
check for parity errors is also performed during receive operation, and if an error is detected, a value
corresponding to the error contents is set in the ASIS1 and ASIS2 registers.
(4) 2-frame continuous reception buffer registers (RXB1, RXB2)/reception buffer registers (RXBL1,
RXBL2)
RXBn is a 16-bit (during 2-frame continuous reception, 9-bit extension data reception) buffer register that
holds receive data. During 7, 8 bit/character reception, 0 is stored in the MSB.
For 16-bit access to this register, specify RXB1, RXB2, and for access to the lower 8 bits, specify RXBL1,
RXBL2.
In the reception enabled state, receive data is transferred from the reception shift register to the reception
buffer in synchronization with the completion of shift-in processing of one frame.
A reception completion interrupt request (INTSRn) is generated upon transfer to the reception buffer (when 2-
frame continuous reception is specified, reception buffer transfer of the second frame).
(5) 2-frame continuous transmission shift registers (TXS1, TXS2)/transmission shift registers (TXSL1,
TXSL2)
TXSn is a 9-bit/2-frame continuous transmission processing shift register. Transmission is started by writing
data to this register.
A transmission completion interrupt request (INTSTn) is generated in synchronization with the end of
transmission of 1 frame or 2 frames including the TXSn data.
For 16-bit access to this register, specify TXS1, TXS2, and for access to the lower 8 bits, specify TXSL1,
TXSL2.
(6) Addition of transmission control parity
A transmission operation is controlled by adding a start bit, parity bit, or stop bit to the data that is written to
the TXSn or TXSLn register, according to the contents set in the ASIMn0, ASIMn1 registers.
(7) Selector
The selector selects the serial clock source.
