33
CHAPTER 5 DIFFERENCES FROM TARGET DEVICE
Figure 5-1. Equivalent Circuit Diagram of Port Pin Emulation Circuit (2/3)
P0 (7 : 0)
Emulation device
side
27
Ω
Target probe
side
P4 (7 : 0)
P5 (7 : 0)
P6 (7 : 0)
P7 (7 : 0)
P8 (7 : 0)
P9 (6 : 0)
INTP (2 : 0)
PTO0 (2 : 0)
PWM (1 : 0)
SCK2
SO2
SI2/BUSY
ANI (11 : 8)
NMI
27
Ω
27
Ω
27
Ω
27
Ω
P0 (7 : 0)
P4 (7 : 0)
P5 (7 : 0)
P6 (7 : 0)
P7 (7 : 0)
P8 (7 : 0)
P9 (6 : 0)
INTP (2 : 0)
PTO0 (2 : 0)
PWM (1 : 0)
SCK2
SO2
SI2/BUSY
ANI (11 : 8)
NMI
Q D
NMIMSK1
(emulation board)
Summary of Contents for IE-784915-R-EM1
Page 2: ...2 MEMO...
Page 6: ...6 MEMO...
Page 11: ...VOLUME 1 IE 784915 R EM1 I O EMULATION BOARD 11...
Page 12: ...12 MEMO...
Page 18: ...MEMO 18...
Page 24: ...MEMO 24...
Page 28: ...28 CHAPTER 3 SETTING OF USER CLOCK MEMO 28...
Page 30: ...MEMO 30...
Page 38: ...MEMO 38...
Page 40: ...MEMO 40...
Page 41: ...VOLUME 2 EP 784915GF R EMULATION PROBE 41...
Page 42: ...42 MEMO...
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