CHAPTER 9 WATCHDOG TIMER
User’s Manual U16898EJ3V0UD
148
Cautions 1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values.
2. After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing is attempted a second time, an internal reset
signal is generated. However, at the first write, if “1” and “x” are set for WDCS4 and
WDCS3 respectively and the watchdog timer is stopped, then the internal reset
signal does not occur even if the following are executed.
•
Second write to WDTM
•
1-bit memory manipulation instruction to WDTE
•
Writing of a value other than “ACH” to WDTE
3. WDTM cannot be set by a 1-bit memory manipulation instruction.
4. When using the flash memory self programming by self writing, set the overflow time
for the watchdog timer so that enough everflow time is secured (Example 1-byte
writing: 200
µ
s MIN., 1-block deletion: 10 ms MIN.).
Remarks 1.
f
RL
: Low-speed internal oscillation clock oscillation frequency
2.
f
X
: System clock oscillation frequency
3.
×
: Don’t
care
4.
Figures in parentheses apply to operation at f
RL
= 480 kHz (MAX.), f
X
= 10 MHz.
(2) Watchdog timer enable register (WDTE)
Writing ACH to WDTE clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 9AH.
Figure 9-3. Format of Watchdog Timer Enable Register (WDTE)
0
1
2
3
4
5
6
7
Symbol
WDTE
Address: FF49H After reset: 9AH R/W
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated.
3. The value read from WDTE is 9AH (this differs from the written value (ACH)).
