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NEC 78K0S/KA1+, User Manual

Introducing the NEC 78K0S/KA1+: A versatile microcontroller offering stellar performance. For a comprehensive understanding of its features and functionalities, grab our Preliminary User's Manual - available for free download on our website. Unlock the full potential of your device today! manualshive.com

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CHAPTER  6   16-BIT  TIMER/EVENT  COUNTER  00 

User’s Manual  U16898EJ3V0UD 

121

(18) Edge detection 

 

<1>  In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. 
 

(a)  Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit 

timer counter 00 (TM00) is enabled  

 

 

→

 If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, 

a rising edge is detected immediately after the TM00 operation is enabled. 

 

(b)  If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is then enabled 

after a low level is input to the TI0n0 pin  

 

 

→

 If the falling edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin, 

a falling edge is detected immediately after the TM00 operation is enabled. 

 

(c)  When the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is then 

enabled after a high level is input to the TI0n0 pin 

 

 

→

 If the rising edge or both rising and falling edges are specified as the valid edge, of the TI0n0 pin, 

a rising edge is detected immediately after the TM00 operation is enabled. 

 

Remark 

n = 0, 1 

 
<2>  The sampling clock used to remove noise differs when a TI000 valid edge is used as the count clock and 

when it is used as a capture trigger. In the former case, the count clock is f

XP

, and in the latter case the 

count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not performed 
until the valid edge is sampled and the valid level is detected twice, thus eliminating, noise with a short 
pulse width. 

 

(19) External event counter  

 
<1>  The timing of the count start is after two valid edge detections. 
 
<2>  When reading the external event counter count value, TM00 should be read.

 

 

(20) PPG output  

 
<1>  Values in the following range should be set in CR000 and CR010: 
 0000H 

<

 

CR010 < CR000 

≤ 

FFFFH 

 
<2>  The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010 

setting value + 1)/(CR000 setting value + 1).

 

 

(21) STOP mode or system clock stop mode setting 

Except when TI000 pin valid edge is selected as the count clock, stop the timer operation before setting STOP 
mode or system clock stop mode; otherwise the timer may malfunction when the system clock starts. 

 

(22) P31/TI010/TO00 pin 

When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00).  
When using P31 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge.

 

 

Summary of Contents for 78K0S/KA1+

Page 1: ...User s Manual µPD78F9221 µPD78F9222 78K0S KA1 8 Bit Single Chip Microcontrollers Printed in Japan Document No U16898EJ3V0UD00 3rd edition Date Published July 2005 NS CP K 2003 ...

Page 2: ...User s Manual U16898EJ3V0UD 2 MEMO ...

Page 3: ... including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the power source is turned ON d...

Page 4: ...esponsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including ...

Page 5: ...anch Seoul Korea Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 5888 5400 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 6253 8311 J04 1 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65030 Sucursal en España Madrid Spain Tel 091 504 27 87 Vélizy Villacoublay France Tel 01 30 67 58 00 Succur...

Page 6: ...upts Other internal peripheral functions Electrical specifications CPU function Instruction set Instruction description How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To understand the overall functions of 78K0S KA1 Read this manual in the order of the CONTENTS The mark shows major revised po...

Page 7: ...l This manual 78K 0S Series Instructions User s Manual U11047E Documents Related to Development Software Tools User s Manuals Document Name Document No Operation U16656E Language U14877E RA78K0S Assembler Package Structured Assembly Language U11623E Operation U16654E CC78K0S C Compiler Language U14872E ID78K0S NS Ver 2 52 Integrated Debugger Operation U16584E ID78K0S QB Ver 2 81 Integrated Debugge...

Page 8: ...ages X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Note See the Semiconductor Device Mount Manual website http www necel com pkg en mount index html Caution The related documents listed abov...

Page 9: ...Circuits and Connection of Unused Pins 25 CHAPTER 3 CPU ARCHITECTURE 27 3 1 Memory Space 27 3 1 1 Internal program memory space 29 3 1 2 Internal data memory space 29 3 1 3 Special function register SFR area 30 3 1 4 Data memory addressing 30 3 2 Processor Registers 32 3 2 1 Control registers 32 3 2 2 General purpose registers 34 3 2 3 Special function registers SFRs 35 3 3 Instruction Address Add...

Page 10: ... oscillator 72 5 4 2 Crystal ceramic oscillator 72 5 4 3 External clock input circuit 74 5 4 4 Prescaler 74 5 5 Operation of CPU Clock Generator 75 5 6 Operation of Clock Generator Supplying Clock to Peripheral Hardware 80 CHAPTER 6 16 BIT TIMER EVENT COUNTER 00 82 6 1 Functions of 16 Bit Timer Event Counter 00 82 6 2 Configuration of 16 Bit Timer Event Counter 00 83 6 3 Registers to Control 16 Bi...

Page 11: ...on in STOP mode when low speed internal oscillator can be stopped by software is selected by option byte 153 9 4 4 Watchdog timer operation in HALT mode when low speed internal oscillator can be stopped by software is selected by option byte 155 CHAPTER 10 A D CONVERTER 156 10 1 Functions of A D Converter 156 10 2 Configuration of A D Converter 158 10 3 Registers Used by A D Converter 160 10 4 A D...

Page 12: ...ear Circuit 245 15 2 Configuration of Power on Clear Circuit 246 15 3 Operation of Power on Clear Circuit 246 15 4 Cautions for Power on Clear Circuit 247 CHAPTER 16 LOW VOLTAGE DETECTOR 249 16 1 Functions of Low Voltage Detector 249 16 2 Configuration of Low Voltage Detector 249 16 3 Registers Controlling Low Voltage Detector 250 16 4 Operation of Low Voltage Detector 252 16 5 Cautions for Low Vo...

Page 13: ...ramming mode 302 18 8 11 Examples of operation when interrupt disabled time should be minimized in self programming mode 309 CHAPTER 19 INSTRUCTION SET OVERVIEW 320 19 1 Operation 320 19 1 1 Operand identifiers and description methods 320 19 1 2 Description of Operation column 321 19 1 3 Description of Flag column 321 19 2 Operation List 322 19 3 Instructions Listed by Addressing Type 327 CHAPTER ...

Page 14: ...ES ON TARGET SYSTEM DESIGN 381 APPENDIX C REGISTER INDEX 383 C 1 Register Index Register Name 383 C 2 Register Index Symbol 385 APPENDIX D LIST OF CAUTIONS 387 APPENDIX E REVISION HISTORY 353 E 1 Major Revisions in This Edition 353 E 2 Revision History up to Previous Editions 356 ...

Page 15: ...channel 8 bit timer 2 channels Watchdog timer 1 channel O Serial interface UART LIN Local Interconnect Network bus supported 1 channel O 10 bit resolution A D converter 4 channels O Supply voltage VDD 2 0 to 5 5 V Note O Operating temperature range TA 40 to 85 C T product S product R product A product TA 40 to 125 C T2 product A2 product Note Use this product in a voltage range of 2 2 to 5 5 V bec...

Page 16: ... Devices Document No C11531E published by NEC Corporation to know the specification of quality grade standard grade and special grade on the devices and its recommended applications Part number list µPD78F9221MC T 5A4 µPD78F9222MC T 5A4 µPD78F9221MC T 5A4 A µPD78F9222MC T 5A4 A µPD78F9221MC T2 5A4 Note µPD78F9222MC T2 5A4 Note µPD78F9221MC T2 5A4 A Note µPD78F9222MC T2 5A4 A Note µPD78F9221MC S 5A...

Page 17: ... 3 4 5 6 7 8 9 10 P40 Note In the 78K0S KA1 VSS functions alternately as the ground potential of the A D converter Be sure to connect VSS to a stabilized GND 0 V ANI0 to ANI3 Analog input RESET Reset AVREF Analog reference voltage RxD6 Receive data INTP0 to INTP3 External interrupt input TI000 TI010 Timer input P20 to P23 Port 2 TO00 TOH1 Timer output P30 P31 P34 Port 3 TxD6 Transmit data P40 to P...

Page 18: ...TYP Crystal ceramic oscillation 1 to 10 MHz External clock input oscillation 1 to 10 MHz Clock for TMH1 and WDT oscillation frequency Low speed internal oscillation 240 kHz TYP CMOS I O 13 15 24 CMOS input 1 1 1 Port CMOS output 1 1 16 bit TM0 1 ch 8 bit TMH 1 ch 8 bit TM8 1 ch Timer WDT 1 ch Serial interface LIN Bus supporting UART 1 ch A D converter 10 bits 4 ch 2 7 to 5 5V Multiplier 8 bits 8 b...

Page 19: ...3 3 Port 12 System control High speed internal oscillator RESET P34 X1 P121 X2 P122 Low speed internal oscillator INTP0 P30 INTP1 P43 INTP2 P31 INTP3 P41 ANI0 P20 to ANI3 P23 4 A D converter AVREF 8 bit timer 80 Watchdog timer 8 bit timer H1 16 bit timer event counter 00 TO00 TI010 P31 TI000 P30 RxD6 P44 TxD6 P43 Serial interface UART6 Interrupt control Note In the 78K0S KA1 VSS functions alternat...

Page 20: ... pins CMOS input 1 pin CMOS output 1 pin Timer 16 bit timer event counter 1 channel 8 bit timer timer H1 1 channel 8 bit timer timer 80 1 channel Watchdog timer 1 channel Timer output 2 pins PWM 1 pin A D converter 10 bit resolution 4 channels Serial interface LIN bus supporting UART mode 1 channel External 4 Vectored interrupt sources Internal 9 Reset Reset by RESET pin Internal reset by watchdog...

Page 21: ... Input TI010 TO00 INTP2 P34 Note Input Port 3 Input only Input RESET Note P40 P41 INTP3 P42 TOH1 P43 TxD6 INTP1 P44 RxD6 P45 I O Port 4 6 bit I O port Can be set to input or output mode in 1 bit units An on chip pull up resistor can be connected by setting software Input P121 Note X1 Note P122 Note X2 Note P123 I O Port 12 3 bit I O port Can be set to input or output mode in 1 bit units An on chip...

Page 22: ... of 16 bit timer event counter 00 P30 INTP0 TI010 Input Capture trigger input to capture register CR000 of 16 bit timer event counter 00 Input P31 TO00 INTP2 TO00 Output 16 bit timer event counter 00 output Input P31 TI010 INTP2 TOH1 Output 8 bit timer H1 output Input P42 ANI0 to ANI3 Input Analog input of A D converter Input P20 to P23 AVREF Reference voltage of A D converter RESET Note Input Sys...

Page 23: ...as a RESET pin and when the power is turned on this is the reset function For the setting method for pin functions see CHAPTER 17 OPTION BYTE When P34 is used as an input port pin connect the pull up resistor P30 P31 and P34 can be set to the following operation modes in 1 bit units 1 Port mode P30 and P31 function as a 2 bit I O port Each bit of this port can be set to the input or output mode by...

Page 24: ...These are external interrupt request input pins for which the valid edge rising edge falling edge or both rising and falling edges can be specified b TOH1 This is the output pin of 8 bit timer H1 c TxD6 This pin outputs serial data from the asynchronous serial interface d RxD6 This pin inputs serial data to the asynchronous serial interface 2 2 4 P121 to P123 Port 12 P121 to P123 constitute a 3 bi...

Page 25: ...tion of Unused Pins Table 2 1 shows I O circuit type of each pin and the connections of unused pins For the configuration of the I O circuit of each type refer to Figure 2 1 Table 2 1 Types of Pin I O Circuits and Connection of Unused Pins Pin Name I O Circuit Type I O Recommended Connection of Unused Pin P20 ANI0 to P23 ANI3 11 Input Independently connect to AVREF or VSS via a resistor Output Lea...

Page 26: ...SS P ch N ch Input enable Pull up enable VDD P ch Pull up enable Data Output disable VDD P ch VDD P ch IN OUT N ch P ch Feedback cut off X1 IN OUT X2 IN OUT OSC enable Data Output disable VDD P ch N ch Data Output Disable P ch N ch Type 2 Type 3 C Type 8 A Type 16 B Type 11 Schmitt triggered input with hysteresis characteristics Comparator VSS VSS VSS VSS VSS ...

Page 27: ...Internal high speed RAM 128 8 bits Flash memory 2 048 8 bits Use prohibited Program memory space Data memory space Program area Option byte area Program area CALLT table area Vector table area F F F F H 0 7 F F H 0 0 8 0 H 0 0 7 F H 0 0 8 2 H 0 0 8 1 H 0 0 4 0 H 0 0 3 F H 0 0 2 2 H 0 0 2 1 H 0 0 0 0 H F F 0 0 H F E F F H F E 8 0 H F E 7 F H 0 8 0 0 H F 7 F F H 0 0 0 0 H Protect byte area Remark Th...

Page 28: ...bits Program memory space Data memory space Program area Option byte area Program area CALLT table area Vector table area Use prohibited F F F F H 0 F F F H 0 0 0 0 H 0 0 8 0 H 0 0 7 F H 0 0 8 2 H 0 0 8 1 H 0 0 4 0 H 0 0 3 F H 0 0 2 2 H 0 0 2 1 H F F 0 0 H F E F F H F E 0 0 H F D F F H 1 0 0 0 H 0 F F F H 0 0 0 0 H Protect byte area Remark The option byte and protect byte are 1 byte each ...

Page 29: ...ess and the higher 8 bits are stored in an odd address Table 3 2 Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H Reset 0012H INTAD 0006H INTLVI 0016H INTP2 0008H INTP0 0018H INTP3 000AH INP1 001AH INTTM80 000CH INTTMH1 001CH INTSRE6 000EH INTTM000 001EH INTSR6 0010H INTTM010 0020H INTST6 Caution No interrupt sources correspond to the vector table ad...

Page 30: ...or FE00H to FEFFH which contains a data memory and the special function register area SFR can be accessed using a unique addressing mode in accordance with each function Figures 3 3 and 3 4 illustrate the data memory addressing Figure 3 3 Data Memory Addressing µPD78F9221 Special function registers SFR 256 8 bits Internal high speed RAM 128 8 bits Flash memory 2 048 8 bits Use prohibted Direct add...

Page 31: ...egisters SFR 256 8 bits Internal high speed RAM 256 8 bits Flash memory 4 096 8 bits Use prohibited Direct addressing Register indirect addressing Based addressing SFR addressing Short direct addressing F F F F H F F 0 0 H F E F F H F F 2 0 H F E 1 F H F E 0 0 H F D F F H F E 2 0 H F E 1 F H 1 0 0 0 H 0 F F F H 0 0 0 0 H ...

Page 32: ...word PSW The program status word is an 8 bit register consisting of various flags to be set reset by instruction execution Program status word contents are stored in stack area upon interrupt request generation or PUSH PSW instruction execution and are restored upon execution of the RETI and POP PSW instructions Reset signal generation sets PSW to 02H Figure 3 6 Program Status Word Configuration 7...

Page 33: ...he SP is decremented before writing saving to the stack memory and is incremented after reading restoring from the stack memory Each stack operation saves restores data as shown in Figures 3 8 and 3 9 Caution Since reset signal generation makes the SP contents undefined be sure to initialize the SP before using the stack memory Figure 3 8 Data to Be Saved to Stack Memory Interrupt PSW PC15 to PC8 ...

Page 34: ...t registers in pairs can be used as a 16 bit register AX BC DE and HL Registers can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute names R0 to R7 and RP0 to RP3 Figure 3 10 General Purpose Register Configuration a Function names X 15 0 7 0 16 bit processing 8 bit processing HL DE BC AX A C B E D L H b Absolute names R0 15 0 7 0 16 bit processing 8 bit processi...

Page 35: ...bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describes a symbol reserved by the assembler for the 16 bit manipulation instruction operand When specifying an address describe an even address Table 3 3 lists the special function registers The meanings of the symbols in this table are as follows Symbol Indicates the addresses of ...

Page 36: ... 3 PM3 FF24H Port mode register 4 PM4 FF2CH Port mode register 12 PM12 FFH FF32H Pull up resistance option register 2 PU2 FF33H Pull up resistance option register 3 PU3 FF34H Pull up resistance option register 4 PU4 FF3CH Pull up resistance option register 12 PU12 00H FF48H Watchdog timer mode register WDTM 67H FF49H Watchdog timer enable register WDTE 9AH FF50H Low voltage detect register LVIM FF...

Page 37: ...D W Undefined FFA1H Flash status register PFS 00H FFA2H Flash programming mode control register FLPMC Undefined FFA3H Flash programming command register FLCMD 00H FFA4H Flash address pointer L FLAPL FFA5H Flash address pointer H FLAPH Undefined FFA6H Flash address pointer H compare register FLAPHC FFA7H Flash address pointer L compare register FLAPLC FFA8H Flash write buffer register FLW FFCCH 8 b...

Page 38: ...Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC to branch The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes the sign bit In other words the range of branch in relative addressing is be...

Page 39: ...r High addr PC PC 1 PC 2 3 3 3 Table indirect addressing Function The table contents branch destination address of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter PC to branch Table indirect addressing is carried out when the CALLT addr5 instruction is executed This instruction can be used to branch to ...

Page 40: ... 4 Register addressing Function The register pair AX contents to be specified with an instruction word are transferred to the program counter PC to branch This function is carried out when the BR AX instruction is executed Illustration 7 0 rp 0 7 A X 15 0 PC 8 7 ...

Page 41: ...ruction execution 3 4 1 Direct addressing Function The memory indicated by immediate data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE80H When setting addr16 to FE80H Instruction code 0 0 1 0 1 0 0 1 OP code 1 0 0 0 0 0 0 0 80H 1 1 1 1 1 1 1 0 FEH Illustration 7 0 OP code addr16 low addr16 hig...

Page 42: ...nd these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is cleared to 0 When it is at 00H to 1FH bit 8 is set to 1 See Illustration below Operand format Identifier Description saddr µPD78F9221 Label or FE80H to FF1FH immediate data µPD78F9222 Label or FE20H to FF1FH immediate data saddrp µPD78F9221 Label or F...

Page 43: ...ction word This addressing is applied to the 256 byte space FF00H to FFFFH However SFRs mapped at FF00H to FF1FH are accessed with short direct addressing Operand format Identifier Description sfr Special function register name Description example MOV PM0 A When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 Illustration 15 0 SFR Effective address 1 1 1 1 1 1 1 8 7 0 7 OP c...

Page 44: ...at is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the instruction code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described with absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C When selecting the C register for r Instructio...

Page 45: ... accessed is specified with the register pair specify code in the instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Description DE HL Description example MOV A DE When selecting register pair DE Instruction code 0 0 1 0 1 0 1 1 Illustration 15 0 8 D 7 E 0 7 7 0 A DE The contents of addressed memory are transferred Memory address specified by re...

Page 46: ...ddition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL byte Description example MOV A HL 10H When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 Illustration 16 0 8 H 7 L 0 7 7 0 A HL The contents of addressed me...

Page 47: ...hod is automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is saved restored upon interrupt request generation Stack addressing can be used to access the internal high speed RAM area only Description example In the case of PUSH DE Instruction code 1 0 1 0 1 0 1 0 Illustration FEE0H FEE0H FEDFH FEDEH D E FEDEH SP SP 7 0 Memory ...

Page 48: ...hich can be used for various control operations Table 4 1 shows the functions of each port In addition to digital I O port functions each of these ports has an alternate function For details refer to CHAPTER 2 PIN FUNCTIONS Figure 4 1 Port Functions P45 Port 4 P20 Port 2 P23 P30 P31 Port 3 P40 Port 13 P130 P34 P121 P123 Port 12 ...

Page 49: ... Note X2 Note P123 I O Port 12 3 bit I O port Can be set to input or output mode in 1 bit units On chip pull up resistor can be connected only to P123 by setting software Input P130 Output Port 13 1 bit output only port Output Note For the setting method for pin functions see CHAPTER 17 OPTION BYTE Caution The P121 X1 and P122 X2 pins are pulled down during reset Remarks 1 P121 and P122 can be all...

Page 50: ...on register 2 PU2 This port is also used as the analog input pins of the internal A D converter Reset signal generation sets port 2 to the input mode Figure 4 2 shows the block diagram of port 2 Figure 4 2 Block Diagram of P20 to P23 P20 ANI0 to P23 ANI3 WRPU RD PU20 to PU23 WRPM PM20 to PM23 VDD P ch PU2 PMC2 PM2 WRPORT Output latch P20 to P23 PMC20 to PMC23 A D converter Internal bus Selector WR...

Page 51: ...st input pin functions Reset signal generation sets port 3 to the input mode P34 is a 1 bit input only port This pin is also used as a RESET pin and when the power is turned on this is the reset function For the setting method for pin functions see CHAPTER 17 OPTION BYTE When P34 is used as an input port pin connect the pull up resistor Figures 4 3 to 4 5 show the block diagrams of port 3 Figure 4...

Page 52: ...iagram of P31 P31 TI010 TO00 INTP2 WRPU RD WRPORT WRPM PU31 Output latch P31 PM31 Alternate function VDD P ch PU3 PM3 Internal bus Selector Alternate function P3 P3 Port register 3 PU3 Pull up resistor option register 3 PM3 Port mode register 3 RD Read signal WR Write signal ...

Page 53: ...e if low level is input to the RESET pin before the referencing then the reset state is not released When it is used as an input port pin connect the pull up resistor 4 2 3 Port 4 Port 4 is a 6 bit I O port with an output latch Each bit of this port can be set to the input or output mode by using port mode register 4 PM4 When the P40 to P45 pins are used as an input port an on chip pull up resisto...

Page 54: ...ure 4 6 Block Diagram of P40 and P45 P40 P45 WRPU RD WRPORT WRPM PU40 PU45 Output latch P40 P45 PM40 PM45 VDD P ch PU4 PM4 Internal bus Selector P4 P4 Port register 4 PU4 Pull up resistor option register 4 PM4 Port mode register 4 RD Read signal WR Write signal ...

Page 55: ...iagram of P41 and P44 P41 INTP3 P44 RxD6 WRPU RD WRPORT WRPM PU41 PU44 Alternate function Output latch P41 P44 PM41 PM44 VDD P ch PU4 PM4 Internal bus Selector P4 P4 Port register 4 PU4 Pull up resistor option register 4 PM4 Port mode register 4 RD Read signal WR Write signal ...

Page 56: ...gure 4 8 Block Diagram of P42 P42 TOH1 WRPU RD WRPORT WRPM PU42 Output latch P42 PM42 Alternate function VDD P ch PM4 PU4 Internal bus Selector P4 P4 Port register 4 PU4 Pull up resistor option register 4 PM4 Port mode register 4 RD Read signal WR Write signal ...

Page 57: ...k Diagram of P43 P43 TxD6 INTP1 WRPU RD WRPORT WRPM PU43 Output latch P43 PM43 Alternate function VDD P ch PU4 PM4 Internal bus Selector Alternate function P4 P4 Port register 4 PU4 Pull up resistor option register 4 PM4 Port mode register 4 RD Read signal WR Write signal ...

Page 58: ...eed internal oscillator The P121 and P122 pins can be used as I O port pins 2 Crystal ceramic oscillator The P121 and P122 pins cannot be used as I O port pins because they are used as the X1 and X2 pins 3 External clock input The P121 pin is used as the X1 pin to input an external clock and therefore it cannot be used as an I O port pin The P122 pin can be used as an I O port pin The system clock...

Page 59: ...9 Figure 4 11 Block Diagram of P123 P123 WRPU RD WRPORT WRPM PU123 Output latch P123 PM123 VDD P ch PM12 PU12 Internal bus Selector P12 P12 Port register 12 PU12 Pull up resistor option register 12 PM12 Port mode register 12 RD Read signal WR Write signal ...

Page 60: ...ort registers P2 P3 P4 P12 P13 Port mode control register 2 PMC2 Pull up resistor option registers PU2 PU3 PU4 PU12 1 Port mode registers PM2 PM3 PM4 PM12 These registers are used to set the corresponding port to the input or output mode in 1 bit units Each port mode register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets these registers to FFH When a p...

Page 61: ...1 1 1 1 PM123 PM122 PM121 1 PMmn Selection of I O mode of Pmn pin m 2 3 4 or 12 n 0 to 5 0 Output mode output buffer ON 1 Input mode output buffer OFF 2 Port registers P2 P3 P4 P12 P13 These registers are used to write data to be output from the corresponding port pin to an external device connected to the chip When a port register is read the pin level is read in the input mode and the value of t...

Page 62: ...6 5 4 3 2 1 0 P12 0 0 0 0 P123 P122 P121 0 Address FF0DH After reset 00H Output latch R W Symbol 7 6 5 4 3 2 1 0 P13 0 0 0 0 0 0 0 P130 m 2 3 4 12 or 13 n 0 5 Pmn Controls of output data in output mode Input data read in input mode 0 Output 0 Input low level 1 Output 1 Input high level Note Because P34 is read only its reset value is undefined 3 Port mode control register 2 PMC2 This register spec...

Page 63: ...Setting of Port Mode Register Port Register Output Latch and Port Mode Control Register When Alternate Function Is Used Alternate Function Pin Port Name Name I O PM P PMC2n n 0 to 3 P20 to P23 ANI0 to ANI3 Input 1 1 TI000 Input 1 P30 INTP0 Input 1 TO00 Output 0 0 TI010 Input 1 P31 INTP2 Input 1 P41 INTP3 Input 1 P42 TOH1 Output 0 0 TxD6 Output 0 1 P43 INTP1 Input 1 P44 RxD6 Input 1 Remark don t ca...

Page 64: ...ipulation instruction Reset signal generation set these registers to 00H Figure 4 16 Format of Pull up Resistor Option Register Address FF32H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU2 0 0 0 0 PU23 PU22 PU21 PU20 Address FF33H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU3 0 0 0 0 0 0 PU31 PU30 Address FF34H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PU4 0 0 PU45 PU44 PU43 PU42 PU41 PU40 Addre...

Page 65: ...off however the pin status remains unchanged Once data is written to the output latch it is retained until new data is written to the output latch When a reset signal is generated cleans the data in the output latch 4 4 2 Reading from I O port 1 In output mode The data of the output latch can be read by a transfer instruction The data of the output latch remain unchanged 2 In input mode The pin st...

Page 66: ... X1 and X2 pins It can oscillate a clock of 1 to 10 MHz Oscillation of this circuit can be stopped by execution of the STOP instruction External clock input circuit This circuit supplies a clock from an external IC to the X1 pin A clock of 1 to 10 MHz can be supplied Internal clock supply can be stopped by execution of the STOP instruction If the external clock input is selected as the system cloc...

Page 67: ...tion of Clock Generators Item Configuration Control registers Processor clock control register PCC Preprocessor clock control register PPCC Low speed internal oscillation mode register LSRCM Oscillation stabilization time select register OSTS Oscillators Crystal ceramic oscillator High speed internal oscillator External clock input circuit Low speed internal oscillator ...

Page 68: ...rol register PCC System clock oscillation stabilization time counter Selector Prescaler Clock to peripheral hardware fXP 8 bit timer H1 watchdog timer Option byte 1 Cannot be stopped 0 Can be stopped Low speed internal oscillation mode register LSRCM Low speed internal oscillator Prescaler System clock oscillatorNote External clock input Crystal ceramic oscillation High speed internal oscillation ...

Page 69: ...et by using a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets PCC and PPCC to 02H Figure 5 2 Format of Processor Clock Control Register PCC Address FFFBH After reset 02H R W Symbol 7 6 5 4 3 2 1 0 PCC 0 0 0 0 0 0 PCC1 0 Figure 5 3 Format of Preprocessor Clock Control Register PPCC Address FFF3H After reset 02H R W Symbol 7 6 5 4 3 2 1 0 PPCC 0 0 0 0 0 0 PPCC1 PPCC0 PPCC...

Page 70: ...llation mode register LSRCM This register is used to select the operation mode of the low speed internal oscillator 240 kHz TYP This register is valid when it is specified by the option byte that the low speed internal oscillator can be stopped by software If it is specified by the option byte that the low speed internal oscillator cannot be stopped by software setting of this register is invalid ...

Page 71: ...TS Address FFF4H After reset Undefined R W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0 OSTS1 OSTS0 Selection of oscillation stabilization time 0 0 2 10 fX 102 4 µs 0 1 2 12 fX 409 6 µs 1 0 2 15 fX 3 27 ms 1 1 2 17 fX 13 1 ms Cautions 1 To set and then release the STOP mode set the oscillation stabilization time as follows Expected oscillation stabilization time of resonator Oscillation sta...

Page 72: ...een the X1 and X2 pins If the crystal ceramic oscillator is selected by the option byte as the system clock source the X1 and X2 pins are used as crystal or ceramic resonator connection pins For details of the option byte refer to CHAPTER 17 OPTION BYTE For details of I O ports refer to CHAPTER 4 PORT FUNCTIONS Figure 5 6 shows the external circuit of the crystal ceramic oscillator Figure 5 6 Exte...

Page 73: ...7 Examples of Incorrect Resonator Connection 1 2 a Too long wiring of connected circuit b Crossed signal lines VSS X1 X2 VSS X1 X2 PORT c Wiring near high fluctuating current d Current flowing through ground line of oscillator Potential at points A B and C fluctuates VSS X1 X2 High current VSS X1 X2 PORT VDD A B C High current ...

Page 74: ... option byte refer to CHAPTER 17 OPTION BYTE For details of I O ports refer to CHAPTER 4 PORT FUNCTIONS 5 4 4 Prescaler The prescaler divides the clock fX output by the system clock oscillator to generate a clock fXP to be supplied to the peripheral hardware It also divides the clock to peripheral hardware fXP to generate a clock to be supplied to the CPU Remark The clock output by the oscillator ...

Page 75: ...ed internal oscillator is selected as the oscillator the CPU can be started without having to wait for the oscillation stabilization time of the system clock Therefore the start time can be shortened Improvement of expandability If the high speed internal oscillator is selected as the oscillator the X1 and X2 pins can be used as I O port pins For details refer to CHAPTER 4 PORT FUNCTIONS Figures 5...

Page 76: ...with PCC 02H PPCC 02H HALT STOP Interrupt Reset signal Interrupt Power application Reset by power on clear High speed internal oscillator selected by option byte Clock division ratio variable during CPU operation Remark PCC Processor clock control register PPCC Preprocessor clock control register 2 Crystal ceramic oscillator If crystal ceramic oscillation is selected by the option byte a clock fre...

Page 77: ...TE The oscillation stabilization time that elapses after the STOP mode is released is selected by the oscillation stabilization time select register OSTS a The internal reset signal is generated by the power on clear function on power application the option byte is referenced after reset and the system clock is selected b After high speed internal oscillation clock is generated the option byte is ...

Page 78: ...processor clock control register 3 External clock input circuit If external clock input is selected by the option byte the following is possible High speed operation The accuracy of processing is improved as compared with high speed internal oscillation 8 MHz TYP because an oscillation frequency of 1 to 10 MHz can be selected and an external clock with a small frequency deviation can be supplied I...

Page 79: ...er application the option byte is referenced after reset and the system clock is selected b The option byte is referenced and the system clock is selected Then the external clock operates as the system clock Figure 5 13 Status Transition of Default Start by External Clock Input HALT STOP HALT instruction STOP instruction VDD 2 1 V 0 1 V Start with PCC 02H PPCC 02H Interrupt Reset signal Interrupt ...

Page 80: ...cannot be stopped by software If it is specified that the low speed internal oscillator can be stopped by software oscillation can be started or stopped by using the low speed internal oscillation mode register LSRCM If it is specified that it cannot be stopped by software the clock source of WDT is fixed to the low speed internal oscillation clock fRL The low speed internal oscillator is independ...

Page 81: ...xed to fRL Low speed internal oscillator can be stopped Low speed internal oscillator cannot be stopped Low speed internal oscillator stops LSRSTOP 1 VDD 2 1 V 0 1 V Reset signal Power application Reset by power on clear Select by option byte if low speed internal oscillator can be stopped or not Note The clock source of the watchdog timer WDT is selected from fX or fRL or it may be stopped For de...

Page 82: ...th or more of a signal input externally Valid level pulse width 2 fXP or more 3 Pulse width measurement 16 bit timer event counter 00 can measure the pulse width of an externally input signal Valid level pulse width 2 fXP or more 4 Square wave output 16 bit timer event counter 00 can output a square wave with any selected frequency Cycle 2 to 65536 2 count clock cycle 5 PPG output 16 bit timer eve...

Page 83: ... mode register 3 PM3 Port register 3 P3 Figures 6 1 shows a block diagram of these counters Figure 6 1 Block Diagram of 16 Bit Timer Event Counter 00 Internal bus Capture compare control register 00 CRC00 TI010 TO00 INTP2 P31 fXP fXP 22 fXP 28 fX TI000 INTP0 P30 Prescaler mode register 00 PRM00 2 PRM001 PRM000 CRC002 16 bit timer capture compare register 010 CR010 Match Match 16 bit timer counter ...

Page 84: ...since the input of the count clock is temporarily stopped and then resumed after the read 2 16 bit timer capture compare register 000 CR000 CR000 is a 16 bit register which has the functions of both a capture register and a compare register Whether it is used as a capture register or as a compare register is set by bit 0 CRC000 of capture compare control register 00 CRC00 CR000 is set by 16 bit me...

Page 85: ...art mode using the valid edge of TI000 pin if CR000 is set to 0000H an interrupt request INTTM000 is generated when CR000 changes from 0000H to 0001H following overflow FFFFH 2 If the new value of CR000 is less than the value of 16 bit timer counter 0 TM00 TM00 continues counting overflows and then starts counting from 0 again If the new value of CR000 is less than the old value therefore the time...

Page 86: ...es Both rising and falling edges 1 1 Remarks 1 Setting ES010 ES000 1 0 is prohibited 2 ES010 ES000 Bits 5 and 4 of prescaler mode register 00 PRM00 CRC002 Bit 2 of capture compare control register 00 CRC00 Cautions 1 In the free running mode and in the clear start mode using the valid edge of the TI000 pin if CR010 is set to 0000H an interrupt request INTTM010 is generated when CR010 changes from ...

Page 87: ...ister 00 PRM00 Port mode register 3 PM3 Port register 3 P3 1 16 bit timer mode control register 00 TMC00 This register sets the 16 bit timer operating mode the 16 bit timer counter 00 TM00 clear mode and output timing and detects an overflow TMC00 is set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets the value of TMC00 to 00H Caution 16 bit timer counter 00 TM00 s...

Page 88: ...the OVF00 flag is set to 1 6 Even if the OVF00 flag is cleared before the next count clock is counted before TM00 becomes 0001H after the occurrence of a TM00 overflow the OVF00 flag is re set newly and clear is disabled 7 The capture operation is performed at the fall of the count clock An interrupt request input INTTM0n0 however occurs at the rise of the next count clock Remark TM00 16 bit timer...

Page 89: ...er selection 0 Capture on valid edge of TI010 pin 1 Capture on valid edge of TI000 pin by reverse phase Note CRC000 CR000 operating mode selection 0 Operate as compare register 1 Operate as capture register Note When the CRC001 bit value is 1 capture is not performed if both the rising and falling edges have been selected as the valid edges of the TI000 pin Cautions 1 The timer operation must be s...

Page 90: ...ion operation LVS00 LVR00 Timer output F F status setting 0 0 No change 0 1 Timer output F F reset 0 1 0 Timer output F F set 1 1 1 Setting prohibited TOC001 Timer output F F control using match of CR000 and TM00 0 Disables inversion operation 1 Enables inversion operation TOE00 Timer output control 0 Disables output output fixed to level 0 1 Enables output Note The one shot pulse output mode oper...

Page 91: ...7 6 5 4 3 2 1 0 PRM00 ES110 ES100 ES010 ES000 0 0 PRM001 PRM000 ES110 ES100 TI010 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges ES010 ES000 TI000 pin valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both falling and rising edges PRM001 PRM000 Count clock selection 0 0 fXP 10 MHz 0 1 fXP 2 2 2 5 MHz...

Page 92: ... valid edge of the TI0n0 pin a rising edge is detected immediately after the TM00 operation is enabled 4 The sampling clock used to eliminate noise differs when a TI000 valid edge is used as the count clock and when it is used as a capture trigger In the former case the count clock is fXP and in the latter case the count clock is selected by prescaler mode register 00 PRM00 The capture operation i...

Page 93: ...he set value Caution Changing the CR000 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation Remark For how to enable the INTTM000 interrupt see CHAPTER 12 INTERRUPT FUNCTIONS Interrupt requests are generated repeatedly using the count value set in 16 bit timer ...

Page 94: ...etting 10 is prohibited c 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 1 TMC002 1 TMC001 0 1 OVF00 0 TMC00 Clears and starts on match between TM00 and CR000 Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with the interval timer See the description of the respective control registers for details Figure 6 11 Interval Timer Configuration Diagram 16 b...

Page 95: ... from 0 Thus if the value M after the CR000 change is smaller than that N before the change it is necessary to restart the timer after changing CR000 Figure 6 13 Timing After Change of Compare Register During Timer Count Operation N M N M CR000 N M Count clock TM00 count value X 1 X FFFFH 0000H 0001H 0002H Remark N X M 6 4 2 External event counter operation Setting The basic operation setting proc...

Page 96: ...rried out only when the valid edge of the TI000 pin is detected twice after sampling with the internal clock fXP noise with a short pulse width can be removed Figure 6 14 Control Register Settings in External Event Counter Mode with Rising Edge Specified a Capture compare control register 00 CRC00 7 0 6 0 5 0 4 0 3 0 CRC002 0 1 CRC001 0 1 CRC000 0 CRC00 CR000 used as compare register b Prescaler m...

Page 97: ...ternal Event Counter Operation Timing with Rising Edge Specified 1 INTTM000 generation timing immediately after operation starts Counting is started after a valid edge is detected twice CR000 INTTM000 0000H 0001H 0002H 0003H N 2 N 1 N 0000H 0001H 0002H N 1 2 3 Count starts TI000 pin input TM00 count value Timer operation starts 2 INTTM000 generation timing after INTTM000 has been generated twice C...

Page 98: ...idth is sampled in the count clock cycle selected by prescaler mode register 00 PRM00 and the valid level of the TI000 or TI010 pin is detected twice thus eliminating noise with a short pulse width Figure 6 17 CR010 Capture Operation with Rising Edge Specified Count clock TM00 TI000 Rising edge detection CR010 INTTM010 N 3 N 2 N 1 N N 1 N Setting The basic operation setting procedure is as follows...

Page 99: ...on The measurable pulse width in this operation example is up to 1 cycle of the timer counter Figure 6 18 Control Register Settings for Pulse Width Measurement with Free Running Counter and One Capture Register When TI000 and CR010 Are Used a Capture compare control register 00 CRC00 7 0 6 0 5 0 4 0 3 0 CRC002 1 CRC001 0 1 CRC000 0 CRC00 CR000 used as compare register CR010 used as capture registe...

Page 100: ...ossible to simultaneously measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin Specify both the rising and falling edges as the valid edges of the TI000 and TI010 pins by using bits 4 and 5 ES000 and ES010 and bits 6 and 7 ES100 and ES110 of PRM00 When the valid edge specified by bits 4 and 5 ES000 and ES010 of PRM00 is input to the TI000 pin the value of TM00 is ta...

Page 101: ...res valid edge of TI010 pin to CR000 CR010 used as capture register b Prescaler mode register 00 PRM00 ES110 1 ES100 1 ES010 1 ES000 1 3 0 2 0 PRM001 0 1 PRM000 0 1 PRM00 Selects count clock setting 11 is prohibited Specifies both edges for pulse width detection Specifies both edges for pulse width detection c 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 0 TMC002 1 TMC001 0 1...

Page 102: ... input to the TI000 pin Specify both the rising and falling edges as the valid edges of the TI000 pin by using bits 4 and 5 ES000 and ES010 of PRM00 When the valid edge specified by bits 4 and 5 ES000 and ES010 of PRM00 is input to the TI010 pin the value of TM00 is taken into 16 bit timer capture compare register 000 CR010 and an interrupt request signal INTTM010 is set Also when the inverse edge...

Page 103: ...ing edge for pulse width detection Setting invalid setting 10 is prohibited c 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 0 TMC002 1 TMC001 0 1 OVF00 0 TMC00 Free running mode Note If the valid edge of TI000 pin is specified to be both the rising and falling edges 16 bit timer capture compare register 000 CR000 cannot perform the capture operation When the CRC001 bit value i...

Page 104: ...lue of 16 bit timer counter 00 TM00 is taken into 16 bit timer capture compare register 010 CR010 and then the pulse width of the signal input to the TI000 pin is measured by clearing TM00 and restarting the count Sampling is performed at the interval selected by prescaler mode register 00 PRM00 and a capture operation is only performed when a valid level of the TI000 pin is detected twice thus el...

Page 105: ...ing 10 is prohibited c 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 1 TMC002 0 TMC001 0 1 OVF00 0 TMC00 Clears and starts at valid edge of TI000 pin Note If the valid edge of TI000 pin is specified to be both the rising and falling edges 16 bit timer capture compare register 000 CR000 cannot perform the capture operation Figure 6 26 Timing of Pulse Width Measurement Operation...

Page 106: ...6 3 5 Port mode register 3 PM3 2 For how to enable the INTTM000 interrupt see CHAPTER 12 INTERRUPT FUNCTIONS A square wave with any selected frequency can be output at intervals determined by the count value preset to 16 bit timer capture compare register 000 CR000 The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 1 by setting bit 0 TOE00 and bit 1 T...

Page 107: ... is prohibited Does not invert output on match between TM00 and CR010 Disables one shot pulse output d 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 1 TMC002 1 TMC001 0 OVF00 0 TMC00 Clears and starts on match between TM00 and CR000 Remark 0 1 Setting 0 or 1 allows another function to be used simultaneously with square wave output See the description of the respective control ...

Page 108: ... count clock by using the PRM00 register 6 Set the TMC00 register to start the operation see Figure 6 29 for the set value Caution Changing the CRC0n0 setting during TM00 operation may cause a malfunction To change the setting refer to 6 5 Cautions Related to 16 Bit Timer Event Counter 00 17 Changing compare register during timer operation Remarks 1 For the setting of the TO00 pin see 6 3 5 Port m...

Page 109: ...F F setting 11 is prohibited Inverts output on match between TM00 and CR010 Disables one shot pulse output c Prescaler mode register 00 PRM00 ES110 0 1 ES100 0 1 ES010 0 1 ES000 0 1 3 0 2 0 PRM001 0 1 PRM000 0 1 PRM00 Selects count clock Setting invalid setting 10 is prohibited Setting invalid setting 10 is prohibited d 16 bit timer mode control register 00 TMC00 7 0 6 0 5 0 4 0 TMC003 1 TMC002 1 ...

Page 110: ...TM00 Clear circuit Noise eliminator fXP fXP fXP 22 fXP 28 TI000 INTP0 P30 16 bit timer capture compare register 010 CR010 TO00 TI010 INTP2 P31 Selector Output controller Figure 6 31 PPG Output Operation Timing t 0000H 0000H 0001H 0001H M 1 Count clock TM00 count value TO00 Pulse width M 1 t 1 cycle N 1 t N CR000 capture value CR010 capture value M M N 1 N N Clear Clear Remark 0000H M N FFFFH ...

Page 111: ... by setting bit 6 OSPT00 of the TOC00 register to 1 by software By setting the OSPT00 bit to 1 16 bit timer event counter 00 is cleared and started and its output becomes active at the count value N set in advance to 16 bit timer capture compare register 010 CR010 After that the output becomes inactive at the count value M set in advance to 16 bit timer capture compare register 000 CR000 Note Even...

Page 112: ...5 4 3 CRC00 CRC002 CRC001 CRC000 CR000 as compare register CR010 as compare register 0 0 1 0 c 16 bit timer output control register 00 TOC00 0 7 0 1 1 0 1 TOC00 LVR00 LVS00 TOC004 OSPE00 OSPT00 TOC001 TOE00 Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00 output F F setting 11 is prohibited Inverts output upon match between TM00 and CR010 Sets on...

Page 113: ...n Figure 6 34 and by using the valid edge of the TI000 pin as an external trigger The valid edge of the TI000 pin is specified by bits 4 and 5 ES000 ES010 of prescaler mode register 00 PRM00 The rising falling or both the rising and falling edges can be specified When the valid edge of the TI000 pin is detected the 16 bit timer event counter is cleared and started and the output becomes active at ...

Page 114: ... CRC00 0 0 0 0 0 7 6 5 4 3 CRC00 CRC002 CRC001 CRC000 CR000 used as compare register CR010 used as compare register 0 0 1 0 c 16 bit timer output control register 00 TOC00 0 7 0 1 1 0 1 TOC00 LVR00 TOC001 TOE00 OSPE00 OSPT00 TOC004 LVS00 Enables TO00 output Inverts output upon match between TM00 and CR000 Specifies initial value of TO00 output F F setting 11 is prohibited Inverts output upon match...

Page 115: ...fied 0000H N N N N N M M M M M N 1 N 2 M 1 M 2 M 2 M 1 0001H 0000H Count clock TM00 count value CR010 set value CR000 set value TI000 pin input INTTM010 INTTM000 TO00 pin output When TMC00 is set to 08H TM00 count starts t Caution 16 bit timer counter 00 starts operating as soon as a value other than 00 operation stop mode is set to the TMC002 and TMC003 bits Remark N M ...

Page 116: ...stopped and then resumed after the read 4 If the timer is stopped timer counts and timer interrupts do not occur even if a signal is input to the TI000 TI010 pins 3 Setting of 16 bit timer capture compare registers 000 010 CR000 CR010 1 Set 16 bit timer capture compare register 000 CR000 to other than 0000H in the clear start mode entered on match between TM00 and CR000 This means a 1 pulse count ...

Page 117: ...Always set data to PRM00 after stopping the timer operation 9 Valid edge setting Set the valid edge of the TI000 pin with bits 4 and 5 ES000 and ES010 of prescaler mode register 00 PRM00 after stopping the timer operation 10 One shot pulse output One shot pulse output normally operates only in the free running mode or in the clear start mode at the valid edge of the TI000 pin Because an overflow d...

Page 118: ...n of OVF00 flag 1 The OVF00 flag is also set to 1 in the following case Either of the clear start mode entered on a match between TM00 and CR000 clear start at the valid edge of the TI000 pin or free running mode is selected CR000 is set to FFFFH When TM00 is counted up from FFFFH to 0000H Figure 6 37 Operation Timing of OVF00 Flag Count clock CR000 TM00 OVF00 INTTM000 FFFFH FFFEH FFFFH 0000H 0001...

Page 119: ...dge of the TI000 pin 2 When the CRC001 bit value is 1 capture is not performed in the CR000 register if both the rising and falling edges have been selected as the valid edges of the TI000 pin 3 When the CRC001 bit value is 1 the TM00 count value is not captured in the CR000 register when a valid edge of the TI010 pin is detected but the input from the TI010 pin can be used as an external interrup...

Page 120: ...etween TM00 and CR000 TOC001 1 6 Clear the interrupt request flag of INTTM000 TMIF000 0 7 Enable the INTTM000 interrupt TMMK000 0 Changing duty CR010 1 Disable the timer output inversion operation at the match between TM00 and CR010 TOC004 0 2 Disable the INTTM000 interrupt TMMK000 1 3 Rewrite CR010 4 Wait for 1 cycle of the TM00 count clock 5 Enable the timer output inversion operation at the mat...

Page 121: ...enabled Remark n 0 1 2 The sampling clock used to remove noise differs when a TI000 valid edge is used as the count clock and when it is used as a capture trigger In the former case the count clock is fXP and in the latter case the count clock is selected by prescaler mode register 00 PRM00 The capture operation is not performed until the valid edge is sampled and the valid level is detected twice...

Page 122: ...me Resolution 2 6 fXP 8 µs 2 14 fXP 2 05 ms 2 6 fXP 8 µs 2 8 fXP 32 µs 2 16 fXP 8 19 ms 2 8 fXP 32 µs 2 10 fXP 128 µs 2 18 fXP 32 7 ms 2 10 fXP 128 µs fXP 8 0 MHz 2 16 fXP 8 19 ms 2 24 fXP 2 01 s 2 16 fXP 8 19 ms 2 6 fXP 6 4 µs 2 14 fXP 1 64 ms 2 6 fXP 6 4 µs 2 8 fXP 25 6 µs 2 16 fXP 6 55 ms 2 8 fXP 25 6 µs 2 10 fXP 102 µs 2 18 fXP 26 2 ms 2 10 fXP 102 µs fXP 10 0 MHz 2 16 fXP 6 55 ms 2 24 fXP 1 6...

Page 123: ... counter 80 TM80 Register 8 bit compare register 80 CR80 Control register 8 bit timer mode control register 80 TMC80 Figure 7 1 Block Diagram of 8 Bit Timer 80 Internal bus Internal bus 8 bit compare register 80 CR80 Match 8 bit timer counter 80 TM80 Clear INTTM80 fXP 26 fXP 216 TCE80 TCL801 TCL800 8 bit timer mode control register 80 TMC80 fXP 28 fXP 210 Selector Remark fXP Oscillation frequency ...

Page 124: ...igure 7 2 Format of 8 Bit Compare Register 80 CR80 Symbol CR80 Address FFCDH After reset Undefined W 7 6 5 4 3 2 1 0 Caution When changing the value of CR80 be sure to stop the timer operation If the value of CR80 is changed with the timer operation enabled a match interrupt request signal is generated immediately and the timer may be cleared 2 8 bit timer counter 80 TM80 This 8 bit register count...

Page 125: ... clears TMC80 to 00H Figure 7 4 Format of 8 Bit Timer Mode Control Register 80 TMC80 Address FFCCH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TMC80 TCE80 0 0 0 0 TCL801 TCL800 0 TCE80 Control of operation of TM80 0 Stop operation clear TM80 to 00H 1 Enable operation Selection of count clock of 8 bit timer 80 TCL801 TCL800 fXP 8 0 MHz fXP 10 0 MHz 0 0 fXP 2 6 125 kHz 156 3 kHz 0 1 fXP 2 8 31 25 kHz...

Page 126: ...ue of CR80 is changed with the timer operation enabled a match interrupt request signal may be generated immediately 2 If the count clock of TMC80 is set and the operation of TM80 is enabled at the same time by using an 8 bit memory manipulation instruction the error of one cycle after the timer is started may be 1 clock or more refer to 7 5 1 Error when timer starts Therefore be sure to follow th...

Page 127: ...Timing of Interval Timer Operation Clear Clear Count start Interval time Interval time Count clock TM80 count value CR80 TCE80 INTTM80 N 01H 00H N 01H 00H N 00H 01H N N N N t Interrupt request generated Interrupt request generated Remark Interval time N 1 t N 00H to FFH ...

Page 128: ...fer to Figure 7 6 Figure 7 6 Case Where Error of 1 5 Clocks Max Occurs 8 bit timer counter 80 TM80 Count pulse Clear signal Selected clock TCE80 Delay A Delay B Selected clock TCE80 Clear signal Count pulse TM80 count value 00H 01H 02H 03H Delay A Delay B If the timer is started when the selected clock is high and if delay A delay B an error of up to 1 5 clocks occurs 2 Setting of 8 bit compare re...

Page 129: ... 8 Bit Timer H1 8 bit timer H1 consists of the following hardware Table 8 1 Configuration of 8 Bit Timer H1 Item Configuration Timer register 8 bit timer counter H1 Registers 8 bit timer H compare register 01 CMP01 8 bit timer H compare register 11 CMP11 Timer output TOH1 Control registers 8 bit timer H mode register 1 TMHMD1 Port mode register 4 PM4 Port register 4 P4 Figure 8 1 shows a block dia...

Page 130: ...D10 TOLEV1 TOEN1 8 bit timer H mode register 1 TMHMD1 8 bit timer H compare register 11 CMP11 Decoder TOH1 P42 INTTMH1 Selector fXP fXP 22 fXP 24 fXP 26 fXP 212 fRL 27 Interrupt generator Output controller Level inversion 1 0 F F R 8 bit timer counter H1 PWM mode signal Timer H enable signal Clear 3 2 8 bit timer H compare register 01 CMP01 Output latch P42 PM42 ...

Page 131: ...it Timer H Compare Register 11 CMP11 Symbol CMP11 Address FF0FH After reset 00H R W 7 6 5 4 3 2 1 0 CMP11 can be rewritten during timer count operation If the CMP11 value is rewritten during timer operation the compare value after the rewrite takes effect at the timing at which the count value and the compare value before the rewrite match If the timing at which the count value and compare value m...

Page 132: ...s are used to control 8 Bit Timer H1 8 bit timer H mode register 1 TMHMD1 Port mode register 4 PM4 Port register 4 P4 1 8 bit timer H mode register 1 TMHMD1 This register controls the mode of timer H This register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to 00H ...

Page 133: ...r mode PWM output mode Setting prohibited TMMD11 0 1 TMMD10 0 0 Timer operation mode Low level High level TOLEV1 0 1 Timer output level control in default mode Disable output Enable output TOEN1 0 1 Timer output control Other than above 7 6 5 4 3 2 1 0 Cautions 1 When TMHE1 1 setting the other bits of the TMHMD1 register is prohibited 2 In the PWM output mode be sure to set 8 bit timer H compare r...

Page 134: ... and the output latch of P42 to 0 PM4 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets this register to FFH Figure 8 5 Format of Port Mode Register 4 PM4 Address FF24H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM4 1 1 PM45 PM44 PM43 PM42 PM41 PM40 PM4n P4n pin I O mode selection n 0 to 5 0 Output mode output buffer on 1 Input mode output buffer off ...

Page 135: ...tput from TOH1 1 Usage Generates the INTTMH1 signal repeatedly at the same interval 1 Set each register Figure 8 6 Register Setting During Interval Timer Square Wave Output Operation i Setting timer H mode register 1 TMHMD1 0 0 1 0 1 0 1 0 0 0 1 0 1 TMMD10 TOLEV1 TOEN1 CKS11 CKS12 TMHE1 TMHMD1 CKS10 TMMD11 Timer output setting Timer output level inversion setting Interval timer mode setting Count ...

Page 136: ... 8 bit timer counter H1 clear 2 Level inversion match interrupt occurrence 8 bit timer counter H1 clear 3 1 1 The count operation is enabled by setting the TMHE1 bit to 1 The count clock starts counting no more than 1 clock after the operation is enabled 2 When the values of 8 bit timer counter H1 and the CMP01 register match the value of 8 bit timer counter H1 is cleared the TOH1 output level is ...

Page 137: ...e Output Operation 2 2 b Operation when CMP01 FFH 00H Count clock Count start 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 01H FEH Clear Clear FFH 00H FEH FFH 00H FFH Interval time c Operation when CMP01 00H Count clock Count start 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 00H 00H Interval time ...

Page 138: ... an arbitrary duty and arbitrary cycle can be set is output 1 Set each register Figure 8 8 Register Setting in PWM Output Mode i Setting timer H mode register 1 TMHMD1 0 0 1 0 1 0 1 1 0 0 1 1 TMMD10 TOLEV1 TOEN1 CKS11 CKS12 TMHE1 TMHMD1 CKS10 TMMD11 Timer output enabled Timer output level inversion setting PWM output mode selection Count clock fCNT selection Count operation stopped ii Setting CMP0...

Page 139: ...ter is N the setting value of the CMP11 register is M and the count clock frequency is fCNT the PWM pulse output cycle and duty are as follows PWM pulse output cycle N 1 fCNT Duty Active width Total width of PWM M 1 N 1 Cautions 1 In PWM output mode the setting value for the CMP11 register can be changed during timer count operation However three operation clocks signal selected using the CKS12 to...

Page 140: ...5H 01H 1 2 3 4 1 The count operation is enabled by setting the TMHE1 bit to 1 Start 8 bit timer counter H1 by masking one count clock to count up At this time TOH1 output remains inactive when TOLEV1 0 2 When the values of 8 bit timer counter H1 and the CMP01 register match the TOH1 output level is inverted the value of 8 bit timer counter H1 is cleared and the INTTMH1 signal is output 3 When the ...

Page 141: ...n CMP01 FFH CMP11 00H Count clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 00H 01H FFH 00H 01H 02H FFH 00H FFH 00H 01H 02H CMP11 FFH 00H c Operation when CMP01 FFH CMP11 FEH Count clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H CMP11 FFH FEH ...

Page 142: ... Manual U16898EJ3V0UD 142 Figure 8 9 Operation Timing in PWM Output Mode 3 4 d Operation when CMP01 01H CMP11 00H Count clock 8 bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 TOLEV1 0 01H 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP11 00H ...

Page 143: ... timer counter H1 is cleared the TOH1 output becomes active and the INTTMH1 signal is output 4 If the CMP11 register value is changed the value is latched and not transferred to the register When the values of 8 bit timer counter H1 and the CMP11 register before the change match the value is transferred to the CMP11 register and the CMP11 register value is changed 2 However three count clocks or m...

Page 144: ...llation Clock Operation During System Clock Operation 2 11 fRL 4 27 ms 2 13 fX 819 2 µs 2 12 fRL 8 53 ms 2 14 fX 1 64 ms 2 13 fRL 17 07 ms 2 15 fX 3 28 ms 2 14 fRL 34 13 ms 2 16 fX 6 55 ms 2 15 fRL 68 27 ms 2 17 fX 13 11 ms 2 16 fRL 136 53 ms 2 18 fX 26 21 ms 2 17 fRL 273 07 ms 2 19 fX 52 43 ms 2 18 fRL 546 13 ms 2 20 fX 104 86 ms Remarks 1 fRL Low speed internal oscillation clock oscillation freq...

Page 145: ...er cannot be stopped The watchdog timer can be stopped Note 2 Notes 1 As long as power is being supplied low speed internal oscillator cannot be stopped except in the reset period 2 The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock source of the watchdog timer 1 If the clock source is fX clock supply to the watchdog timer is stopped under the fo...

Page 146: ...f Watchdog Timer fRL 22 Clock input controller Output controller Internal reset signal WDCS2 Internal bus WDCS1 WDCS0 fX 24 WDCS3 WDCS4 0 1 1 Selector 16 bit counter or 213 fX to 220 fX 211 fRL to 218 fRL Watchdog timer enable register WDTE Watchdog timer mode register WDTM 3 2 Clear Option byte to set low speed internal oscillator cannot be stopped or low speed internal oscillator can be stopped ...

Page 147: ...t 67H R W WDCS4 Note 1 WDCS3 Note 1 Operation clock selection 0 0 Low speed internal oscillation clock fRL 0 1 System Clock fX 1 Watchdog timer operation stopped Overflow time setting WDCS2 Note 2 WDCS1 Note 2 WDCS0 Note 2 During low speed internal oscillation clock operation During system clock operation 0 0 0 2 11 fRL 4 27 ms 2 13 fX 819 2 µs 0 0 1 2 12 fRL 8 53 ms 2 14 fX 1 64 ms 0 1 0 2 13 fRL...

Page 148: ...flow time for the watchdog timer so that enough everflow time is secured Example 1 byte writing 200 µs MIN 1 block deletion 10 ms MIN Remarks 1 fRL Low speed internal oscillation clock oscillation frequency 2 fX System clock oscillation frequency 3 Don t care 4 Figures in parentheses apply to operation at fRL 480 kHz MAX fX 10 MHz 2 Watchdog timer enable register WDTE Writing ACH to WDTE clears th...

Page 149: ...ster WDTM by an 8 bit memory manipulation instruction Notes 1 2 Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 The operation clock low speed internal oscillation clock cannot be changed If any value is written to bits 3 and 4 WDCS3 WDCS4 of WDTM it is ignored 2 As soon as WDTM is written the...

Page 150: ...d Is Selected by Option Byte Reset WDT clock fRL Overflow time 546 13 ms MAX STOP WDT count continues HALT WDT count continues STOP instruction HALT instruction WDT clock is fixed to fRL Select overflow time settable only once WDT clock fRL Overflow time 4 27 ms to 546 13 ms MAX WDT count continues Interrupt Interrupt WDTE ACH Clear WDT counter ...

Page 151: ...clock fX Watchdog timer operation stopped Cycle Set using bits 2 to 0 WDCS2 to WDCS0 3 After the above procedures are executed writing ACH to WDTE clears the count to 0 enabling recounting Notes 1 As soon as WDTM is written the counter of the watchdog timer is cleared 2 Set bits 7 6 and 5 to 0 1 1 respectively Do not set the other values 3 At the first write if the watchdog timer is stopped by set...

Page 152: ...DT count continues STOP WDT count stops HALT WDT count stops STOP instruction HALT instruction Interrupt Interrupt WDTE ACH Clear WDT counter WDT operation stops WDCS4 1 WDT clock fX Overflow time 213 fX to 220 fX WDT count continues WDT clock fX Select overflow time settable only once WDT clock fRL WDT count stops WDTE ACH Clear WDT counter LSRSTOP 1 LSRSTOP 0 STOP WDT count stops HALT WDT count ...

Page 153: ...select register OSTS after operation stops in the case of crystal ceramic oscillation and then counting is started again using the operation clock before the operation was stopped At this time the counter is not cleared to 0 but holds its value Figure 9 6 Operation in STOP Mode WDT Operation Clock Clock to Peripheral Hardware 1 CPU clock Crystal ceramic oscillation clock Operation stopped Operatin...

Page 154: ...value Figure 9 7 Operation in STOP Mode WDT Operation Clock Low Speed Internal Oscillation Clock 1 CPU clock Crystal ceramic oscillation clock Operating Oscillation stabilization time Normal operation Oscillation stabilization time set by OSTS register Watchdog timer Operation stopped Operating fRL fCPU CPU operation Normal operation STOP Oscillation stopped Operation stoppedNote 2 CPU clock High ...

Page 155: ...gardless of whether the operation clock of the watchdog timer is the system clock fX or low speed internal oscillation clock fRL After HALT mode is released counting is started again using the operation clock before the operation was stopped At this time the counter is not cleared to 0 but holds its value Figure 9 8 Operation in HALT Mode Watchdog timer Operating fX or fRL fCPU CPU operation Norma...

Page 156: ...ersion is carried out repeatedly for one channel selected from analog inputs ANI0 to ANI3 Each time an A D conversion operation ends an interrupt request INTAD is generated Figure 10 1 shows the timing of sampling and A D conversion and Table 10 1 shows the sampling time and A D conversion time Figure 10 1 Timing of A D Converter Sampling and A D Conversion ADCS Conversion time Conversion time Sam...

Page 157: ... 3 below are satisfied Example When AVREF 2 7 V fXP 8 MHz The sampling time is 11 0 µs or more and the A D conversion time is 14 0 µs or more and 100 µs or less Set FR2 FR1 and FR0 0 1 1 or 1 1 1 2 Set the sampling time as follows AVREF 4 5 V 1 0 µs or more AVREF 4 0 V 2 4 µs or more AVREF 2 85 V 3 0 µs or more AVREF 2 7 V 11 0 µs or more 3 Set the A D conversion time as follows AVREF 4 5 V 3 0 µs...

Page 158: ...ion of A D Converter The A D converter consists of the following hardware 1 ANI0 to ANI3 pins These are the analog input pins of the 4 channel A D converter They input analog signals to be converted into digital signals Pins other than the one selected as the analog input pin by the analog input channel specification register ADS can be used as input port pins 2 Sample hold circuit The sample hold...

Page 159: ...ime A D conversion is completed and the ADCRH register holds the result of A D conversion in its higher 8 bits 8 Controller When A D conversion has been completed INTAD is generated 9 AVREF pin This pin inputs an analog power reference voltage to the A D converter When the A D converter is not used connect this pin to VDD The signal input to ANI0 to ANI3 is converted into a digital signal based on...

Page 160: ...Converter The A D converter uses the following six registers A D converter mode register ADM Analog input channel specification register ADS 10 bit A D conversion result register ADCR 8 bit A D conversion result register ADCRH Port mode control register 2 PMC2 Port mode register 2 PM2 ...

Page 161: ...1 0 0 AVREF 4 0 V 24 fXP 72 fXP 3 0 µs 9 0 µs 2 4 µs 7 2 µs 1 1 0 96 fXP 144 fXP 12 0 µs 18 0 µs 9 6 µs 14 4 µs 1 0 1 48 fXP 96 fXP 6 0 µs 12 0 µs 4 8 µs 9 6 µs 0 1 0 48 fXP 72 fXP 6 0 µs 9 0 µs 4 8 µs 7 2 µs 0 0 1 AVREF 2 85 V 24 fXP 48 fXP 3 0 µs 6 0 µs Setting prohibited 2 4 µs Setting prohibited 4 8 µs 1 1 1 176 fXP 224 fXP 22 0 µs 28 0 µs 17 6 µs 22 4 µs 0 1 1 AVREF 2 7 V 88 fXP 112 fXP 11 0 ...

Page 162: ...tion stabilization Therefore when ADCS is set to 1 after 1 µs or more has elapsed from the time ADCE is set to 1 the conversion result at that time has priority over the first conversion result If the ADCS is set to 1 without waiting for 1 µs or longer ignore the first conversion data Table 10 2 Settings of ADCS and ADCE ADCS ADCE A D Conversion Operation 0 0 Stop status DC power consumption path ...

Page 163: ...W Symbol Caution Be sure to clear bits 2 to 7 of ADS to 0 3 10 bit A D conversion result register ADCR This register is a 16 bit register that stores the A D conversion result The higher six bits are fixed to 0 Each time A D conversion ends the conversion result is loaded from the successive approximation register and is stored in ADCR in order starting from bit 1 of FF19H FF19H indicates the high...

Page 164: ...t PMC20 to PMC23 and PM20 to PM23 to 1 At this time the output latches of P20 to P23 may be 0 or 1 PMC2 and PM2 are set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears PMC2 to 00H and sets PM2 to FFH Figure 10 8 Format of Port Mode Control Register 2 PMC2 Address FF84H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20 PMC2n Operation...

Page 165: ...9 Next bit 8 of SAR is automatically set to 1 and the operation proceeds to the next comparison The D A converter voltage tap is selected according to the preset value of bit 9 as described below Bit 9 1 3 4 AVREF Bit 9 0 1 4 AVREF The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows Analog input voltage Voltage tap Bit 8 1 Analog input voltage Voltage t...

Page 166: ...onversion operations are performed continuously until bit 7 ADCS of the A D converter mode register ADM is reset 0 by software If a write operation is performed to ADM or the analog input channel specification register ADS during an A D conversion operation the conversion operation is initialized and if the ADCS bit is set 1 conversion starts again from the beginning Reset signal generation makes ...

Page 167: ...Function which returns integer part of value in parentheses VAIN Analog input voltage AVREF AVREF pin voltage ADCR 10 bit A D conversion result register ADCR value Figure 10 11 shows the relationship between the analog input voltage and the A D conversion result Figure 10 11 Relationship Between Analog Input Voltage and A D Conversion Result 1023 1022 1021 3 2 1 0 03FFH 03FEH 03FDH 0003H 0002H 000...

Page 168: ...d in the A D conversion result register ADCR ADCRH and an interrupt request signal INTAD is generated Once the A D conversion has started and when one A D conversion has been completed the next A D conversion operation is immediately started The A D conversion operations are repeated until new data is written to ADS If ADM or ADS is written during A D conversion the A D conversion operation under ...

Page 169: ... D conversion data to the A D conversion result register ADCR ADCRH Change the channel 7 Change the channel using bits 1 and 0 ADS1 ADS0 of ADS 8 An interrupt request signal INTAD is generated 9 Transfer the A D conversion data to the A D conversion result register ADCR ADCRH Complete A D conversion 10 Clear ADCS to 0 11 Clear ADCE to 0 Cautions 1 Make sure the period of 1 to 4 is 1 µs or more 2 I...

Page 170: ...verall error in the characteristics table 3 Quantization error When analog values are converted to digital values a 1 2LSB error naturally occurs In an A D converter an analog input voltage in a range of 1 2LSB is converted to the same digital code so a quantization error cannot be avoided Note that the quantization error is not included in the overall error zero scale error full scale error integ...

Page 171: ... and the ideal value Figure 10 15 Zero Scale Error Figure 10 16 Full Scale Error 111 011 010 001 Zero scale error Ideal line 000 0 1 2 3 AVREF Digital output Lower 3 bits Analog input LSB 111 110 101 000 0 AVREF 3 Full scale error Ideal line Analog input LSB Digital output Lower 3 bits AVREF 2 AVREF 1 AVREF Figure 10 17 Integral Linearity Error Figure 10 18 Differential Linearity Error 0 AVREF Dig...

Page 172: ...o an analog input channel the converted value of that channel becomes undefined In addition the converted values of the other channels may also be affected 3 Conflicting operations 1 Conflict between A D conversion result register ADCR ADCRH write and ADCR ADCRH read by instruction upon the end of conversion ADCR ADCRH read has priority After the read operation the new conversion result is written...

Page 173: ...µ 5 ANI0 P20 to ANI3 P23 1 The analog input pins ANI0 to ANI3 are also used as input port pins P20 to P23 When A D conversion is performed with any of ANI0 to ANI3 selected do not access P20 to P23 while conversion is in progress otherwise the conversion resolution may be degraded 2 If a digital pulse is applied to the pins adjacent to the pins currently used for A D conversion the expected value ...

Page 174: ...ersion ADCR ADCRH ADIF ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADS rewrite start of ANIm conversion ADIF is set but ANIm conversion has not ended Remarks 1 n 0 to 3 2 m 0 to 3 8 Conversion results just after A D conversion start The first A D conversion value immediately after A D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 µs after the ADCE bit was ...

Page 175: ... Table 10 3 Resistance and Capacitance Values Reference Values of Equivalent Circuit AVREF ROUT RIN COUT CIN 4 5 V AVREF 5 5 V 1 kΩ 3 kΩ 8 pF 15 pF 2 7 V AVREF 4 5 V 1 kΩ 60 kΩ 8 pF 15 pF Remarks 1 The resistance and capacitance values shown in Table 10 3 are not guaranteed values 2 n 0 to 3 3 ROUT Allowable signal source impedance RIN Analog input equivalent resistance CIN Analog input equivalent...

Page 176: ...13 to 20 bits More than 11 bits can be identified for synchronous break field reception SBF reception flag provided Cautions 1 The TXD6 output inversion function inverts only the transmission side and not the reception side To use this function the reception side must be ready for reception of inverted data 2 If clock supply to serial interface UART6 is not stopped e g in the HALT mode normal oper...

Page 177: ...t and corrects the baud rate error Therefore communication is possible when the baud rate error in the slave is 15 or less Figures 11 1 and 11 2 outline the transmission and reception operations of LIN Figure 11 1 LIN Transmission Operation LIN bus Wakeup signal frame 8 bitsNote 1 55H transmission Data transmission Data transmission Data transmission Data transmission 13 bitNote 2 SBF transmission...

Page 178: ...unter 00 during SBF reception completion interrupt processing and measure the bit width pulse width of the sync field refer to 6 4 3 Pulse width measurement operations Detection of errors OVE6 PE6 and FE6 is suppressed and error detection processing of UART communication and data transfer of the shift register and RXB6 is not performed The shift register holds the reset value FFH 4 Calculate the b...

Page 179: ...xD6 P44 Selector Selector Selector Remark ISC0 ISC1 Bits 0 and 1 of the input switch control register ISC see Figure 11 11 The peripheral functions used in the LIN communication operation are shown below Peripheral functions used External interrupt INTP0 wakeup signal detection Use Detects the wakeup signal edges and detects start of communication 16 bit timer event counter 00 TI000 baud rate erro...

Page 180: ...er 6 RXS6 Transmit buffer register 6 TXB6 Transmit shift register 6 TXS6 Control registers Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface transmission status register 6 ASIF6 Clock selection register 6 CKSR6 Baud rate generator control register 6 BRGC6 Asynchronous serial interface co...

Page 181: ...e buffer register 6 RXB6 RXD6 P44 TI000 INTP0Note INTSR6 Baud rate generator Filter INTSRE6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface transmission status register 6 ASIF6 Transmission control Registers fXP fXP 2 fXP 22 fXP 23 fXP 24 fXP 25 fXP 26 fXP 27 fXP 28 fXP 29 fXP 210 fXP ...

Page 182: ...a Transmission is started when data is written to TXB6 If the data length is set to 7 bits In LSB fast transmission data is transferred to bits 0 to 6 of TXB6 and the MSB of TXB6 is not transmitted In MSB fast transmission data is transferred to bits 7 to 1 of TXB6 and the LSB of TXB6 is not transmitted This register can be read or written by an 8 bit memory manipulation instruction Reset signal g...

Page 183: ...ER6 and bit 6 TXE6 of ASIM6 1 or bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Figure 11 5 Format of Asynchronous Serial Interface Operation Mode Register 6 ASIM6 1 2 Address FF90H After reset 01H R W Symbol 7 6 5 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 Enabling disabling operation of internal operation clock 0 Note 1 Disable operation of the internal operation clock fixes the clo...

Page 184: ...does not occur 1 INTSR6 occurs in case of error at this time INTSRE6 does not occur Note If reception as 0 parity is selected the parity is not judged Therefore bit 2 PE6 of asynchronous serial interface reception error status register 6 ASIS6 is not set and the error interrupt does not occur Cautions 1 At startup set POWER6 to 1 and then set TXE6 to 1 To stop the operation clear TXE6 to 0 and the...

Page 185: ...ASIS6 register is read 1 If the parity of transmit data does not match the parity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 0 and RXE6 0 or if ASIS6 register is read 1 If the stop bit is not detected on completion of reception OVE6 Status flag indicating overrun error 0 If POWER6 0 and RXE6 0 or if ASIS6 register is read 1 If receive data is set to the RXB...

Page 186: ...R6 0 or TXE6 0 or if data is transferred to transmit shift register 6 TXS6 1 If data is written to transmit buffer register 6 TXB6 if data exists in TXB6 TXSF6 Transmit shift register data flag 0 If POWER6 0 or TXE6 0 or if the next data is not transferred from transmit buffer register 6 TXB6 after completion of transfer 1 If data is transferred from transmit buffer register 6 TXB6 if data transmi...

Page 187: ...ck Selection Register 6 CKSR6 Address FF96H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS63 TPS62 TPS61 TPS60 Base clock fXCLK6 selection 0 0 0 0 fXP 10 MHz 0 0 0 1 fXP 2 5 MHz 0 0 1 0 fXP 2 2 2 5 MHz 0 0 1 1 fXP 2 3 1 25 MHz 0 1 0 0 fXP 2 4 625 kHz 0 1 0 1 fXP 2 5 312 5 kHz 0 1 1 0 fXP 2 6 156 25 kHz 0 1 1 1 fXP 2 7 78 13 kHz 1 0 0 0 fXP 2 8 39 06 kHz 1 0 0 ...

Page 188: ... FF97H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8 bit counter 0 0 0 0 0 Setting prohibited 0 0 0 0 1 0 0 0 8 fXCLK6 8 0 0 0 0 1 0 0 1 9 fXCLK6 9 0 0 0 0 1 0 1 0 10 fXCLK6 10 1 1 1 1 1 1 0 0 252 fXCLK6 252 1 1 1 1 1 1 0 1 253 fXCLK6 253 1 1 1 1 1 1 1 0 254 fXCLK6 254 1...

Page 189: ...1 However if the SBRT6 1 and SBTT 1 are set in the refresh operation during the SBF reception SBRF6 1 or SBF transmission between the SBTT6 setting 1 and the INTST6 occurrence it triggers the SBF reception and SBF transmission again so do not set Figure 11 10 Format of Asynchronous Serial Interface Control Register 6 ASICL6 1 2 Address FF98H After reset 16H R W Note Symbol 7 6 5 4 3 2 1 0 ASICL6 S...

Page 190: ...ception error return the mode to the SBF reception mode again and hold 1 the status of the SBRF6 flag 2 Before setting the SBRT6 bit to 1 make sure that bit 7 POWER6 and bit 5 RXE6 of ASIM6 1 Moreover after setting the SBRT6 bit to 1 do not clear the SBRT6 bit to 0 before the SBF reception ends an interrupt request signal is generated 3 The read value of the SBRT6 bit is always 0 SBRT6 is automati...

Page 191: ...0 0 0 0 ISC1 ISC0 ISC1 TI000 input source selection 0 TI000 P30 1 RxD6 P44 ISC0 INTP0 input source selection 0 INTP0 P30 1 RxD6 P44 8 Port mode register 4 PM4 This register sets port 4 input output in 1 bit units When using the P43 TxD6 INTP1 pin for serial interface data output clear PM43 to 0 and set the output latch of P43 to 1 When using the P44 RxD6 pin for serial interface data input set PM4...

Page 192: ...peration of internal operation clock 0 Note 1 Disable operation of the internal operation clock fix the clock to low level and asynchronously reset the internal circuit Note 2 TXE6 Enabling disabling transmission 0 Disable transmission operation synchronously reset the transmission circuit RXE6 Enabling disabling reception 0 Disable reception synchronously reset the reception circuit Notes 1 The o...

Page 193: ...6 BRGC6 Asynchronous serial interface control register 6 ASICL6 Input switch control register ISC Port mode register 4 PM4 Port register 4 P4 The basic procedure of setting an operation in the UART mode is as follows 1 Set the CKSR6 register see Figure 11 8 2 Set the BRGC6 register see Figure 11 9 3 Set bits 0 to 4 ISRM6 SL6 CL6 PS60 PS61 of the ASIM6 register see Figure 11 5 4 Set bits 0 and 1 TX...

Page 194: ...M43 P43 PM44 P44 UART6 Operation TxD6 INTP1 P43 RxD6 P44 0 0 0 Note Note Note Note Stop P43 P44 0 1 Note Note 1 Reception P43 RxD6 1 0 0 1 Note Note Transmission TxD6 P44 1 1 1 0 1 1 Transmission reception TxD6 RxD6 Note Can be set as port function Remark don t care POWER6 Bit 7 of asynchronous serial interface operation mode register 6 ASIM6 TXE6 Bit 6 of ASIM6 RXE6 Bit 5 of ASIM6 PM4 Port mode r...

Page 195: ...ssion reception Start bit Parity bit D7 D6 D5 D4 D3 1 data frame Character bits D2 D1 D0 Stop bit One data frame consists of the following bits Start bit 1 bit Character bits 7 or 8 bits Parity bit Even parity odd parity 0 parity or no parity Stop bit 1 or 2 bits The character bit length parity and stop bit length in one data frame are specified by asynchronous serial interface operation mode regi...

Page 196: ...p bit 1 bit Communication data 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3 Data length 8 bits MSB first Parity Even parity Stop bit 1 bit Communication data 55H TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4 Data length 7 bits LSB first Parity Odd parity Stop bit 2 bits Communication data 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop St...

Page 197: ...he number of bits that are 1 in the receive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the parity bit is controlled so that the number of bits that are 1 is odd If transmit data has an odd number of bits that are 1 0 If transmit data has an even number of bits that are 1 1 Reception The number of...

Page 198: ...shift register 6 TXS6 After that the data is sequentially output from TXS6 to the TXD6 pin When transmission is completed the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request INTST6 is generated Transmission is stopped until the data to be transmitted next is written to TXB6 Figure 11 15 shows the timing of the transmission completion interrupt request...

Page 199: ...ce is incorporated in a LIN the continuous transmission function cannot be used Make sure that asynchronous serial interface transmission status register 6 ASIF6 is 00H before writing transmit data to transmit buffer register 6 TXB6 TXBF6 Writing to TXB6 Register 0 Writing enabled 1 Writing disabled Caution To transmit data continuously write the first transmit data first byte to the TXB6 register...

Page 200: ...sfer executed necessary number of times Yes Read ASIF6 TXBF6 0 No No Yes Transmission completion interrupt occurred Read ASIF6 TXSF6 0 No No No Yes Yes Yes Yes Completion of transmission processing Transfer executed necessary number of times Remark TXB6 Transmit buffer register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 transmit buffer data flag TXSF6...

Page 201: ...a 1 Data 2 Data 3 Data 2 Data 1 Data 3 FF FF Parity Stop Data 2 Parity Stop TXB6 TXS6 TXBF6 TXSF6 Start Start Note Note When ASIF6 is read there is a period in which TXBF6 and TXSF6 1 1 Therefore judge whether writing is enabled using only the TXBF6 bit Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous seri...

Page 202: ...B6 TXS6 TXBF6 TXSF6 POWER6 or TXE6 Start Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 TXSF6 Bit 0 of ASIF6 POWER6 Bit 7 of asynchronous serial interface operation mode register ASIM6 TXE6 Bit 6 of asynchronous serial interface operati...

Page 203: ...top bit has been received the reception completion interrupt INTSR6 is generated and the data of RXS6 is written to receive buffer register 6 RXB6 If an overrun error OVE6 occurs however the receive data is not written to RXB6 Even if a parity error PE6 occurs while reception is in progress reception continues to the reception position of the stop bit and an error interrupt INTSR6 INTSRE6 is gener...

Page 204: ...tion Error Cause Parity error The parity specified for transmission does not match the parity of the receive data Framing error Stop bit is not detected Overrun error Reception of the next data is completed before data is read from receive buffer register 6 RXB6 The error interrupt can be separated into reception completion interrupt INTSR6 and error interrupt INTSRE6 by clearing bit 0 ISRM6 of as...

Page 205: ...sion Operation When bit 7 POWER6 of asynchronous serial interface mode register 6 ASIM6 is set to 1 the TxD6 pin outputs high level Next when bit 6 TXE6 of ASIM6 is set to 1 the transmission enabled status is entered and SBF transmission is started by setting bit 5 SBTT6 of asynchronous serial interface control register 6 ASICL6 to 1 Thereafter a low level of bits 13 to 20 set by bits 4 to 2 SBL62...

Page 206: ...st INTSR6 is generated as normal processing At this time the SBRF6 and SBRT6 bits are automatically cleared and SBF reception ends Detection of errors such as OVE6 PE6 and FE6 bits 0 to 2 of asynchronous serial interface reception error status register 6 ASIS6 is suppressed and error detection processing of UART communication is not performed In addition data transfer between receive shift registe...

Page 207: ...n POWER6 0 Transmission counter This counter stops operation cleared to 0 when bit 7 POWER6 or bit 6 TXE6 of asynchronous serial interface operation mode register 6 ASIM6 is 0 It starts counting when POWER6 1 and TXE6 1 The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 TXB6 If data are continuously transmitted the counter is cleared to 0 again whe...

Page 208: ...ud rate generator BRGC6 MDL67 to MDL60 1 2 POWER6 TXE6 or RXE6 CKSR6 TPS63 to TPS60 fXP fXP 2 fXP 22 fXP 23 fXP 24 fXP 25 fXP 26 fXP 27 fXP 28 fXP 29 fXP 210 fXP 211 fXCLK6 Remark POWER6 Bit 7 of asynchronous serial interface operation mode register 6 ASIM6 TXE6 Bit 6 of ASIM6 RXE6 Bit 5 of ASIM6 CKSR6 Clock selection register 6 BRGC6 Baud rate generator control register 6 ...

Page 209: ...60 bits of CKSR6 register k Value set by MDL67 to MDL60 bits of BRGC6 register k 8 9 10 255 b Error of baud rate The baud rate error can be calculated by the following expression Error 1 100 Cautions 1 Keep the baud rate error during transmission to within the permissible error range at the reception destination 2 Make sure that the baud rate error during reception satisfies the range shown in 4 P...

Page 210: ... 1H 109 9610 0 11 10400 1H 240 10417 0 16 1H 201 10423 0 22 1H 101 10475 0 28 19200 1H 130 19231 0 16 1H 109 19220 0 11 0H 109 19220 0 11 31250 0H 160 31250 0 00 0H 134 31268 0 06 0H 67 31268 0 06 38400 0H 130 38462 0 16 0H 109 38440 0 11 0H 55 38090 0 80 76800 0H 65 76923 0 16 0H 55 76182 0 80 0H 27 77693 1 03 115200 0H 43 116279 0 94 0H 36 116389 1 03 0H 18 116389 1 03 153600 0H 33 151515 1 36 0...

Page 211: ...it Bit 0 Bit 1 Bit 7 Parity bit Minimum permissible data frame length Maximum permissible data frame length Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 11 25 the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 BRGC6 after the start bit has been de...

Page 212: ...aud rate error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 11 5 Maximum Minimum Permissible Baud Rate Error Division Ratio k Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 8 3 53 3 61 20 4 26 4 31 50 4 56 4 58 100 4 66 4 67 255 4 72 4 73 Remarks 1 The permissible error of recepti...

Page 213: ...because the timing is initialized on the reception side when the start bit is detected Figure 11 26 Data Frame Length During Continuous Transmission Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame FL FL FL FL FL FL FLstp Start bit of second byte Start bit Bit 0 Where the 1 bit data length is FL the stop bit length is FLstp and base clock frequency is fXCLK6 the following expression...

Page 214: ...nterrupt requests are generated at the same time processing takes place in the priority order of the vector interrupt servicing For details on the priority order see Table 12 1 There are nine internal sources and four external sources of maskable interrupts Reset The CPU and SFR are returned to their initial states by the reset signal The causes for reset signal occurrences are shown in Table 12 1...

Page 215: ...ter is specified 0010H 7 INTAD End of A D conversion Internal 0012H A 8 INTP2 0016H 9 INTP3 Pin input edge detection External 0018H B 10 INTTM80 Match between TM80 and CR80 001AH 11 INTSRE6 UART6 reception error occurrence 001CH 12 INTSR6 End of UART6 reception 001EH Maskable 13 INTST6 End of UART6 transmission Internal 0020H A RESET Reset input POC Power on clear LVI Low voltage detection Note 4 ...

Page 216: ...K IF IE Internal bus Interrupt request Vector table address generator Standby release signal B External maskable interrupt Internal bus External interrupt mode register INTM0 INTM1 MK IF IE Vector table address generator Standby release signal Edge detector Interrupt request IF Interrupt request flag IE Interrupt enable flag MK Interrupt mask flag ...

Page 217: ...1 Program status word PSW Table 12 2 lists interrupt requests the corresponding interrupt request flags and interrupt mask flags Table 12 2 Interrupt Request Signals and Corresponding Flags Interrupt Request Signal Interrupt Request Flag Interrupt Mask Flag INTLVI INTP0 INTP1 INTTMH1 INTTM000 INTTM010 INTAD INTP2 INTP3 INTTM80 INTSRE6 INTSR6 INTST6 LVIIF PIF0 PIF1 TMIFH1 TMIF000 TMIF010 ADIF PIF2 ...

Page 218: ...rmat of Interrupt Request Flag Registers IF0 IF1 Address FFE0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0 ADIF TMIF010 TMIF000 TMIFH1 PIF1 PIF0 LVIIF 0 Address FFE1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1 0 STIF6 SRIF6 SREIF6 TMIF80 PIF3 PIF2 0 IF Interrupt request flag 0 No interrupt request signal has been issued 1 An interrupt request signal has been issued an interrupt request stat...

Page 219: ...s FFE4H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0 ADMK TMMK010 TMMK000 TMMKH1 PMK1 PMK0 LVIMK 1 Address FFE5H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK1 1 STMK6 SRMK6 SREMK6 TMMK80 PMK3 PMK2 1 MK Interrupt servicing control 0 Enables interrupt servicing 1 Disables interrupt servicing Caution Because P30 P31 P41 and P43 have an alternate function as external interrupt inputs when the outpu...

Page 220: ...e selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES11 ES10 INTP1 valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges ES01 ES00 INTP0 valid edge selection 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges Cautions 1 Be sure to clear bits 0 and 1 to ...

Page 221: ...isable interrupts To enable interrupts clear PIF3 to 0 then clear PMK3 to 0 5 Program status word PSW The program status word is used to hold the instruction execution result and the current status of the interrupt requests The IE flag used to enable and disable maskable interrupts is mapped to PSW PSW can be read and write accessed in 8 bit units as well as using bit manipulation instructions and...

Page 222: ... of Maskable Interrupt Request to Servicing Minimum Time Maximum Time Note 9 clocks 19 clocks Note The wait time is maximum when an interrupt request is generated immediately before BT and BF instructions Remark 1 clock fCPU CPU clock When two or more maskable interrupt requests are generated at the same time they are acknowledged starting from the interrupt request assigned the highest priority A...

Page 223: ...ming Example of MOV A r Clock CPU Interrupt MOV A r Saving PSW and PC jump to interrupt servicing 8 clocks Interrupt servicing program If an interrupt request flag IF is set before an instruction clock n n 4 to 10 under execution becomes n 1 the interrupt is acknowledged after the instruction under execution is complete Figure 12 8 shows an example of the interrupt request acknowledgment timing fo...

Page 224: ...le of the interrupt request acknowledgment timing for an interrupt request flag that is set at the second clock of NOP 2 clock instruction In this case the MOV A r instruction after the NOP instruction is executed and then the interrupt acknowledgment processing is performed Caution Interrupt requests will be held pending while the interrupt request flag registers IF0 IF1 or interrupt mask flag re...

Page 225: ...eased and the interrupt request acknowledgement enable state is set Caution Multiple interrupts can be acknowledged even for low priority interrupts Example 2 Multiple interrupts are not generated because interrupts are not enabled INTyy EI Main processing RETI INTyy servicing INTxx servicing IE 0 INTxx RETI INTyy is held pending IE 0 Because interrupts are not enabled in interrupt INTxx servicing...

Page 226: ...rrupt is given priority since the INTP0 interrupt was first masked Afterwards once the interrupt mask for INTP0 is released INTP0 processing through multiple interrupts is performed IE 0 Interrupt request acknowledgment disabled 12 4 3 Interrupt request pending Some instructions may keep pending the acknowledgment of an instruction request until the completion of the execution of the next instruct...

Page 227: ... LSRSTOP setting is valid only when Can be stopped by software is set for the low speed internal oscillator by the option byte Remark LSRSTOP Bit 0 of the low speed internal oscillation mode register LSRCM The standby function is designed to reduce the operating current of the system The following two modes are available 1 HALT mode HALT instruction execution sets the HALT mode In the HALT mode th...

Page 228: ...7 µs MAX In either of these two modes all the contents of registers flags and data memory just before the standby mode is set are held The I O port output latches and output buffer statuses are also held Cautions 1 When shifting to the STOP mode be sure to stop the peripheral hardware operation before executing STOP instruction except the peripheral hardware that operates on the low speed internal...

Page 229: ...BYTE OSTS is set by using the 8 bit memory manipulation instruction Figure 13 1 Format of Oscillation Stabilization Time Select Register OSTS Address FFF4H After reset Undefined R W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 0 OSTS1 OSTS0 OSTS1 OSTS0 Selection of oscillation stabilization time 0 0 2 10 fX 102 4 µs 0 1 2 12 fX 409 6 µs 1 0 2 15 fX 3 27 ms 1 1 2 17 fX 13 1 ms Cautions 1 To set and then r...

Page 230: ...ion Continues When Low Speed Internal Oscillation Stops System clock Clock supply to CPU is stopped CPU Operation stops Port latch Holds status before HALT mode was set 16 bit timer event counter 00 Operable 8 bit timer 80 Operable Sets count clock to fXP to fXP 2 12 Operable 8 bit timer H1 Sets count clock to fRL 2 7 Operable Operable Operation stops System clock selected as operating clock Setti...

Page 231: ...ent is disabled the next address instruction is executed Figure 13 2 HALT Mode Release by Interrupt Request Generation HALT instruction Wait Wait Operating mode HALT mode Operating mode Oscillation System clock oscillation Status of CPU Standby release signal Interrupt request Remarks 1 The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledge...

Page 232: ...n is stopped 277 µs MIN 544 µs TYP 1 075 ms MAX because the option byte is referenced 2 When CPU clock is crystal ceramic oscillation clock HALT instruction Reset signal System clock oscillation Operation mode HALT mode Reset period Operation stopsNote Oscillation stabilization waits Oscillates Oscillation stops Oscillates CPU status Oscillation stabilization time 210 fX to 217 fX Operation mode N...

Page 233: ...l Oscillator Can Be Stopped Note Setting of HALT Mode Item Low Speed Internal Oscillator Cannot Be Stopped Note When Low Speed Internal Oscillation Continues When Low Speed Internal Oscillation Stops System clock Oscillation stops CPU Operation stops Port latch Holds status before STOP mode is set 16 bit timer event counter 00 Operation stops 8 bit timer 80 Operation stops Sets count clock to fXP ...

Page 234: ...de is released STOP mode High speed internal oscillation clock or external clock input Operation stopsNote 2 If crystal ceramic oscillation clock is selected as system clock to be supplied System clock oscillation CPU clock STOP mode is released STOP mode HALT status oscillation stabilization time set by OSTS Crystal ceramic oscillation clock Operation stopsNote Note The operation stop time is 17 ...

Page 235: ...igh speed internal oscillation clock or external input clock Operation mode Operation mode Oscillation STOP instruction STOP mode Standby release signal System clock oscillation CPU status Oscillation Oscillation stops Operation stopsNote Interrupt request 2 If CPU clock is crystal ceramic oscillation clock Waiting for stabilization of oscillation Oscillation stabilization time set by OSTS HALT mo...

Page 236: ...µs MIN 544 µs TYP 1 075 ms MAX because the option byte is referenced 2 If CPU clock is crystal ceramic oscillation clock STOP instruction Reset signal System clock oscillation Operation mode STOP mode Reset period Operation stopsNote Operation mode Oscillation Oscillation stops Oscillation CPU status Oscillation stabilization time 210 fX to 217 fX Oscillation stabilization waits Note Operation is ...

Page 237: ...after referencing the option byte after the option byte is referenced and the clock oscillation stabilization time elapses if crystal ceramic oscillation is selected A reset generated by the watchdog timer source is automatically released after the reset and the CPU starts program execution after referencing the option byte after the option byte is referenced and the clock oscillation stabilizatio...

Page 238: ...egister RESF Internal bus Reset signal of WDT Reset signal of POC Reset signal of LVI Internal reset signal Reset signal to LVIM LVIS register Clear Set Clear Set Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit Remarks 1 LVIM Low voltage detect register 2 LVIS Low voltage detection level select register ...

Page 239: ...If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the reset signal to the CPU 2 With crystal ceramic oscillation clock Hi Z RESET Port pin P130 Note 2 Port pin except P130 Delay Normal operation in progress Reset period oscillation stops Oscillation stabilization time 210 fX to 217 fX Normal operation reset processing CPU clock Internal...

Page 240: ...l If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the reset signal to the CPU 2 With crystal ceramic oscillation clock Hi Z Port pin P130 Note 2 Port pin except P130 Normal operation in progress Reset period oscillation stops Oscillation stabilization time 210 fX to 217 fX Normal operation reset processing CPU clock Internal reset sig...

Page 241: ...75 ms MAX 2 Set high level output using software Remark When reset is effected P130 outputs a low level If P130 is set to output a high level before reset is effected the output signal of P130 can be dummy output as the reset signal to the CPU 2 With crystal ceramic oscillation clock Hi Z RESET Port pin except P130 Port pin P130 Note 2 Delay Normal operation in progress CPU clock Normal operation ...

Page 242: ... PU2 PU3 PU4 PU12 00H Processor clock control register PCC 02H Preprocessor clock control register PPCC 02H Low speed internal oscillation mode register LSRCM 00H Oscillation stabilization time select register OSTS Undefined Timer counter 00 TM00 0000H Capture compare registers 000 010 CR000 CR010 0000H Mode control register 00 TMC00 00H Prescaler mode register 00 PRM00 00H Capture compare control...

Page 243: ...w voltage detection register LVIM 00H Note Low voltage detector Low voltage detection level select register LVIS 00H Note Request flag registers IF0 IF1 00H Mask flag registers MK0 MK1 FFH Interrupt External interrupt mode registers INTM0 INTM1 00H Flash protect command register PFCMD Undefined Flash status register PFS 00H Flash programming mode control register FLPMC Undefined Flash programming ...

Page 244: ...1 0 RESF 0 0 0 WDTRF 0 0 0 LVIRF WDTRF Internal reset request by watchdog timer WDT 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated LVIRF Internal reset request by low voltage detector LVI 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated Note The value after reset varies depending on the reset sour...

Page 245: ...l is generated in the POC circuit the reset control flag register RESF is cleared to 00H 2 Because the detection voltage VPOC of the POC circuit is in a range of 2 1 V 0 1 V use a voltage in the range of 2 2 to 5 5 V Remark This product incorporates multiple hardware functions that generate an internal reset signal A flag that indicates the reset cause is located in the reset control flag register...

Page 246: ... source Internal reset signal VDD VDD 15 3 Operation of Power on Clear Circuit In the power on clear circuit the supply voltage VDD and detection voltage VPOC 2 1 V 0 1 V are compared and an internal reset signal is generated when VDD VPOC and an internal reset is released when VDD VPOC Figure 15 2 Timing of Internal Reset Signal Generation in Power on Clear Circuit Time Supply voltage VDD POC det...

Page 247: ...imer and then initialize the ports Figure 15 3 Example of Software Processing After Release of Reset 1 2 If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Check reset source Note 2 Initialization of ports Setting WDT Source fRL 2 1 MHz MAX 212 51 ms when the compare value is 25 Timer starts TMHE1 1 Note 1 Setting 8 bit timer H1 50 ms is measured Specify the divisi...

Page 248: ... Example of Software Processing After Release of Reset 2 2 Checking reset cause Yes No Check reset source Power on clear external reset generated Reset processing by watchdog timer Reset processing by low voltage detector No WDTRF of RESF register 1 LVIRF of RESF register 1 Yes ...

Page 249: ...re Operable in STOP mode When the low voltage detector is used to reset bit 0 LVIRF of the reset control flag register RESF is set to 1 if reset occurs For details of RESF refer to CHAPTER 14 RESET FUNCTION 16 2 Configuration of Low Voltage Detector The block diagram of the low voltage detector is shown in Figure 16 1 Figure 16 1 Block Diagram of Low Voltage Detector LVION Reference voltage source...

Page 250: ...tection operation mode selection 0 Generate interrupt signal when supply voltage VDD detection voltage VLVI 1 Generate internal reset signal when supply voltage VDD detection voltage VLVI LVIF Note 4 Low voltage detection flag 0 Supply voltage VDD detection voltage VLVI or when operation is disabled 1 Supply voltage VDD detection voltage VLVI Notes 1 For a reset by LVI the value of LVIM is not ini...

Page 251: ...ter LVIS Address FF51H After reset 00H Note R W Symbol 7 6 5 4 3 2 1 0 LVIS 0 0 0 0 LVIS3 LVIS2 LVIS1 LVIS0 LVIS3 LVIS2 LVIS1 LVIS0 Detection level 0 0 0 0 VLVI0 4 3 V 0 2 V 0 0 0 1 VLVI1 4 1 V 0 2 V 0 0 1 0 VLVI2 3 9 V 0 2 V 0 0 1 1 VLVI3 3 7 V 0 2 V 0 1 0 0 VLVI4 3 5 V 0 2 V 0 1 0 1 VLVI5 3 3 V 0 15 V 0 1 1 0 VLVI6 3 1 V 0 15 V 0 1 1 1 VLVI7 2 85 V 0 15 V 1 0 0 0 VLVI8 2 6 V 0 1 V 1 0 0 1 VLVI9 ...

Page 252: ...LVION of LVIM to 1 enables LVI operation 4 Use software to instigate a wait of at least 0 2 ms 5 Wait until supply voltage VDD detection voltage VLVI at bit 0 LVIF of LVIM is confirmed 6 Set bit 1 LVIMD of LVIM to 1 generates internal reset signal when supply voltage VDD detection voltage VLVI Figure 16 4 shows the timing of generating the internal reset signal of the low voltage detector Numbers ...

Page 253: ...K flag set by software LVION flag set by software LVIMD flag set by software Cleared by software Not cleared Not cleared Not cleared Not cleared Cleared by software Time Clear Clear Clear 4 0 2 ms or longer Notes 1 The LVIMK flag is set to 1 by reset input 2 The LVIF flag may be set 1 3 LVIRF is bit 0 of the reset control flag register RESF For details of RESF refer to CHAPTER 14 RESET FUNCTION Re...

Page 254: ...y voltage VDD detection voltage VLVI at bit 0 LVIF of LVIM is confirmed 6 Clear the interrupt request flag of LVI LVIIF to 0 7 Release the interrupt mask flag of LVI LVIMK 8 Execute the EI instruction when vector interrupts are used Figure 16 5 shows the timing of generating the interrupt signal of the low voltage detector Numbers 1 to 7 in this figure correspond to 1 to 7 above When stopping oper...

Page 255: ...VIIF flag Internal reset signal LVIMK flag set by software LVION flag set by software Time 6 Cleared by software 7 Cleared by software 4 0 2 ms or longer Note 2 Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 An interrupt request signal INTLVI may be generated and the LVIF and LVIIF flags may be set to 1 Remark 1 to 7 in Figure 16 5 above correspond to 1 to 7 in the description of ...

Page 256: ...n used as reset After releasing the reset signal wait for the supply voltage fluctuation period of each system by means of a software counter that uses a timer and then initialize the ports see Figure 16 6 2 When used as interrupt a Perform the processingNote for low voltage detection Check that supply voltage VDD detection voltage VLVI in the servicing routine of the LVI interrupt by using bit 0 ...

Page 257: ...ion flag Clear timaer counter and timer starts LVI reset Check reset source Note Initialization of ports Setting WDT Reset Initialization processing 1 Setting 8 bit timer H1 50 ms is measured Source fRL 2 1 MHz MAX 212 51 ms when the compare value is 25 Timer starts TMHE1 1 fXP High speed internal oscillation clock 8 4 MHz MAX 22 default value Clears WDT 50 ms has passed TMIFH1 1 Initialization pr...

Page 258: ...Example of Software Processing After Release of Reset 2 2 Checking reset source Yes No Yes No Check reset source Power on clear external reset generated Reset processing by watchdog timer Reset processing by low voltage detector WDTRF of RESF register 1 LVIRF of RESF register 1 ...

Page 259: ...g the option byte 1 Selection of system clock source High speed internal oscillation clock Crystal ceramic oscillation clock External clock input 2 Low speed internal oscillation clock oscillation Cannot be stopped Can be stopped by software 3 Control of RESET pin Used as RESET pin RESET pin is used as an input port pin P34 4 Oscillation stabilization time on power application or after reset relea...

Page 260: ...34 Caution Because the option byte is referenced after reset release if a low level is input to the RESET pin before the option byte is referenced then the reset state is not released Also when setting 0 to RMCE connect the pull up resistor OSCSEL1 OSCSEL0 Selection of system clock source 0 0 Crystal ceramic oscillation clock 0 1 External clock input 1 High speed internal oscillation clock Caution...

Page 261: ...speed internal oscillation mode register LSRCM Similarly clock supply is also stopped when a clock other than the low speed internal oscillation clock is selected as a count clock to WDT While the low speed internal oscillator is operating LSRSTOP 0 the clock can be supplied to the 8 bit timer H1 even in the STOP mode Remarks 1 fX 10 MHz 2 For the oscillation stabilization time of the resonator re...

Page 262: ...6 bytes Write unit 1 block at onboard offboard programming time 1 byte at self programming time Rewriting method Rewriting by communication with dedicated flash programmer on board off board programming Rewriting flash memory by user program self programming Supports rewriting of the flash memory at onboard offboard programming time through security functions Supports security functions in block u...

Page 263: ...0FFH Block 0 256 bytes Block 1 256 bytes Block 2 256 bytes Block 3 256 bytes Block 4 256 bytes Block 5 256 bytes Block 6 256 bytes Block 7 256 bytes Block 0 256 bytes Block 1 256 bytes Block 2 256 bytes Block 3 256 bytes Block 4 256 bytes Block 5 256 bytes Block 6 256 bytes Block 7 256 bytes Block 8 256 bytes Block 9 256 bytes Block 10 256 bytes Block 11 256 bytes Block 12 256 bytes Block 13 256 b...

Page 264: ...an unauthorized person Refer to 18 7 3 Security settings for details on the security function Table 18 1 Rewrite Method Rewrite Method Functional Outline Operation Mode On board programming Flash memory can be rewritten after the device is mounted on the target system by using a dedicated flash programmer Off board programming Flash memory can be rewritten before the device is mounted on the targe...

Page 265: ... of the flash memory can be rewritten after the 78K0S KA1 has been mounted on the target system The connectors that connect the dedicated flash programmer and the test pad must be mounted on the target system The test pad is required only when writing data with the crystal ceramic resonator mounted refer to Figure 18 6 for mounting of the test pad 2 Off board programming Data can be written to the...

Page 266: ...arget 3V Target PG FPL2 USB PG FPL2 Host machine Dedicated flash programmer Note DGCLK is a clock for communication while DGDATA is a transmit receive signal for communication data A host machine that controls the dedicated flash programmer is necessary When using the PG FP4 or FL PR4 data can be written with just the dedicated flash programmer after downloading the program from the host machine U...

Page 267: ...X1 pin and the SI RxD and SO TxD signals to the X2 signal therefore these signals need to be directly connected Figure 18 4 Wiring diagram with FlashPro4 78K0S KA1 CLK FLMD0 SO TxD RESET VDD GND FlashPro4 signal name SI RxD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Table 18 3 Wiring Between 78K0S KA1 and PG FPL2 PG FPL2 Connection Pin 78K0S KA1 Connection Pin Pin Name I O Pin Function Pin...

Page 268: ...olate the connection with the external device Perform the following processing 1 and 2 when on board writing is performed with the resonator mounted when it is difficult to isolate the resonator while a crystal or ceramic resonator is selected as the system clock 1 Mount the minimum possible test pads between the device and the resonator and connect the flash programmer via the test pad Keep the w...

Page 269: ...e usage environment these values may change so set them after having performed sufficient evaluations 18 6 2 RESET pin If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset signal generator on the board signal collision takes place To prevent this collision isolate the connection with the reset signal generator If the reset signal is inp...

Page 270: ...KA1 18 6 3 Port pins When the flash memory programming mode is set all the pins not used for flash memory programming enter the same status as that immediately after reset If external devices connected to the ports do not recognize the port status immediately after reset the port pin must be connected to VDD or VSS via a resistor The state of the pins in the self programming mode is the same as th...

Page 271: ...XX XXXXXX XXXX XXXX YYYY STATVE FlashPro4 Dedicated flash programmer Power Status MODE Target 3V Target PG FPL2 PG FPL2 Communication commands are listed in the table below All these communication commands are issued from the programmer and the 78K0S KA1 perform processing corresponding to the respective communication commands Table 18 6 Communication Commands Classification Command Name Function ...

Page 272: ...he batch erase chip erase command Write is prohibited Execution of the write and block erase commands for entire blocks in the flash memory is prohibited This prohibition setting can be cancelled using the batch erase chip erase command Remark The security setting is valid when the programming mode is set next time The batch erase chip erase block erase and write commands are enabled by the defaul...

Page 273: ...of the 78K0S KA1 as the external EEPROM for storing data refer to 78K0S Kx1 EEPROM Emulation AN U17379E 18 8 1 Outline of self programming To execute self programming shift the mode from the normal operation of the user program normal mode to the self programming mode Write erase processing for the flash memory which has been set to the register in advance is performed by executing the HALT instru...

Page 274: ...uit Erase circuit WEPRERR VCERR FPRERR HALT release signal FLCMD2 FLCMD1 FLCMD0 Internal bus Flash programming command register FLCMD Increment circuit Flash memory Protect byte PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 5 Flash address pointer H FLAPH Flash address pointer L FLAPL Flash address pointer H compare register FLAPHC Match Match Flash address pointer L compare register FLAPLC Flash write ...

Page 275: ...ution End Internal verify This command is used to check if data has been correctly written to the flash memory After data has been written to the memory specify the block number the start address and the end address then execute this command Internal verify for 1 block internal verify command executed once 6 8 ms Internal verify for 1 byte 27 µs Block erasure This command is used to erase a specif...

Page 276: ...elf programming mode the self programming command can be executed regardless of the security function setting To disable write or erase processing during self programming set the protect byte Be sure to clear bits 4 to 7 of flash address pointer H FLAPH and flash address pointer H compare register FLAPHC to 0 before executing the self programming command If the value of these bits is 1 when execut...

Page 277: ...f 16 µs is required from setting FLSPM to 1 to execution of the HALT instruction 2 Flash protect command register PFCMD If the application system stops inadvertently due to malfunction caused by noise or program hang up an operation to write the flash programming mode control register FLPMC may have a serious effect on the system PFCMD is used to protect FLPMC from being written so that the applic...

Page 278: ...mat of Flash Status Register PFS Address FFA1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PFS 0 0 0 0 0 WEPRERR VCERR FPRERR 1 Operating conditions of FPRERR flag Setting conditions If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to write a specific value A5H to FLPMC If the first store instruction operation after 1 is on a peripheral reg...

Page 279: ...s If the area specified by the protect byte to be protected from erasing or writing is specified by the flash address pointer H FLAPH and a command is executed to this area If 1 is written to a bit that has not been erased a bit for which the data is 0 Reset conditions When 0 is written to the WEPRERR flag When the reset signal is generated 4 Flash programming command register FLCMD This register ...

Page 280: ...the specified address in the flash memory Specify the write address and write data then execute this command If 1 is written to a bit that has not been erased a bit for which the data is 0 then bit 2 WEPRERR of the flash status register PFS becomes 1 Other than aboveNote Setting prohibited Note If a value other than the above is set and the self programming mode is set the self programming mode is...

Page 281: ...gramming mode Set FLAPHC to the same value as that of FLAPH Set the last address of the range in which verification is to be executed to FLAPLC These registers are set with a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears these registers to 00H Figure 18 17 Format of Flash Address Pointer H L Compare Registers FLAPHC FLAPLC Address FFA6H FFA7H After reset 00H R W FLA...

Page 282: ...lears these registers to 00H Figure 18 18 Format of Flash Write Buffer Register FLW Address FFA8H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 FLW FLW7 FLW6 FLW5 FLW4 FLW3 FLW2 FLW1 FLW0 8 Protect byte This protect byte is used to specify the area that is to be protected from writing or erasing The specified area is valid only in the self programming mode Because self programming of the protected ar...

Page 283: ...above Setting prohibited µPD78F9222 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 Status 0 1 0 0 0 Blocks 15 to 0 are protected 0 1 0 0 1 Blocks 13 to 0 are protected Blocks 14 and 15 can be written or erased 0 1 0 1 0 Blocks 11 to 0 are protected Blocks 12 to 15 can be written or erased 0 1 0 1 1 Blocks 9 to 0 are protected Blocks 10 to 15 can be written or erased 0 1 1 0 0 Blocks 7 to 0 are protected ...

Page 284: ...to FFH and executing the DI instruction 2 Clear the flash status register PFS 3 Set self programming mode using a specific sequence Write a specific value A5H to PFCMD Write 01H to FLPMC writing in this step is invalid Write 0FEH inverted value of 01H to FLPMC writing in this step is invalid Write 01H to FLPMC writing in this step is valid 4 Check the execution result of the specific sequence usin...

Page 285: ... Check execution result FPRERR flag Abnormal Normal When interrupt function is used 2 Clear PFS 5 Termination FLPMC 01H set value FLPMC 0FEH inverted set value FLPMC 01H set value Set value is invalid Set value is valid 3 Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased nor written Remark 1 to 5 in Figure 18 20 corres...

Page 286: ...ModeOnLoop MOV PFS 00H Clears flash status register MOV PFCMD 0A5H PFCMD register control MOV FLPMC 01H FLPMC register control sets value MOV FLPMC 0FEH FLPMC register control inverts set value MOV FLPMC 01H Sets self programming mode with FLPMC register control sets value MOV A PFS CMP A 00H BNZ ModeOnLoop Checks completion of write to specific registers Repeats the same processing when an error ...

Page 287: ...pecific value A5H to PFCMD Write 00H to FLPMC writing in this step is invalid Write 0FFH inverted value of 00H to FLPMC writing in this step is invalid Write 00H to FLPMC writing in this step is valid 3 Check the execution result of the specific sequence using bit 0 FPRERR of PFS Abnormal 1 normal 4 4 Enable interrupt servicing by executing the EI instruction and changing MK0 and MK1 to restore th...

Page 288: ...0H set value FLPMC 0FFH inverted set value FLPMC 00H set value Set value is invalid Set value is valid 4 Enable interrupts by executing EI instruction and changing MK0 MK1 When interrupt function is used 2 Caution Be sure to perform the series of operations described above using the user program at an address where data is not erased nor written Remark 1 to 5 in Figure 18 21 correspond to 1 to 5 i...

Page 289: ...0A5H PFCMD register control MOV FLPMC 00H FLPMC register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value MOV A PFS CMP A 00H BNZ ModeOffLoop Checks completion of write to specific registers Repeats the same processing when an error occurs MOV MK0 INT_MK0 Restores interrupt mask flag MOV MK1 INT_MK1 EI E...

Page 290: ...ter FLAPHC 5 Set the flash address pointer L compare register FLAPLC to 00H 6 Clear the flash status register PFS 7 Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Note 8 Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been executed 9 Check if a self prog...

Page 291: ...CERR and WEPRERR flags 8 Execute HALT instruction Normal 6 Clear PFS 1 Set erase command FLCMD 03H 2 Set no of block to be erased to FLAPH Block erasure 4 Set the same value as that of FLAPH to FLAPHC 10 Abnormal termination Abnormal 3 Set FLAPL to 00H 5 Set FLAPLC to 00H Note This setting is not required when the watchdog timer is not used Remark 1 to 11 in Figure 18 22 correspond to 1 to 11 in 1...

Page 292: ...s number of block to be erased block 7 is specified here MOV FLAPL 00H Fixes FLAPL to 00H MOV FLAPHC 07H Sets erase block compare number same value as that of FLAPH MOV FLAPLC 00H Fixes FLAPLC to 00H MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS MOV CmdStatus A Execution result is stored in variable CmdStatus 0 normal terminat...

Page 293: ...ess pointer H compare register FLAPHC 5 Set the flash address pointer L compare register FLAPLC to FFH 6 Clear the flash status register PFS 7 Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Note 8 Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been exec...

Page 294: ...d WEPRERR flags 8 Execute HALT instruction Normal Abnormal 6 Clear PFS 1 Set block blank check command FLCMD 04H 2 Set no of block for blank check to FLAPH Block blank check 10 Abnormal termination 5 Set FLAPLC to 00H 4 Set the same value as that of FLAPH to FLAPHC 3 Set FLAPL to 00H Note This setting is not required when the watchdog timer is not used Remark 1 to 11 in Figure 18 23 correspond to ...

Page 295: ... Sets number of block for blank check block 7 is specified here MOV FLAPL 00H Fixes FLAPL to 00H MOV FLAPHC 07H Sets blank check block compare number same value as that of FLAPH MOV FLAPLC 0FFH Fixes FLAPLC to FFH MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS MOV CmdStatus A Execution result is stored in variable CmdStatus 0 n...

Page 296: ...ite buffer register FLW 5 Clear the flash status register PFS 6 Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Note 7 Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming has been executed 8 Check if a self programming error has occurred using bit 1 VCERR and bit...

Page 297: ...ERR and WEPRERR flags 7 Execute HALT instruction Normal Abnormal 5 Clear PFS 1 Set byte write command FLCMD 05H Byte write 9 Abnormal termination 4 Set data to be written to FLW 2 Set no of block to be written to FLAPH 3 Set address at which data is to be written to FLAPL Note This setting is not required when the watchdog timer is not used Remark 1 to 10 in Figure 18 24 correspond to 1 to 10 in 1...

Page 298: ...ta is to be written with FLAPH block 7 is specified here MOV FLAPL 20H Sets address to which data is to be written with FLAPL address 20H is specified here MOV FLW 10H Sets data to be written 10H is specified here MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS MOV CmdStatus A Execution result is stored in variable CmdStatus 0 n...

Page 299: ...inter H compare register FLAPHC 5 Sets the verify end address to the flash address pointer L compare register FLAPLC 6 Clear the flash status register PFS 7 Write ACH to the watchdog timer enable register WDTE clear and restart the watchdog timer counter Note 8 Execute the HALT instruction then start self programming Execute an instruction immediately after the HALT instruction if self programming...

Page 300: ...flags 8 Execute HALT instruction Normal Abnormal 6 Clear PFS 1 Set internal verify command FLCMD 01H Internal verify 10 Abnormal termination 2 Set no of block for internal verify to FLAPH 4 Set the same value as that of FLAPH to FLAPHC 5 Set end address to FLAPLC 3 Set start address to FLAPL Note This setting is not required when the watchdog timer is not used Remark 1 to 11 in Figure 18 25 corres...

Page 301: ...H Sets verify start address with FLAPH block 7 is specified here MOV FLAPL 00H Sets verify start address with FLAPL Address 00H is specified here MOV FLAPHC 07H MOV FLAPLC 20H Sets verify end address MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS MOV CmdStatus A Execution result is stored in variable CmdStatus 0 normal terminat...

Page 302: ...ted from self programming mode to normal mode 1 to 5 in 18 8 5 Figure 18 26 Example of Operation When Command Execution Time Should Be Minimized from Erasure to Blank Check 4 Shift to normal mode Abnormal 1 Shift to self programming mode Erasure to blank check Abnormal terminationNote 2 Execute block erase 3 Execute block blank check 2 Check execution result VCERR and WEPRERR flags 3 Check executi...

Page 303: ...odeOnLoop Checks completion of write to specific registers Repeats the same processing when an error occurs FlashBlockErase MOV FLCMD 03H Sets flash control command block erase MOV FLAPH 07H Sets number of block to be erased block 7 is specified here MOV FLAPL 00H Fixes FLAPL to 00H MOV FLAPHC 07H Sets erase block compare number same value as that of FLAPH MOV FLAPLC 00H Fixes FLAPLC to 00H MOV WD...

Page 304: ...ster MOV PFCMD 0A5H PFCMD register control MOV FLPMC 00H FLPMC register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value MOV A PFS CMP A 00H BNZ ModeOffLoop Checks completion of write to specific registers Repeats the same processing when an error occurs MOV MK0 INT_MK0 Restores interrupt mask flag MOV M...

Page 305: ...mand Execution Time Should Be Minimized from Write to Internal Verify 6 Shift to normal mode Abnormal 1 Shift to self programming mode Write to internal verify 3 Execute byte write command 5 Execute internal verify command 3 Check execution result VCERR and WEPRERR flags 5 Check execution result VCERR and WEPRERR flags Normal termination Normal Abnormal Normal Figure 18 24 1 to 10 Figure 18 25 1 t...

Page 306: ...o specific registers Repeats the same processing when an error occurs FlashWrite MOVW HL DataAdrTop Sets address at which data to be written is located MOVW DE WriteAdr Sets address at which data is to be written FlashWriteLoop MOV FLCMD 05H Sets flash control command byte write MOV A D MOV FLAPH A Sets address at which data is to be written MOV A E MOV FLAPL A Sets address at which data is to be ...

Page 307: ...ted MOV A PFS CMP A 00H BNZ StatusError Checks internal verify error Performs abnormal termination processing when an error occurs ModeOffLoop MOV PFS 00H Clears flash status register MOV PFCMD 0A5H PFCMD register control MOV FLPMC 00H FLPMC register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value MOV A...

Page 308: ...ORY User s Manual U16898EJ3V0UD 308 normal mode in order to return to normal processing StatusError END normal termination processing StatusNormal Data to be written DataAdrTop DB XXH DB XXH DB XXH DB XXH DB XXH DataAdrBtm ...

Page 309: ...ase command 1 to 5 in 18 8 6 2 Mode is shifted from normal mode to self programming mode 1 to 5 in 18 8 4 3 Execution of block erase command Error check 6 to 11 in 18 8 6 4 Mode is shifted from self programming mode to normal mode 1 to 5 in 18 8 5 5 Specification of block blank check command 1 to 5 in 18 8 7 6 Mode is shifted from normal mode to self programming mode 1 to 5 in 18 8 4 7 Execution o...

Page 310: ...o self programming mode Figure 18 20 1 to 5 3 Execute block erase command Figure 18 22 6 to 11 4 Shift to normal mode Figure 18 21 1 to 5 5 Specify block blank check command 7 Check execution result VCERR and WEPRERR flags Figure 18 23 1 to 5 6 Shift to self programming mode Figure 18 20 1 to 5 7 Execute block blank check command Figure 18 23 6 to 11 8 Shift to normal mode Figure 18 21 1 to 5 Norm...

Page 311: ...WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS CMP A 00H BNZ StatusError Checks erase error Performs abnormal termination processing when an error occurs CALL ModeOff Shift to normal mode Sets blank check command MOV FLCMD 04H Sets flash control command block blank check MOV FLAPH 07H Sets block number for blank check block 7 is specified here MOV FLAPL 00H Fixes FLAPL to...

Page 312: ...ts MOV MK1 11111111B DI ModeOnLoop MOV PFS 00H Clears flash status register MOV PFCMD 0A5H PFCMD register control MOV FLPMC 01H FLPMC register control sets value MOV FLPMC 0FEH FLPMC register control inverts set value MOV FLPMC 01H Sets self programming mode via FLPMC register control sets value MOV A PFS CMP A 00H BNZ ModeOnLoop Checks completion of write to specific registers Repeats the same pr...

Page 313: ...ntrol inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value MOV A PFS CMP A 00H BNZ ModeOff Checks completion of write to specific registers Repeats the same processing when an error occurs MOV MK0 INT_MK0 Restores interrupt mask flag MOV MK1 INT_MK1 EI RET ...

Page 314: ...tion of byte write command Error check 5 to 10 in 18 8 8 5 Mode is shifted from self programming mode to normal mode 1 to 5 in 18 8 5 6 2 to 5 is repeated until all data are written 7 The internal verify command is specified 1 to 5 in 18 8 9 8 Mode is shifted from normal mode to self programming mode 1 to 5 in 18 8 4 9 Execution of internal verify command Error check 6 to 11 in 18 8 9 10 Mode is s...

Page 315: ...cute byte write command Figure 18 24 5 to 10 5 Shift to normal mode Figure 18 21 1 to 5 7 Specify internal verify command 9 Check execution result VCERR and WEPRERR flags Figure 18 25 1 to 5 8 Shift to self programming mode Figure 18 20 1 to 5 9 Execute internal verify command Figure 18 25 6 to 10 10 Shift to normal mode Figure 18 21 1 to 5 Normal 1 Set source data for write Write to internal veri...

Page 316: ... at which data is to be written MOV A HL MOV FLW A Sets data to be written CALL ModeOn Shift to self programming mode Execution of write command MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS CMP A 00H BNZ StatusError Checks write error Performs abnormal termination processing when an error occurs CALL ModeOff Shift to normal m...

Page 317: ... mode Execution of internal verify command MOV PFS 00H Clears flash status register MOV WDTE 0ACH Clears restarts WDT HALT Self programming is started MOV A PFS CMP A 00H BNZ StatusError Checks internal verify error Performs abnormal termination processing when an error occurs CALL ModeOff Shift to normal mode BR StatusNormal END abnormal termination processing Perform processing to shift to norma...

Page 318: ...fic registers Repeats the same processing when an error occurs RET Processing to shift to normal mode ModeOff MOV PFS 00H Clears flash status register MOV PFCMD 0A5H PFCMD register control MOV FLPMC 00H FLPMC register control sets value MOV FLPMC 0FFH FLPMC register control inverts set value MOV FLPMC 00H Sets normal mode via FLPMC register control sets value MOV A PFS CMP A 00H BNZ ModeOff Checks...

Page 319: ...CHAPTER 18 FLASH MEMORY User s Manual U16898EJ3V0UD 319 DB XXH DB XXH DB XXH DataAdrBtm ...

Page 320: ...irect address specification In the case of immediate data describe an appropriate numeric value or a label When using a label be sure to describe the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 19 1 Operand Identifiers and Description Methods Identifier...

Page 321: ...k pointer PSW Program status word CY Carry flag AC Auxiliary carry flag Z Zero flag IE Interrupt request enable flag Memory contents indicated by address or register contents in parentheses H L Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit data displacem...

Page 322: ...sfr sfr A 2 4 sfr A A addr16 3 8 A addr16 addr16 A 3 8 addr16 A PSW byte 3 6 PSW byte A PSW 2 4 A PSW PSW A 2 4 PSW A A DE 1 6 A DE DE A 1 6 DE A A HL 1 6 A HL HL A 1 6 HL A A HL byte 2 6 A HL byte MOV HL byte A 2 6 HL byte A A X 1 4 A X A r Note 2 2 6 A r A saddr 2 6 A saddr A sfr 2 6 A sfr A DE 1 8 A DE A HL 1 8 A HL XCH A HL byte 2 8 A HL byte Notes 1 Except r A 2 Except r A X Remark One instru...

Page 323: ...addr16 A HL 1 6 A CY A HL ADD A HL byte 2 6 A CY A HL byte A byte 2 4 A CY A byte CY saddr byte 3 6 saddr CY saddr byte CY A r 2 4 A CY A r CY A saddr 2 4 A CY A saddr CY A addr16 3 8 A CY A addr16 CY A HL 1 6 A CY A HL CY ADDC A HL byte 2 6 A CY A HL byte CY A byte 2 4 A CY A byte saddr byte 3 6 saddr CY saddr byte A r 2 4 A CY A r A saddr 2 4 A CY A saddr A addr16 3 8 A CY A addr16 A HL 1 6 A CY...

Page 324: ... 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL AND A HL byte 2 6 A A HL byte A byte 2 4 A A byte saddr byte 3 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL 1 6 A A HL OR A HL byte 2 6 A A HL byte A byte 2 4 A A byte saddr byte 3 6 saddr saddr byte A r 2 4 A A r A saddr 2 4 A A saddr A addr16 3 8 A A addr16 A HL ...

Page 325: ... DEC saddr 2 4 saddr saddr 1 INCW rp 1 4 rp rp 1 DECW rp 1 4 rp rp 1 ROR A 1 1 2 CY A7 A0 Am 1 Am 1 ROL A 1 1 2 CY A0 A7 Am 1 Am 1 RORC A 1 1 2 CY A0 A7 CY Am 1 Am 1 ROLC A 1 1 2 CY A7 A0 CY Am 1 Am 1 saddr bit 3 6 saddr bit 1 sfr bit 3 6 sfr bit 1 A bit 2 4 A bit 1 PSW bit 3 6 PSW bit 1 SET1 HL bit 2 10 HL bit 1 saddr bit 3 6 saddr bit 0 sfr bit 3 6 sfr bit 0 A bit 2 4 A bit 0 PSW bit 3 6 PSW bit...

Page 326: ... saddr16 2 6 PC PC 2 jdisp8 if Z 1 BNZ saddr16 2 6 PC PC 2 jdisp8 if Z 0 saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 1 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 1 A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 BT PSW bit addr16 4 10 PC PC 4 jdisp8 if PSW bit 1 saddr bit addr16 4 10 PC PC 4 jdisp8 if saddr bit 0 sfr bit addr16 4 10 PC PC 4 jdisp8 if sfr bit 0 A bit addr16 3 8 PC PC 3 jdisp8 i...

Page 327: ...L byte addr16 1 None A ADD ADDC SUB SUBC AND OR XOR CMP MOVNot e XCHNot e ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV MOV INC DEC B C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MOV DBNZ INC ...

Page 328: ...rp Note saddrp SP None AX ADDW SUBW CMPW MOVW XCHW MOVW MOVW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW sp MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions SET1 CLR1 NOT1 BT BF 2nd Operand 1st Operand addr16 None A bit BT BF SET1 CLR1 sfr bit BT BF SET1 CLR1 saddr bit BT BF SET1 CLR1 PSW bit BT BF SET1 CLR1 HL bit SET1 CLR1 CY SET1 CLR1 NOT1 ...

Page 329: ...3V0UD 329 4 Call instructions branch instructions CALL CALLT BR BC BNC BZ BNZ DBNZ 2nd Operand 1st Operand AX addr16 addr5 addr16 Basic instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound instructions DBNZ 5 Other instructions RET RETI NOP EI DI HALT STOP ...

Page 330: ...r than P20 to P23 44 0 mA Output current high IOH Total of P20 to P23 44 0 mA Per pin 20 0 mA Output current low IOL Total of all pins 44 0 mA In normal operation mode Operating ambient temperature TA During flash memory programming 40 to 85 C Flash memory blank status 65 to 150 C Storage temperature Tstg Flash memory programming already performed 40 to 125 C Note Must be 6 5 V or lower Caution Pr...

Page 331: ...ion voltage VPOC of the power on clear POC circuit is 2 1 V 0 1 V 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Caution When using the X1 oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiri...

Page 332: ...fX Note 2 2 0 V VDD 2 7 V 5 5 MHz Notes 1 Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 1 V 0 1 V 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Low Speed Internal Oscillator Characteristics TA 40 to 85 C VDD 2 0 to 5 5 V Note VSS 0 V Resonator Parameter Condition...

Page 333: ...2 0 0 3VDD V Total of pins other than P20 to P23 IOH1 15 mA 4 0 V VDD 5 5 V IOH1 5 mA VDD 1 0 V VOH1 IOH1 100 µA 2 0 V VDD 4 0 V VDD 0 5 V 4 0 V AVREF 5 5 V IOH2 5 mA AVREF 1 0 V Output voltage high VOH2 Total of pins P20 to P23 IOH2 10 mA 2 0 V AVREF 4 0 V IOH2 5 mA AVREF 0 5 V Total of pins IOL 30 mA 4 0 V VDD 5 5 V IOL 10 mA 1 3 V Output voltage low VOL 2 0 V VDD 4 0 V IOL 400 µA 0 4 V Input le...

Page 334: ...peed internal oscillation operating mode Note 7 fX 8 MHz VDD 5 0 V 10 Note 4 When A D converter is operating Note 8 6 5 13 0 mA When peripheral functions are stopped 1 4 3 2 IDD4 High speed internal oscillation HALT mode Note 7 fX 8 MHz VDD 5 0 V 10 Note 4 When peripheral functions are operating 5 9 mA When low speed internal oscillation is stopped 3 5 35 5 VDD 5 0 V 10 When low speed internal osc...

Page 335: ...cle time minimum instruction execution time TCY High speed internal oscillation clock 2 0 V VDD 2 7 V 0 95 4 22 µs 4 0 V VDD 5 5 V 2 fsam 0 1 Note 2 µs TI000 input high level width low level width tTIH tTIL 2 0 V VDD 4 0 V 2 fsam 0 2 Note 2 µs Interrupt input high level width low level width tINTH tINTL 1 µs RESET input low level width tRSL 2 µs Notes 1 Use this product in a voltage range of 2 2 t...

Page 336: ...vs VDD Crystal Ceramic Oscillation Clock External Clock Input Supply voltage VDD V 1 2 3 4 5 6 0 1 0 4 1 0 10 60 Cycle time T CY s Guaranteed operation range 0 33 2 7 5 5 µ 16 TCY vs VDD High speed internal ocillator Clock 1 2 3 4 5 6 0 1 1 0 10 60 2 7 5 5 0 23 4 22 0 47 0 95 Supply voltage VDD V Cycle time T CY s Guaranteed operation range µ ...

Page 337: ...tor output Parameter Symbol Conditions MIN TYP MAX Unit Transfer rate 312 5 kbps Note Use this product in a voltage range of 2 2 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 1 V 0 1 V AC Timing Test Points Excluding X1 Input 0 8VDD 0 2VDD 0 8VDD 0 2VDD Test points Clock Timing 1 fX tXL tXH X1 input TI000 Timing tTIL tTIH TI000 Interrupt Input Timing INTP0 to I...

Page 338: ...cale error Notes 2 3 Ezs 2 7 V AVREF 4 0 V 0 6 FSR 4 0 V AVREF 5 5 V 0 4 FSR Full scale error Notes 2 3 Efs 2 7 V AVREF 4 0 V 0 6 FSR 4 0 V AVREF 5 5 V 2 5 LSB Integral non linearity error Note 2 ILE 2 7 V AVREF 4 0 V 4 5 LSB 4 0 V AVREF 5 5 V 1 5 LSB Differential non linearity error Note 2 DLE 2 7 V AVREF 4 0 V 2 0 LSB Analog input voltage VAIN VSS Note 1 AVREF V Notes 1 In the 78K0S KA1 VSS func...

Page 339: ...VDD 0 V 2 1 V 1 5 µs Response delay time 1 Note 1 tPTHD When power supply rises after reaching detection voltage MAX 3 0 ms Response delay time 2 Note 2 tPD When power supply falls 1 0 ms Minimum pulse width tPW 0 2 ms Notes 1 Time required from voltage detection to internal reset release 2 Time required from voltage detection to internal reset signal generation POC Circuit Timing Supply voltage V...

Page 340: ...nimum pulse width tLW 0 2 ms Operation stabilization wait time Note 2 tLWAIT 0 1 0 2 ms Notes 1 Time required from voltage detection to interrupt output or internal reset signal generation 2 Time required from setting LVION to 1 to operation stabilization Remarks 1 VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 VLVI8 VLVI9 2 VPOC VLVIm m 0 to 9 LVI Circuit Timing Supply voltage VDD Detection volt...

Page 341: ...0 2 7 V VDD 3 5 V 12 3 s 4 5 V VDD 5 5 V 0 4 s 3 5 V VDD 4 5 V 0 5 s TA 10 to 85 C NERASE 100 2 7 V VDD 3 5 V 0 6 s 4 5 V VDD 5 5 V 2 6 s 3 5 V VDD 4 5 V 2 8 s TA 10 to 85 C NERASE 1000 2 7 V VDD 3 5 V 3 3 s 4 5 V VDD 5 5 V 0 9 s 3 5 V VDD 4 5 V 1 0 s TA 40 to 85 C NERASE 100 2 7 V VDD 3 5 V 1 1 s 4 5 V VDD 5 5 V 4 9 s 3 5 V VDD 4 5 V 5 4 s Block erase time TBERASE TA 40 to 85 C NERASE 1000 2 7 V ...

Page 342: ...H Total of P20 to P23 44 0 mA Per pin 20 0 mA Output current low IOL Total of all pins 44 0 mA TA 40 to 85 C 120 mW PT Note 2 TA 85 to 125 C 110 mW In normal operation mode 40 to 125 C Operating ambient temperature TA During flash memory programming 40 to 105 C Flash memory blank status 65 to 150 C Storage temperature Tstg Flash memory programming already performed 40 to 125 C Notes 1 Must be 6 5 ...

Page 343: ...85 Temperature C Total loss P T mW 120 50 100 150 120 125 110 Use the following formula to perform design such that the sum of the power consumption of the device is less than or equal to the total loss PT use at 80 or less of the rated value is recommended Total power consumption VDD IDD IOH VDD VOH IOH VOH IOL Caution When using the internal pull up resistor calculate and add the separate power ...

Page 344: ...e VPOC of the power on clear POC circuit is 2 26 V MAX 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Caution When using the X1 oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the...

Page 345: ... 2 0 V VDD 2 7 V 5 5 MHz Notes 1 Use this product in a voltage range of 2 26 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 26 V MAX 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Low Speed Internal Oscillator Characteristics TA 40 to 125 C VDD 2 0 to 5 5 V Note VSS 0 V Resonator Parameter Conditions MIN TY...

Page 346: ... 3VDD V Total of pins other than P20 to P23 IOH1 10 5 mA 4 0 V VDD 5 5 V IOH1 3 5 mA VDD 1 0 V VOH1 IOH1 100 µA 2 0 V VDD 4 0 V VDD 0 5 V 4 0 V AVREF 5 5 V IOH2 3 5 mA AVREF 1 0 V Output voltage high VOH2 Total of pins P20 to P23 IOH2 7 mA 2 0 V AVREF 4 0 V IOH2 3 5 mA AVREF 0 5 V Total of pins IOL 21 mA 4 0 V VDD 5 5 V IOL 7 mA 1 3 V Output voltage low VOL 2 0 V VDD 4 0 V IOL 400 µA 0 4 V Input l...

Page 347: ...ernal oscillation operating mode Note 7 fX 8 MHz VDD 5 0 V 10 Note 4 When A D converter is operating Note 8 6 5 15 2 mA When peripheral functions are stopped 1 4 4 4 IDD4 High speed internal oscillation HALT mode Note 7 fX 8 MHz VDD 5 0 V 10 Note 4 When peripheral functions are operating 7 1 mA When low speed internal oscillation is stopped 3 5 1200 VDD 5 0 V 10 When low speed internal oscillation...

Page 348: ...minimum instruction execution time TCY High speed internal oscillation clock 2 0 V VDD 2 7 V 0 95 4 22 µs 4 0 V VDD 5 5 V 2 fsam 0 1 Note 2 µs TI000 input high level width low level width tTIH tTIL 2 0 V VDD 4 0 V 2 fsam 0 2 Note 2 µs Interrupt input high level width low level width tINTH tINTL 1 µs RESET input low level width tRSL 2 µs Notes 1 Use this product in a voltage range of 2 26 to 5 5 V ...

Page 349: ...al Ceramic Oscillation Clock External Clock Input Supply voltage VDD V 1 2 3 4 5 6 0 1 0 4 1 0 10 60 Cycle time T CY s Guaranteed operation range 0 33 2 7 5 5 µ 16 0 25 TCY vs VDD High speed internal ocillator Clock 1 2 3 4 5 6 0 1 1 0 10 60 2 7 5 5 0 23 4 22 0 47 0 95 Supply voltage VDD V Cycle time T CY s Guaranteed operation range µ ...

Page 350: ...t Parameter Symbol Conditions MIN TYP MAX Unit Transfer rate 312 5 kbps Note Use this product in a voltage range of 2 26 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 26 V MAX AC Timing Test Points Excluding X1 Input 0 8VDD 0 2VDD 0 8VDD 0 2VDD Test points Clock Timing 1 fX tXL tXH X1 input TI000 Timing tTIL tTIH TI000 Interrupt Input Timing INTP0 to INTP3 tINT...

Page 351: ...Notes 2 3 Ezs 2 7 V AVREF 4 0 V 0 9 FSR 4 0 V AVREF 5 5 V 0 7 FSR Full scale error Notes 2 3 Efs 2 7 V AVREF 4 0 V 0 9 FSR 4 0 V AVREF 5 5 V 5 5 LSB Integral non linearity error Note 2 ILE 2 7 V AVREF 4 0 V 7 5 LSB 4 0 V AVREF 5 5 V 2 5 LSB Differential non linearity error Note 2 DLE 2 7 V AVREF 4 0 V 3 0 LSB Analog input voltage VAIN VSS Note 1 AVREF V Notes 1 In the 78K0S KA1 VSS functions alter...

Page 352: ...2 1 V 1 5 µs Response delay time 1 Note 1 tPTHD When power supply rises after reaching detection voltage MAX 3 0 ms Response delay time 2 Note 2 tPD When power supply falls 1 0 ms Minimum pulse width tPW 0 2 ms Notes 1 Time required from voltage detection to internal reset release 2 Time required from voltage detection to internal reset signal generation POC Circuit Timing Supply voltage VDD Detec...

Page 353: ...pulse width tLW 0 2 ms Operation stabilization wait time Note 2 tLWAIT 0 1 0 2 ms Notes 1 Time required from voltage detection to interrupt output or internal reset signal generation 2 Time required from setting LVION to 1 to operation stabilization Remarks 1 VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 VLVI8 VLVI9 2 VPOC VLVIm m 0 to 9 LVI Circuit Timing Supply voltage VDD Detection voltage MI...

Page 354: ... 5 V VDD 4 5 V 0 5 s TA 10 to 105 C NERASE 100 2 7 V VDD 3 5 V 0 6 s 4 5 V VDD 5 5 V 2 6 s 3 5 V VDD 4 5 V 2 8 s TA 10 to 105 C NERASE 1000 2 7 V VDD 3 5 V 3 3 s 4 5 V VDD 5 5 V 0 9 s 3 5 V VDD 4 5 V 1 0 s TA 40 to 105 C NERASE 100 2 7 V VDD 3 5 V 1 1 s 4 5 V VDD 5 5 V 4 9 s 3 5 V VDD 4 5 V 5 4 s Block erase time TBERASE TA 40 to 105 C NERASE 1000 2 7 V VDD 3 5 V 6 6 s Byte write time TWRITE TA 40...

Page 355: ...ng formula to perform design such that the sum of the power consumption of the device is less than or equal to the total loss PT use at 80 or less of the rated value is recommended Total power consumption VDD IDD IOH VDD VOH IOH VOH IOL Caution When using the internal pull up resistor calculate and add the separate power consumption Remark During flash memory programming IDD 7 0 mA MAX ...

Page 356: ... Total of P20 to P23 30 0 mA Per pin 14 0 mA Output current low IOL Total of all pins 30 0 mA TA 40 to 85 C 120 mW PT Note 2 TA 85 to 125 C 110 mW In normal operation mode 40 to 125 C Operating ambient temperature TA During flash memory programming 40 to 105 C Flash memory blank status 65 to 150 C Storage temperature Tstg Flash memory programming already performed 40 to 125 C Notes 1 Must be 6 5 V...

Page 357: ...85 Temperature C Total loss P T mW 120 50 100 150 120 125 110 Use the following formula to perform design such that the sum of the power consumption of the device is less than or equal to the total loss PT use at 80 or less of the rated value is recommended Total power consumption VDD IDD IOH VDD VOH IOH VOH IOL Caution When using the internal pull up resistor calculate and add the separate power ...

Page 358: ...e VPOC of the power on clear POC circuit is 2 26 V MAX 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Caution When using the X1 oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the...

Page 359: ... 2 0 V VDD 2 7 V 5 5 MHz Notes 1 Use this product in a voltage range of 2 26 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 26 V MAX 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Low Speed Internal Oscillator Characteristics TA 40 to 125 C VDD 2 0 to 5 5 V Note VSS 0 V Resonator Parameter Conditions MIN TY...

Page 360: ... 3VDD V Total of pins other than P20 to P23 IOH1 10 5 mA 4 0 V VDD 5 5 V IOH1 3 5 mA VDD 1 0 V VOH1 IOH1 100 µA 2 0 V VDD 4 0 V VDD 0 5 V 4 0 V AVREF 5 5 V IOH2 3 5 mA AVREF 1 0 V Output voltage high VOH2 Total of pins P20 to P23 IOH2 7 mA 2 0 V AVREF 4 0 V IOH2 3 5 mA AVREF 0 5 V Total of pins IOL 21 mA 4 0 V VDD 5 5 V IOL 7 mA 1 3 V Output voltage low VOL 2 0 V VDD 4 0 V IOL 400 µA 0 4 V Input l...

Page 361: ...ernal oscillation operating mode Note 7 fX 8 MHz VDD 5 0 V 10 Note 4 When A D converter is operating Note 8 6 5 15 2 mA When peripheral functions are stopped 1 4 4 4 IDD4 High speed internal oscillation HALT mode Note 7 fX 8 MHz VDD 5 0 V 10 Note 4 When peripheral functions are operating 7 1 mA When low speed internal oscillation is stopped 3 5 1200 VDD 5 0 V 10 When low speed internal oscillation...

Page 362: ...minimum instruction execution time TCY High speed internal oscillation clock 2 0 V VDD 2 7 V 0 95 4 22 µs 4 0 V VDD 5 5 V 2 fsam 0 1 Note 2 µs TI000 input high level width low level width tTIH tTIL 2 0 V VDD 4 0 V 2 fsam 0 2 Note 2 µs Interrupt input high level width low level width tINTH tINTL 1 µs RESET input low level width tRSL 2 µs Notes 1 Use this product in a voltage range of 2 26 to 5 5 V ...

Page 363: ...al Ceramic Oscillation Clock External Clock Input Supply voltage VDD V 1 2 3 4 5 6 0 1 0 4 1 0 10 60 Cycle time T CY s Guaranteed operation range 0 33 2 7 5 5 µ 16 0 25 TCY vs VDD High speed internal ocillator Clock 1 2 3 4 5 6 0 1 1 0 10 60 2 7 5 5 0 23 4 22 0 47 0 95 Supply voltage VDD V Cycle time T CY s Guaranteed operation range µ ...

Page 364: ...t Parameter Symbol Conditions MIN TYP MAX Unit Transfer rate 312 5 kbps Note Use this product in a voltage range of 2 26 to 5 5 V because the detection voltage VPOC of the power on clear POC circuit is 2 26 V MAX AC Timing Test Points Excluding X1 Input 0 8VDD 0 2VDD 0 8VDD 0 2VDD Test points Clock Timing 1 fX tXL tXH X1 input TI000 Timing tTIL tTIH TI000 Interrupt Input Timing INTP0 to INTP3 tINT...

Page 365: ...Notes 2 3 Ezs 2 7 V AVREF 4 0 V 0 9 FSR 4 0 V AVREF 5 5 V 0 7 FSR Full scale error Notes 2 3 Efs 2 7 V AVREF 4 0 V 0 9 FSR 4 0 V AVREF 5 5 V 5 5 LSB Integral non linearity error Note 2 ILE 2 7 V AVREF 4 0 V 7 5 LSB 4 0 V AVREF 5 5 V 2 5 LSB Differential non linearity error Note 2 DLE 2 7 V AVREF 4 0 V 3 0 LSB Analog input voltage VAIN VSS Note 1 AVREF V Notes 1 In the 78K0S KA1 VSS functions alter...

Page 366: ...2 1 V 1 5 µs Response delay time 1 Note 1 tPTHD When power supply rises after reaching detection voltage MAX 3 0 ms Response delay time 2 Note 2 tPD When power supply falls 1 0 ms Minimum pulse width tPW 0 2 ms Notes 1 Time required from voltage detection to internal reset release 2 Time required from voltage detection to internal reset signal generation POC Circuit Timing Supply voltage VDD Detec...

Page 367: ...pulse width tLW 0 2 ms Operation stabilization wait time Note 2 tLWAIT 0 1 0 2 ms Notes 1 Time required from voltage detection to interrupt output or internal reset signal generation 2 Time required from setting LVION to 1 to operation stabilization Remarks 1 VLVI0 VLVI1 VLVI2 VLVI3 VLVI4 VLVI5 VLVI6 VLVI7 VLVI8 VLVI9 2 VPOC VLVIm m 0 to 9 LVI Circuit Timing Supply voltage VDD Detection voltage MI...

Page 368: ... 5 V VDD 4 5 V 0 5 s TA 10 to 105 C NERASE 100 2 7 V VDD 3 5 V 0 6 s 4 5 V VDD 5 5 V 2 6 s 3 5 V VDD 4 5 V 2 8 s TA 10 to 105 C NERASE 1000 2 7 V VDD 3 5 V 3 3 s 4 5 V VDD 5 5 V 0 9 s 3 5 V VDD 4 5 V 1 0 s TA 40 to 105 C NERASE 100 2 7 V VDD 3 5 V 1 1 s 4 5 V VDD 5 5 V 4 9 s 3 5 V VDD 4 5 V 5 4 s Block erase time TBERASE TA 40 to 105 C NERASE 1000 2 7 V VDD 3 5 V 6 6 s Byte write time TWRITE TA 40...

Page 369: ...ng formula to perform design such that the sum of the power consumption of the device is less than or equal to the total loss PT use at 80 or less of the rated value is recommended Total power consumption VDD IDD IOH VDD VOH IOH VOH IOL Caution When using the internal pull up resistor calculate and add the separate power consumption Remark During flash memory programming IDD 7 0 mA MAX ...

Page 370: ...M B C I L M N 20 PIN PLASTIC SSOP 7 62 mm 300 A K D E F G H J P T MILLIMETERS 0 65 T P 0 475 MAX 0 13 0 5 6 1 0 2 0 10 6 65 0 15 0 17 0 03 0 1 0 05 0 24 1 3 0 1 8 1 0 2 1 2 0 08 0 07 1 0 0 2 3 5 3 0 25 0 6 0 15 U NOTE Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition S20MC 65 5A4 2 ...

Page 371: ...P Index mark Leed free markNote 2 Products for which writing has already been performed 1 µPD78F9221 F9221 XXXZZ YWWP Index mark Leed free markNote 2 µPD78F9222 F9222 XXXZZ YWWP Index mark Leed free markNote W Week code 2 digit number Y Last digit of year 1 digit number Z Grade indication XXX ROM code P In house control code Note The lead free marking is applied only on lead free products ...

Page 372: ...MC A2 5A4 Note 1 78F9222MC A2 5A4 Note 1 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher Count 3 times or less Exposure limit 7 days Note 2 after that prebake at 125 C for 20 hours IR35 207 3 VPS Package peak temperature 215 C Time 40 seconds max at 200 C or higher Count 3 times or less Exposur...

Page 373: ...A2 5A4 A Note 1 Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature 260 C Time 30 seconds max at 210 C or higher Count 3 times or less Exposure limit 7 days Note 2 after that prebake at 125 C for 20 hours IR60 207 3 Wave soldering For details contact an NEC Electronics sales representative Partial heating Pin temperature 350 C max Time 3 seco...

Page 374: ...mpatibility with PC98 NX series Unless stated otherwise products which are supported by IBM PC ATTM and compatibles can also be used with the PC98 NX series When using the PC98 NX series therefore refer to the explanations for IBM PC AT and compatibles WindowsTM Unless stated otherwise Windows refers to the following operating systems Windows 98 Windows NTTM Ver 4 0 Windows 2000 Windows XP ...

Page 375: ...le or emulation probe Pin header or conversion socket Target system Flash programmer Flash memory writing adapter Flash memory Power supply unit Software package Control software Project Manager Windows version only Note 2 Software package Flash memory writing environment Notes 1 The C library source file is not included in the software package 2 The Project Manager PM is included in the assembler...

Page 376: ...m Flash programmer Flash memory writing adapter Flash memory Power supply unit Software package Control software Project Manager Windows version only Note 2 Software package Flash memory writing environment In circuit emulatorNote 3 QB 78K0SMINI Notes 1 The C library source file is not included in the software package 2 The Project Manager PM is included in the assembler package PM is used only in...

Page 377: ...er package is a DOS based application but may be used under the Windows environment by using PM included in the assembler package RA78K0S Assembler package Part number µS RA78K0S Program that converts program written in C language into object codes that can be executed by microcontroller Used in combination with assembler package RA78K0S and device file DF789234 both sold separately Caution when u...

Page 378: ...tly developed in the Windows environment With this software a series of user program development operations including starting the editor build and starting the debugger can be executed on PM Caution PM is included in the assembler package RA78K0S It can be used only in the Windows environment A 4 Flash Memory Writing Tools Flashpro IV FL PR4 PG FP4 Flash memory programmer Flash programmer dedicat...

Page 379: ...emulating the peripheral hardware inherent to the device Used in combination with in circuit emulator A target cable is provided NP 30MC Emulation probe This probe is used to connect the in circuit emulator to the target system and is designed for use with a 30 pin plastic SSOP MC 5A4 type NSPACK20BK YSPACK30BK Conversion connector This conversion connector connects the NP 30MC to a target system ...

Page 380: ...e This is a system simulator for the 78K 0S series SM for 78K0S is Windows based software This simulator can execute C source level or assembler level debugging while simulating the operations of the target system on the host machine By using SM for 78K0S the logic and performance of the application can be verified independently of hardware development Therefore the development efficiency can be e...

Page 381: ...f parts to be mounted on the target system when designing a system Figure B 1 Distance Between In Circuit Emulator IE 78K0S NS IE 78K0S NS A and Conversion Connector NP 30MC In circuit emulator IE 78K0S NS IE 78K0S NS A Emulation board IE 789234 NS EM1 Target system CN5 Emulation probe NP 30MC Conversion connector YSPACK20BK NSPACK30BK NP 30MC tip board 150 mm Remarks 1 The NP 30MC is a product ma...

Page 382: ...K0S NS IE 78K0S NS A 31 mm 37 mm Target system Emulation probe NP 30MC 13 mm Emulation board IE 789234 NS EM1 15 mm 20 mm 5 mm NP 30MC tip board Conversion connector YSPACK30BK NSPACK20BK Guide pin YQ Guide Remarks 1 The NP 30MC is a product made by Naito Densei Machida Mfg Co Ltd 2 The YSPACK30BK and NSPACK20BK are products by Naito Densei Machida Mfg Co Ltd ...

Page 383: ...t channel specify register ADS 163 Asynchronous serial interface operation mode register 6 ASIM6 183 Asynchronous serial interface reception error status register 6 ASIS6 185 Asynchronous serial interface transmission status register 6 ASIF6 186 Asynchronous serial interface control register 6 ASICL6 189 B Baud rate generator control register 6 BRGC6 188 C Capture compare control register 00 CRC00...

Page 384: ...de register 2 PM2 60 164 Port mode register 3 PM3 60 92 Port mode register 4 PM4 60 134 191 Port mode register 12 PM12 60 Port register 2 P2 61 Port register 3 P3 61 Port register 4 P4 61 Port register 12 P12 61 Port register 13 P13 61 Preprocessor clock control register PPCC 69 Prescaler mode register 00 PRM00 91 Processor clock control register PCC 69 Pull up resistance option register 2 PU2 64 ...

Page 385: ... bit timer capture compare register 000 84 CR010 16 bit timer capture compare register 010 86 CR80 8 bit compare register 80 124 CRC00 Capture compare control register 00 89 F FLAPH Flash address pointer H 280 FLAPHC Flash address pointer H compare register 281 FLAPL Flash address pointer L 280 FLAPLC Flash address pointer L compare register 281 FLCMD Flash programming command register 279 FLPMC F...

Page 386: ...er 2 62 164 PPCC Preprocessor clock control register 69 PRM00 Prescaler mode register 00 91 PU2 Pull up resistance option register 2 64 PU3 Pull up resistance option register 3 64 PU4 Pull up resistance option register 4 64 PU12 Pull up resistance option register 12 64 R RESF Reset control flag register 244 RXB6 Receive buffer register 6 182 T TM00 16 bit timer counter 00 84 TM80 8 bit timer count...

Page 387: ...e reset state is not released When it is used as an input port pin connect the pull up resistor p 53 P31 P31 P43 Because P30 P31 and P43 are also used as external interrupt pins the corresponding interrupt request flag is set if each of these pins is set to the output mode and its output level is changed To use the port pin in the output mode therefore set the corresponding interrupt mask flag to ...

Page 388: ...ted after the value of CR000 is changed pp 85 116 Soft The value of CR000 after 16 bit timer event counter 00 has stopped is not guaranteed pp 85 117 The capture operation may not be performed for CR000 set in compare mode even if a capture trigger is input pp 85 119 When P31 is used as the input pin for the valid edge of TI010 it cannot be used as a timer output TO00 Moreover when P31 is used as ...

Page 389: ...ree running mode is selected when the set value of CR000 is FFFFH and the TM00 value changes from FFFFH to 0000H the OVF00 flag is set to 1 p 88 Even if the OVF00 flag is cleared before the next count clock is counted before TM00 becomes 0001H after the occurrence of a TM00 overflow the OVF00 flag is re set newly and clear is disabled pp 88 118 TMC00 16 bit timer mode control register 00 The captu...

Page 390: ...k and when it is used as a capture trigger In the former case the count clock is fXP and in the latter case the count clock is selected by prescaler mode register 00 PRM00 The capture operation is not performed until the valid edge is sampled and the valid level is detected twice thus eliminating noise with a short pulse width pp 92 121 Hard PRM00 Prescaler mode register 00 When using P31 as the i...

Page 391: ...one clock may occur in the time required for a match signal to be generated after timer start This is because 16 bit timer counter 00 TM00 is started asynchronously to the count clock p 116 One shot pulse output One shot pulse output normally operates only in the free running mode or in the clear start mode at the valid edge of the TI000 pin Because an overflow does not occur in the clear start mo...

Page 392: ...it compare register 80 CR80 can be set to 00H p 128 Chapter 7 Soft 8 bit timer 80 Stting STOP mode Before executing the STOP instruction be sure to stop the timer operation TCE80 0 p 128 CMP01 8 bit timer H compare register 01 CMP01 cannot be rewritten during timer count operation p 131 CMP11 8 bit timer H compare register 11 In the PWM output mode be sure to set CMP11 when starting the timer coun...

Page 393: ...og timer overflows after STOP instruction execution If this processing is not performed an internal reset signal is generated when the watchdog timer overflows after STOP instruction execution p 149 Chapter 9 Hard d Watchdog timer when low speed internal oscillator can be stopped by software is selected by option byte In this mode watchdog timer operation is stopped during HALT STOP instruction ex...

Page 394: ...nalog input channel the converted value of that channel becomes undefined In addition the converted values of the other channels may also be affected p 172 Conflict between A D conversion result register ADCR ADCRH write and ADCR ADCRH read by instruction upon the end of conversion ADCR ADCRH read has priority After the read operation the new conversion result is written to ADCR ADCRH p 172 Soft C...

Page 395: ...not fall within the rating range if the ADCS bit is set to 1 within 1 µs after the ADCE bit was set to 1 or if the ADCS bit is set to 1 with the ADCE bit 0 Take measures such as polling the A D conversion end interrupt request INTAD and removing the first conversion result p 174 Chapter 10 Soft A D converter A D conversion result register ADCR ADCRH read operation When a write operation is perform...

Page 396: ...t discarded p 185 ASIS6 Asynchronous serial interface reception error status register 6 Be sure to read ASIS6 before reading receive buffer register 6 RXB6 pp 185 203 To transmit data continuously write the first transmit data first byte to the TXB6 register Be sure to check that the TXBF6 flag is 0 If so write the next transmit data second byte to the TXB6 register If data is written to the TXB6 ...

Page 397: ...nuous transmission is possible or not by reading only the TXBF flag p 199 Continuous transmission When the device is incorporated in a LIN the continuous transmission function cannot be used Make sure that asynchronous serial interface transmission status register 6 ASIF6 is 00H before writing transmit data to transmit buffer register 6 TXB6 p 199 TXBF6 during continuous transmission Bit 1 of ASIF...

Page 398: ...ure to clear bits 2 to 7 to 0 p 221 INTM1 External interrupt mode register 1 Before setting INTM1 set PMK3 to 1 to disable interrupts To enable interrupts clear PIF3 to 0 then clear PMK3 to 0 p 221 Interrupt requests are held pending Interrupt requests will be held pending while the interrupt request flag registers IF0 IF1 or interrupt mask flag registers MK0 MK1 are being accessed p 224 Chapter 1...

Page 399: ...tion the system clock and low speed internal oscillation clock stop oscillating p 237 When the RESET pin is used as an input only port pin P34 the 78K0S KA1 is reset if a low level is input to the RESET pin after reset is released by the POC circuit and before the option byte is referenced again The reset status is retained until a high level is input to the RESET pin p 237 The LVI circuit is not ...

Page 400: ...ced then the reset state is not released Also when setting 0 to RMCE connect the pull up resistor p 260 Selection of system clock source Because the X1 and X2 pins are also used as the P121 and P122 pins the conditions under which the X1 and X2 pins can be used differ depending on the selected system clock source 1 Crystal ceramic oscillation clock is selected The X1 and X2 pins cannot be used as ...

Page 401: ...sure is FFH p 276 When the oscillator or the external clock is selected as the main clock a wait time of 16 µs is required starting from the setting of the self programming mode to the execution of the HALT instruction p 276 The state of the pins in self programming mode is the same as that in HALT mode p 276 Since the security function set via on board off board programming is disabled in self pr...

Page 402: ...that ensure that the absolute maximum ratings are not exceeded p 330 X1 oscillator characteristics When using the X1 oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line thro...

Page 403: ...hich the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded p 356 Allowable loss When using the internal pull up resistor calculate and add the separate power consumption pp 357 369 X1 oscillator characteristics When using the X1 oscillator wire as follows in the area enclosed b...

Page 404: ... 88 Modification of Caution 2 in Figure 6 5 Format of 16 Bit Timer Mode Control Register 00 TMC00 p 97 Addition of 1 INTTM000 generation timing immediately after operation starts to Figure 6 16 External Event Counter Operation Timing with Rising Edge Specified pp 99 101 102 104 Addition of Caution to 1 2 3 and 4 in 6 4 3 Pulse width measurement operations p 100 Modification of Figure 6 19 Configur...

Page 405: ...Operation p 178 Modification of Figure 11 2 LIN Reception Operation and description p 191 Addition of description to 7 Input switch control register ISC in 11 3 Registers Controlling Serial Interface UART6 p 210 Modification of value in Table 11 4 Set Data of Baud Rate Generator p 214 Modification of 12 1 Interrupt Function Types p 224 Modification of 12 4 2 Multiple interrupt servicing p 225 Addi...

Page 406: ... memory programming mode p 271 Modification of 18 7 2 Communication commands p 276 Modification of and Addition to 18 8 2 Cautions on self programming function p 279 Addition of Setting conditions in 3 Operating conditions of WEPRERR flag of 18 8 3 Registers used for self programming function 3 p 280 Addition of description to Figure 18 15 Format of Flash Programming Command Register FLCMD p 281 M...

Page 407: ...ion of Note 3 to Table 3 3 Special Function Registers 1 2 Addition of registers to be used for the self programming function to Table 3 3 Special Function Registers 2 2 CHAPTER 3 CPU ARCHITECTURE Addition of Caution and modification of Remark 2 in Table 4 1 Port Functions Addition of Figure 4 4 Block Diagram of P31 Modification of Figure 4 9 Block Diagram of P43 CHAPTER 4 PORT FUNCTIONS Modificati...

Page 408: ...ication of Figure 9 5 Status Transition Diagram When Low Speed Internal Oscillator Can Be Stopped by Software Is Selected by Option Byte CHAPTER 9 WATCHDOG TIMER Addition of Note to and modification of Figure 10 1 Timing of A D Converter Sampling and A D Conversion Addition of Note 1 Caution and Remark 2 to and modification of Table 10 1 Sampling Time and A D Conversion Time Modification of Figure...

Page 409: ...iming by RESET Input in STOP Mode Addition of registers to be used for self programming function in Table 14 1 Hardware Statuses After Reset Acknowledgment CHAPTER 14 RESET FUNCTION Addition of Note 1 to Figure 16 2 Format of Low Voltage Detect Register LVIM Addition of Note to Figure 16 3 Format of Low Voltage Detection Level Select Register LVIS Addition of Notes 1 and 2 to and modification of F...

Page 410: ...cation of pin header on target system to A 5 1 When using in circuit emulator IE 78K0S NS or IE 78K0S NS A Addition of A 5 2 When using in circuit emulator QB 78K0KX1MINI Modification of system simulator name device file name and Remark in and addition of ID78K0S QB to A 6 Debugging Tools Software APPENDIX A DEVELOPMENT TOOLS Modification of Figure B 1 Distance Between In Circuit Emulator IE 78K0S...

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